[Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in...
authorSonic Zhang <sonic.zhang@analog.com>
Wed, 23 Apr 2008 22:13:37 +0000 (06:13 +0800)
committerBryan Wu <cooloney@kernel.org>
Wed, 23 Apr 2008 22:13:37 +0000 (06:13 +0800)
commitb85b82d980526d683dc3b39f2ac1f447fa84a105
tree116646f10fc37668b4136aa040136354442eeb54
parent253bcf4f9b6dde1cfa169bc29655cf177d6a903b
[Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in link script of kernel

http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3978

Section data_l1_cacheline_aligned should be defined in
link script of kernel, when L1 data sram bank A is not available.

In bf536 with all data cache is enabled, there is no L1 data sram.
Current link script won't define section data_l1.cacheline_aligned in
this case. But, if user select put cacheline_aligned data into l1 sram
in kernel menuconfig, these data will be dropped and access to these
data will trigger data CPLB exception.

Do panic in l1 relocation code as well.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
arch/blackfin/kernel/setup.c
arch/blackfin/kernel/vmlinux.lds.S