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(parent: 081a51c) | patch
rockchip: px5: enable spl-fifo-mode for emmc for px5-evb
authorAndy Yan <andy.yan@rock-chips.com>
Tue, 26 Nov 2019 13:15:39 +0000 (21:15 +0800)
committerKever Yang <kever.yang@rock-chips.com>
Thu, 5 Dec 2019 15:53:07 +0000 (23:53 +0800)
commitafe18f205e269682edd680cb4a5bcbe2094ea58b
tree9ebe883d2b5b3870701e0b1a3220a4bcba013b66tree | snapshot
parent081a51c937952b91957873badafa11ad2a025315commit | diff
rockchip: px5: enable spl-fifo-mode for emmc for px5-evb

We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/dts/rk3368-px5-evb-u-boot.dtsi diff | blob | history
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