MIPS: Fix ISA level which causes secondary cache init bypassing and more
authorDeng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Mon, 1 Apr 2013 18:14:28 +0000 (18:14 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 5 Apr 2013 13:10:45 +0000 (15:10 +0200)
commitadb3789264c4e8567113a0e764ad30ce6e8737f3
tree8cca117e544ee9a6a6586e45ab18b15069bf213e
parented1197f9317c960a199f491779e056c572506dd3
MIPS: Fix ISA level which causes secondary cache init bypassing and more

The commit a96102be70 introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:

if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

This patch fixes it.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/cpu-probe.c
arch/mips/kernel/traps.c
arch/mips/mm/c-r4k.c
arch/mips/mm/sc-mips.c