clk: ti: clk-7xx: Correct ABE DPLL configuration
authorPeter Ujfalusi <peter.ujfalusi@ti.com>
Wed, 2 Apr 2014 13:48:45 +0000 (16:48 +0300)
committerMike Turquette <mturquette@linaro.org>
Thu, 31 Jul 2014 15:36:58 +0000 (08:36 -0700)
commita74c52def9ab953c77956a8e93d225621980f54c
treef84ef30560279ed4eab59f732f345bee34346f04
parent64aa90f26c06e1cb2aacfb98a7d0eccfbd6c1a91
clk: ti: clk-7xx: Correct ABE DPLL configuration

ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/ti/clk-7xx.c