x86/PCI: Moorestown PCI support
authorJesse Barnes <jbarnes@virtuousgeek.org>
Thu, 4 Feb 2010 18:59:27 +0000 (10:59 -0800)
committerH. Peter Anvin <hpa@zytor.com>
Wed, 24 Feb 2010 07:14:47 +0000 (23:14 -0800)
commita712ffbc199849364c46e9112b93b66de08e2c26
treeaf5c32acfcbd84a1069490ed6951e5d3bd7ff079
parent4966e1affb45c5fc402969e10e979407b972a7df
x86/PCI: Moorestown PCI support

The Moorestown platform only has a few devices that actually support
PCI config cycles.  The rest of the devices use an in-RAM MCFG space
for the purposes of device enumeration and initialization.

There are a few uglies in the fake support, like BAR sizes that aren't
a power of two, sizing detection, and writes to the real devices, but
other than that it's pretty straightforward.

Another way to think of this is not really as PCI at all, but just a
table in RAM describing which devices are present, their capabilities
and their offsets in MMIO space.  This could have been done with a
special new firmware table on this platform, but given that we do have
some real PCI devices too, simply describing things in an MCFG type
space was pretty simple.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
LKML-Reference: <43F901BD926A4E43B106BF17856F07559FB80D08@orsmsx508.amr.corp.intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
arch/x86/pci/Makefile
arch/x86/pci/mrst.c [new file with mode: 0644]
include/linux/pci_regs.h