drm/i915: ValleyView mode setting limits and PLL functions
authorJesse Barnes <jbarnes@virtuousgeek.org>
Fri, 15 Jun 2012 18:55:13 +0000 (11:55 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 20 Jun 2012 12:21:23 +0000 (14:21 +0200)
commita0c4da24eafb32a3ce44f37b7c3412c6ffb6e37c
treeb512d984cd6e3745822640edde9fa96af8cceafd
parentcc889e0f6ce6a63c62db17d702ecfed86d58083f
drm/i915: ValleyView mode setting limits and PLL functions

Add some VLV limit structures and update the PLL code.

v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits
v3: re-add dpio write function
v4: squash in Vijay's fixes for the PLL limits and clean up the m/n finder

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c