imx: mx6ul/sx: fix mmdc_ch0 clk calculation
authorPeng Fan <peng.fan@nxp.com>
Wed, 6 Jan 2016 03:06:31 +0000 (11:06 +0800)
committerStefano Babic <sbabic@denx.de>
Sun, 24 Jan 2016 11:13:21 +0000 (12:13 +0100)
commit9ba18ff8efcc471635fb2768509fed025fa7db3c
treee30126c87d2fff657f6cbcf14b37df543dde9194
parent234dc6330126e2c16f45821be9f52862aecda030
imx: mx6ul/sx: fix mmdc_ch0 clk calculation

Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.

Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/include/asm/arch-mx6/crm_regs.h