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(parent: a5ed4fa) | patch
clk: imx: pllv3: add enable_bit
authorGiulio Benetti <giulio.benetti@benettiengineering.com>
Wed, 8 Apr 2020 15:10:07 +0000 (17:10 +0200)
committerStefano Babic <sbabic@denx.de>
Sat, 18 Apr 2020 10:54:43 +0000 (12:54 +0200)
commit8cefbe98b16e756b886ebcbe77ba66e05b9392b4
treea98df4f6e9bc3d893e7a9625e38f7377d40370b0tree | snapshot
parenta5ed4fa95f870d5b1aa4437f1dc9e65f69a58805commit | diff
clk: imx: pllv3: add enable_bit

pllv3 PLLs have powerdown/up bits but enable bits too. Specifically
"enable bit" enable the pll output, so when dis/enabling pll by
setting/clearing power_bit we must also set/clear enable_bit.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
drivers/clk/imx/clk-pllv3.c diff | blob | history
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