powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3
authorYork Sun <yorksun@freescale.com>
Thu, 10 Feb 2011 18:13:10 +0000 (10:13 -0800)
committerKumar Gala <galak@kernel.crashing.org>
Fri, 11 Feb 2011 05:40:02 +0000 (23:40 -0600)
commit856e4b0d7fa366b300bae4f5b9512d7baac6bff1
treededbbaa272786a4f7c87971b5f88864452754892
parentb1d67857af0f66f3def3d0461c141d9b4eccc15e
powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3

When DDR data rate is higher than 1200MT/s or controller interleaving is
enabled, additional cycle for write-to-read turnaround is needed to satisfy
dynamic ODT timing.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h