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[POWERPC] Use cache-inhibited large page bit from firmware
authorPaul Mackerras <paulus@samba.org>
Wed, 3 Oct 2007 04:41:15 +0000 (14:41 +1000)
committerPaul Mackerras <paulus@samba.org>
Tue, 9 Oct 2007 11:00:48 +0000 (21:00 +1000)
commit84fdde5af1eca5ff170d1dff7e2681b0a50a9ecb
tree950f8b4208a76503f3149fc711baedd7b167d068tree | snapshot
parentcd6eed3718b1b32c60a6ee5658ae6341de3177d9commit | diff
[POWERPC] Use cache-inhibited large page bit from firmware

Discussions with firmware architects have confirmed that the bit in
the ibm,pa-features property that indicates support for
cache-inhibited large (>= 64kB) page mappings does in fact mean that
the hypervisor allows 64kB mappings to I/O devices.

Thus we can now enable the code that tests that bit and sets our
CPU_FTR_CI_LARGE_PAGE feature bit.

Signed-off-by: Paul Mackerras <paulus@samba.org>
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