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(parent: a6a0b02) | patch
ARC: HSDK: CGU: fix tunnel clock calculation
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Thu, 16 Apr 2020 19:35:11 +0000 (22:35 +0300)
committerAlexey Brodkin <abrodkin@synopsys.com>
Thu, 16 Apr 2020 20:37:10 +0000 (23:37 +0300)
commit7b50db8242b62c85a19da9521b703faa858f4a63
treef095982dd42ec523bd5f9afca93ba4619440c1c4tree | snapshot
parenta6a0b0244bdded02d69e6493219a88ffd0c79bc8commit | diff
ARC: HSDK: CGU: fix tunnel clock calculation

We set wrong tunnel PLL frequency when we request 125MHz tunnel clock.
Fix that.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
drivers/clk/clk-hsdk-cgu.c diff | blob | history
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