clk: sunxi: Rework MMC phase clocks
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Sun, 7 Dec 2014 16:43:04 +0000 (17:43 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Wed, 14 Jan 2015 09:39:16 +0000 (10:39 +0100)
commit6b0b8ccff002414fab08a080c7a8a6ee3db22c0d
tree608d0cc1f59c46ae0f6afbe88eb0d368a88a606d
parent3ec72fabcc6f4f5c786c50e08b59e1251d0fdfeb
clk: sunxi: Rework MMC phase clocks

Instead of having three different clocks for the main MMC clock and the two
phase sub-clocks, which involved having three different drivers sharing the
same register, rework it to have the same single driver registering three
different clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Documentation/devicetree/bindings/clock/sunxi.txt
drivers/clk/sunxi/clk-mod0.c