ARM: mm: use inner-shareable barriers for TLB and user cache operations
authorWill Deacon <will.deacon@arm.com>
Mon, 13 May 2013 11:01:12 +0000 (12:01 +0100)
committerWill Deacon <will.deacon@arm.com>
Mon, 12 Aug 2013 11:25:45 +0000 (12:25 +0100)
commit6abdd491698a27f7df04a32ca12cc453810e4396
tree34f4aa721441439634e721fe0eeba614b076a889
parent62cbbc42e0019aff6310259f275ae812463f8836
ARM: mm: use inner-shareable barriers for TLB and user cache operations

System-wide barriers aren't required for situations where we only need
to make visibility and ordering guarantees in the inner-shareable domain
(i.e. we are not dealing with devices or potentially incoherent CPUs).

This patch changes the v7 TLB operations, coherent_user_range and
dcache_clean_area functions to user inner-shareable barriers. For cache
maintenance, only the store access type is required to ensure completion.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm/mm/cache-v7.S
arch/arm/mm/proc-v7.S
arch/arm/mm/tlb-v7.S