ARM: ux500: select L2X0 cache on ux500
authorArnd Bergmann <arnd@arndb.de>
Sat, 25 Feb 2012 19:48:52 +0000 (12:48 -0700)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 29 Feb 2012 16:09:10 +0000 (17:09 +0100)
commit68526e586307faadc49c27406dad3cb93f067eb0
tree130b84018c10f4b18c961fae087f9a8a7c7f899f
parentded547a443723f0f29bce513356fe10f96cae315
ARM: ux500: select L2X0 cache on ux500

The cache controller needs to be enabled for the
cortex-a9 specific errata that are also selected
to work.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
arch/arm/mach-ux500/Kconfig