perf events, x86: Fix Intel Nehalem and Westmere last level cache event definitions
authorPeter Zijlstra <peterz@infradead.org>
Fri, 22 Apr 2011 22:57:42 +0000 (00:57 +0200)
committerIngo Molnar <mingo@elte.hu>
Fri, 6 May 2011 09:24:48 +0000 (11:24 +0200)
commit63b6a6758eede2f9283c3594265b6e32e75d7456
treef57561ee0ae40e084dea56ba79439e563071a9d9
parent925f83c085e1bb08435556c5b4844a60de002e31
perf events, x86: Fix Intel Nehalem and Westmere last level cache event definitions

The Intel Nehalem offcore bits implemented in:

  e994d7d23a0b: perf: Fix LLC-* events on Intel Nehalem/Westmere

... are wrong: they implemented _ACCESS as _HIT and counted OTHER_CORE_HIT* as
MISS even though its clearly documented as an L3 hit ...

Fix them and the Westmere definitions as well.

Cc: Andi Kleen <ak@linux.intel.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Steven Rostedt <rostedt@goodmis.org>
Link: http://lkml.kernel.org/r/1299119690-13991-3-git-send-email-ming.m.lin@intel.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_event_intel.c