drm/i915: Enforce write ordering through the GTT
authorChris Wilson <chris@chris-wilson.co.uk>
Tue, 4 Jan 2011 18:42:07 +0000 (18:42 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 11 Jan 2011 20:42:53 +0000 (20:42 +0000)
commit63256ec5347fb2344a42adbae732b90603c92f35
tree5b018e93f38f9e90f3b07beeaac4af08122c5876
parent759010728b1323aec03c5baae13fde8f76e44a99
drm/i915: Enforce write ordering through the GTT

We need to ensure that writes through the GTT land before any
modification to the MMIO registers and so must impose a mandatory write
barrier when flushing the GTT domain. This was revealed by relaxing the
write ordering by experimentally mapping the registers and the GATT as
write-combining.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_execbuffer.c