perf/x86: Add constraint for IVB CYCLE_ACTIVITY:CYCLES_LDM_PENDING
authorStephane Eranian <eranian@google.com>
Wed, 11 Sep 2013 15:22:22 +0000 (08:22 -0700)
committerIngo Molnar <mingo@kernel.org>
Thu, 12 Sep 2013 05:58:26 +0000 (07:58 +0200)
commit6113af14c82726d5a2993a7ba238df24c990a5ee
treed090c0da090da61a81a9a2bb037cbbe9a66250de
parente6d381834d8384b3da570e05b1518db4e2b3d92b
perf/x86: Add constraint for IVB CYCLE_ACTIVITY:CYCLES_LDM_PENDING

The IvyBridge event CYCLE_ACTIVITY:CYCLES_LDM_PENDING can only
be measured on counters 0-3 when HT is off. When HT is on, you
only have counters 0-3.

If you program it on the eight counters for 1s on a 3GHz
IVB laptop running a noploop, you see:

           2 747 527 CYCLE_ACTIVITY:CYCLES_LDM_PENDING
           2 747 527 CYCLE_ACTIVITY:CYCLES_LDM_PENDING
           2 747 527 CYCLE_ACTIVITY:CYCLES_LDM_PENDING
           2 747 527 CYCLE_ACTIVITY:CYCLES_LDM_PENDING
       3 280 563 608 CYCLE_ACTIVITY:CYCLES_LDM_PENDING
       3 280 563 608 CYCLE_ACTIVITY:CYCLES_LDM_PENDING
       3 280 563 608 CYCLE_ACTIVITY:CYCLES_LDM_PENDING
       3 280 563 608 CYCLE_ACTIVITY:CYCLES_LDM_PENDING

Clearly the last 4 values are bogus.

Signed-off-by: Stephane Eranian <eranian@google.com>
Cc: peterz@infradead.org
Cc: ak@linux.intel.com
Cc: zheng.z.yan@intel.com
Cc: dhsharp@google.com
Link: http://lkml.kernel.org/r/20130911152222.GA28761@google.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event_intel.c