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(parent: caad316) | patch
riscv: ax25: cache: Remove SPL_RISCV_MMODE config check
authorPragnesh Patel <pragnesh.patel@sifive.com>
Sat, 14 Mar 2020 13:42:28 +0000 (19:12 +0530)
committerAndes <uboot@andestech.com>
Thu, 23 Apr 2020 02:13:23 +0000 (10:13 +0800)
commit5988bb9dbf6a22c7a14efa67094ac98ca0c965e8
tree209a1a3ef63aa81ca0601b1410d94e9c8c843ebatree | snapshot
parentcaad316b3165615f1a4848901811a4a084444c9dcommit | diff
riscv: ax25: cache: Remove SPL_RISCV_MMODE config check

CONFIG_IS_ENABLED(FOO) will check FOO config option for U-Boot,
SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
arch/riscv/cpu/ax25/cache.c diff | blob | history
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