drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush'
authorAkash Goel <akash.goel@intel.com>
Fri, 4 Apr 2014 11:44:38 +0000 (17:14 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 9 Apr 2014 12:37:09 +0000 (14:37 +0200)
commit4e04632e882719e46edcbbc0b76fad778a0ed845
tree6ad57dc1883be6f750f3da27ffa7f1ef0ca6fa4b
parent8cbf3202098f191f8b0a0606b2df0af047f21fe5
drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush'

On Gen4+ platforms (except BDW), Render Cache Operational flush
cannot be enabled.
This WA is apparently required for all Gen4+ platforms,except BDW.
In BDW, the bit has been repurposed otherwise.
This has been tested only on vlv.

v2: Corrected the code regarding the wrong usage of
MASKED_BIT_DISABLE (Chris)

v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville)

v4: Adding WA for g4x, crestline, broadwater (Ville)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c