OMAP4460: TPS Ensure SET1 is selected after voltage configuration
authorNishanth Menon <nm@ti.com>
Thu, 1 Mar 2012 14:17:38 +0000 (14:17 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 15 May 2012 06:31:22 +0000 (08:31 +0200)
commit3acb553439e3ee9f62f022f96f949c21811f8bdf
tree769d474b7aa9976bf1835938eafdac7d15fd090c
parenta78274b2050dcacc29561f4e35bdc91b896578cd
OMAP4460: TPS Ensure SET1 is selected after voltage configuration

TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
                           |---------------| (SET1 default 1.4V)
                           |               --------(programmed voltage)
                           | <- (This switch happens on mux7,pullup)
vdd_mpu(TPS)         -----/ (OPP boot voltage)
                                             --------- (programmed voltage)
vdd_core(TWL6030)    -----------------------/ (OPP boot voltage)
Problem 1)                |<----- Tx ------>|
   timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.

By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
                                  -------- (programmed voltage)
vdd_mpu(TPS)         ------------/ (Opp boot voltage)
                                   --------- (programmed voltage)
vdd_core(TWL6030)    -------------/ (OPP boot voltage)

NOTE: This does not attempt to address OMAP5 - Aneesh please confirm

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap4/clocks.c
arch/arm/cpu/armv7/omap5/clocks.c
arch/arm/include/asm/arch-omap4/clocks.h
arch/arm/include/asm/arch-omap5/clocks.h
board/ti/panda/panda_mux_data.h
board/ti/sdp4430/sdp4430_mux_data.h