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(parent: 796d1f4) | patch
clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain
authorTomasz Figa <t.figa@samsung.com>
Tue, 15 Oct 2013 17:41:18 +0000 (19:41 +0200)
committerTomasz Figa <t.figa@samsung.com>
Mon, 30 Dec 2013 17:15:48 +0000 (18:15 +0100)
commit3818f11740bbf87ad76f4f502f6739c8d62e5c17
tree19cc5c3a76f11607db73d0bf500ea4da0f788de9tree | snapshot
parent796d1f4cd62500ee55a645f2649b546710b11bd1commit | diff
clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain

This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
drivers/clk/samsung/clk-exynos5250.c diff | blob | history
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