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(parent: ad8d270) | patch
drm/i915: Rename I915_CACHE_MLC_LLC to L3_LLC for Ivybridge
authorChris Wilson <chris@chris-wilson.co.uk>
Tue, 6 Aug 2013 12:17:02 +0000 (13:17 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 6 Aug 2013 14:35:30 +0000 (16:35 +0200)
commit350ec881d966453bdcf1d3299071e90da4e507b4
tree6a527acf2968da235bf6d8b0906efcbf7107b5d9tree | snapshot
parentad8d270c21aa2f57f0cd578b1737f65c44c34b80commit | diff
drm/i915: Rename I915_CACHE_MLC_LLC to L3_LLC for Ivybridge

MLC_LLC was never validated for Sandybridge and was superseded by a new
level of cacheing for the GPU in Ivybridge. Update our names to be
consistent with usage, and in the process stop setting the unwanted bit
on Sandybridge.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: s/BUG/WARN_ON(1) bikeshed.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h diff | blob | history
drivers/gpu/drm/i915/i915_gem_context.c diff | blob | history
drivers/gpu/drm/i915/i915_gem_gtt.c diff | blob | history
drivers/gpu/drm/i915/i915_gpu_error.c diff | blob | history
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