arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs
authorChristoffer Dall <christoffer.dall@linaro.org>
Sun, 28 Sep 2014 14:04:26 +0000 (16:04 +0200)
committerChristoffer Dall <christoffer.dall@linaro.org>
Thu, 16 Oct 2014 08:57:41 +0000 (10:57 +0200)
commit2df36a5dd6792870bef48f63bfca42055ea5b79c
treeef822d51fb8cd4adb030eab48c7dab131b632461
parent3d08c629244257473450a8ba17cb8184b91e68f8
arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs

The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we
store these as an array of two such registers on the vgic vcpu struct.
However, we access them as a single 64-bit value or as a bitmap pointer
in the generic vgic code, which breaks BE support.

Instead, store them as u64 values on the vgic structure and do the
word-swapping in the assembly code, which already handles the byte order
for BE systems.

Tested-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
arch/arm/kvm/interrupts_head.S
arch/arm64/kvm/vgic-v2-switch.S
include/kvm/arm_vgic.h
virt/kvm/arm/vgic-v2.c
virt/kvm/arm/vgic.c