powerpc/perf: Fix instruction address sampling on 970 and Power4
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Mon, 26 Mar 2012 20:47:34 +0000 (20:47 +0000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Wed, 28 Mar 2012 00:33:24 +0000 (11:33 +1100)
commit1ce447b90f3e71c81ae59e0062bc305ef267668b
tree516f26debf251a7aa1538f72710f956b95a2f05c
parentcb52d8970eee65bf2c47d9a91bd4f58b17f595f4
powerpc/perf: Fix instruction address sampling on 970 and Power4

970 and Power4 don't support "continuous sampling" which means that
when we aren't in marked instruction sampling mode (marked events),
SIAR isn't updated with the last instruction sampled before the
perf interrupt. On those processors, we must thus use the exception
SRR0 value as the sampled instruction pointer.

Those processors also don't support the SIPR and SIHV bits in MMCRA
which means we need some kind of heuristic to decide if SIAR values
represent kernel or user addresses.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/include/asm/perf_event_server.h
arch/powerpc/perf/core-book3s.c
arch/powerpc/perf/power4-pmu.c
arch/powerpc/perf/ppc970-pmu.c