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(parent: 774ec60) | patch
imx: Add PHYTEC phyBOARD-i.MX6UL-Segin
authorMartyn Welch <martyn@welchs.me.uk>
Tue, 11 Dec 2018 11:34:46 +0000 (11:34 +0000)
committerStefano Babic <sbabic@denx.de>
Mon, 28 Jan 2019 11:47:27 +0000 (12:47 +0100)
commit0963060c9912c404280e5540018d02777b3400af
treee7731f4076e5294feaf8f98d4287e9f1538d2dabtree | snapshot
parent774ec60b74a7b8d356a2ec6249936b097631a726commit | diff
imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).

CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:    serial
Out:   serial
Err:   serial
Net:   FEC0

Working:
 - Eth0
 - i2C
 - MMC/SD
 - NAND
 - UART (1 & 5)
 - USB (host & otg)

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
12 files changed:
arch/arm/dts/Makefile diff | blob | history
arch/arm/dts/imx6ul-pcl063.dtsi [new file with mode: 0644] blob
arch/arm/dts/imx6ul-phycore-segin.dts [new file with mode: 0644] blob
arch/arm/mach-imx/mx6/Kconfig diff | blob | history
board/phytec/pcl063/Kconfig [new file with mode: 0644] blob
board/phytec/pcl063/MAINTAINERS [new file with mode: 0644] blob
board/phytec/pcl063/Makefile [new file with mode: 0644] blob
board/phytec/pcl063/README [new file with mode: 0644] blob
board/phytec/pcl063/pcl063.c [new file with mode: 0644] blob
board/phytec/pcl063/spl.c [new file with mode: 0644] blob
configs/phycore_pcl063_defconfig [new file with mode: 0644] blob
include/configs/pcl063.h [new file with mode: 0644] blob
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