drm/i915/chv: Trigger phy common lane reset
authorChon Ming Lee <chon.ming.lee@intel.com>
Wed, 9 Apr 2014 10:28:17 +0000 (13:28 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 12 May 2014 17:50:13 +0000 (19:50 +0200)
commit076ed3b2955e5934e137abff39fe9e7180f236fe
tree4a963817c4b3ade8f78964094f7f7c35b92a0cec
parenteb69b0e59ac845666b7b284ca83a1fef17ebaa9f
drm/i915/chv: Trigger phy common lane reset

During cold boot, the display controller needs to deassert the common
lane reset.  Only do it once during intel_init_dpio for both PHYx2 and
PHYx1.

Besides, assert the common lane reset when disable pll.  This still
to be determined whether need to do it by driver.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[vsyrjala: Don't disable DPIO PLL when using DSI]
[vsyrjala: Don't call vlv_disable_pll() by accident on CHV]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[danvet: Move part of a moved comment back as suggested by Imre since
it's valid for both byt and chv.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c