#define OMAP44XX_CTRL_ID_CODE (OMAP44XX_CTRL_GEN_CORE_BASE + 0x204)
#define OMAP44XX_CTRL_BASE 0x4a100000
+#define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000
+
+/* DDR */
+#define OMAP44XX_CONTROL_LPDDR2IO1_0 (OMAP44XX_CTRL_BASE + 0x638)
+#define OMAP44XX_CONTROL_LPDDR2IO1_1 (OMAP44XX_CTRL_BASE + 0x63c)
+#define OMAP44XX_CONTROL_LPDDR2IO1_2 (OMAP44XX_CTRL_BASE + 0x640)
+#define OMAP44XX_CONTROL_LPDDR2IO1_3 (OMAP44XX_CTRL_BASE + 0x644)
+#define OMAP44XX_CONTROL_LPDDR2IO2_0 (OMAP44XX_CTRL_BASE + 0x648)
+#define OMAP44XX_CONTROL_LPDDR2IO2_1 (OMAP44XX_CTRL_BASE + 0x64c)
+#define OMAP44XX_CONTROL_LPDDR2IO2_2 (OMAP44XX_CTRL_BASE + 0x650)
+#define OMAP44XX_CONTROL_LPDDR2IO2_3 (OMAP44XX_CTRL_BASE + 0x654)
+
+/* eFUSE */
+#define OMAP44XX_CONTROL_EFUSE_1 (OMAP44XX_CTRL_BASE + 0x700)
+#define OMAP44XX_CONTROL_EFUSE_2 (OMAP44XX_CTRL_BASE + 0x704)
+#define OMAP44XX_CONTROL_EFUSE_3 (OMAP44XX_CTRL_BASE + 0x708)
+#define OMAP44XX_CONTROL_EFUSE_4 (OMAP44XX_CTRL_BASE + 0x70c)
+
+/* PRM */
+#define OMAP44XX_PRM_VC_VAL_BYPASS (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba0)
+#define OMAP44XX_PRM_VC_CFG_I2C_MODE (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7ba8)
+#define OMAP44XX_PRM_VC_CFG_I2C_CLK (OMAP44XX_WAKEUP_L4_IO_BASE + 0x7bac)
+
+/* IRQ */
+#define OMAP44XX_PRM_IRQSTATUS_MPU_A9 (OMAP44XX_WAKEUP_L4_IO_BASE + 0x6010)
+
+
/* TAP information dont know for 3430*/
#define OMAP44XX_TAP_BASE (0x49000000) /*giving some junk for virtio */
#define OMAP44XX_GPIO_BASE1 0x4a310000
#define OMAP44XX_GPIO_BASE2 0x48055000
+#define OMAP44XX_GPIO_BASE6 0x4805D000
+
+/* common GPIO offsets */
+
+#define __GPIO_REVISION 0
+#define __GPIO_SYSCONFIG 0x10
+#define __GPIO_IRQSTATUS_RAW_0 0x24
+#define __GPIO_IRQSTATUS_RAW_1 0x28
+#define __GPIO_IRQSTATUS_0 0x2c
+#define __GPIO_IRQSTATUS_1 0x30
+#define __GPIO_IRQSTATUS_SET_0 0x34
+#define __GPIO_IRQSTATUS_SET_1 0x38
+#define __GPIO_IRQSTATUS_CLR_0 0x3c
+#define __GPIO_IRQSTATUS_CLR_1 0x40
+#define __GPIO_IRQWAKEN_0 0x44
+#define __GPIO_IRQWAKEN_1 0x48
+#define __GPIO_SYSSTATUS 0x114
+#define __GPIO_IRQSTATUS1 0x118
+#define __GPIO_CTRL 0x130
+#define __GPIO_OE 0x134
+#define __GPIO_DATAIN 0x138
+#define __GPIO_DATAOUT 0x13c
+
+/* SCRM */
+
+#define OMAP44XX_SCRM_BASE 0x4a30a000
+
+#define OMAP44XX_SCRM_ALTCLKSRC (OMAP44XX_SCRM_BASE + 0x110)
+#define OMAP44XX_SCRM_AUXCLK1 (OMAP44XX_SCRM_BASE + 0x314)
+#define OMAP44XX_SCRM_AUXCLK3 (OMAP44XX_SCRM_BASE + 0x31c)
+
+
/* 32KTIMER */
#define SYNC_32KTIMER_BASE (0x48320000)
#define S32K_CR (SYNC_32KTIMER_BASE+0x10)