2 * Fifo-attached Serial Interface (FSI) support for SH7724
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
23 #define DOFF_CTL 0x0004
24 #define DOFF_ST 0x0008
26 #define DIFF_CTL 0x0010
27 #define DIFF_ST 0x0014
32 #define MUTE_ST 0x0028
33 #define OUT_SEL 0x0030
34 #define REG_END OUT_SEL
36 #define A_MST_CTLR 0x0180
37 #define B_MST_CTLR 0x01A0
38 #define CPU_INT_ST 0x01F4
39 #define CPU_IEMSK 0x01F8
40 #define CPU_IMSK 0x01FC
45 #define CLK_RST 0x0210
46 #define SOFT_RST 0x0214
47 #define FIFO_SZ 0x0218
48 #define MREG_START A_MST_CTLR
49 #define MREG_END FIFO_SZ
53 #define CR_MONO (0x0 << 4)
54 #define CR_MONO_D (0x1 << 4)
55 #define CR_PCM (0x2 << 4)
56 #define CR_I2S (0x3 << 4)
57 #define CR_TDM (0x4 << 4)
58 #define CR_TDM_D (0x5 << 4)
59 #define CR_SPDIF 0x00100120
63 #define IRQ_HALF 0x00100000
64 #define FIFO_CLR 0x00000001
67 #define ERR_OVER 0x00000010
68 #define ERR_UNDER 0x00000001
69 #define ST_ERR (ERR_OVER | ERR_UNDER)
72 #define ACKMD_MASK 0x00007000
73 #define BPFMD_MASK 0x00000700
76 #define BP (1 << 4) /* Fix the signal of Biphase output */
77 #define SE (1 << 0) /* Fix the master clock */
80 #define B_CLK 0x00000010
81 #define A_CLK 0x00000001
84 #define INT_B_IN (1 << 12)
85 #define INT_B_OUT (1 << 8)
86 #define INT_A_IN (1 << 4)
87 #define INT_A_OUT (1 << 0)
90 #define PBSR (1 << 12) /* Port B Software Reset */
91 #define PASR (1 << 8) /* Port A Software Reset */
92 #define IR (1 << 4) /* Interrupt Reset */
93 #define FSISR (1 << 0) /* Software Reset */
96 #define OUT_SZ_MASK 0x7
100 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
102 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
105 * FSI driver use below type name for variable
107 * xxx_len : data length
108 * xxx_width : data width
109 * xxx_offset : data offset
110 * xxx_num : number of data
119 struct snd_pcm_substream *substream;
120 struct fsi_master *master;
144 struct fsi_priv fsia;
145 struct fsi_priv fsib;
146 struct fsi_core *core;
147 struct sh_fsi_platform_info *info;
152 * basic read write function
155 static void __fsi_reg_write(u32 reg, u32 data)
157 /* valid data area is 24bit */
160 __raw_writel(data, reg);
163 static u32 __fsi_reg_read(u32 reg)
165 return __raw_readl(reg);
168 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
170 u32 val = __fsi_reg_read(reg);
175 __fsi_reg_write(reg, val);
178 static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
181 pr_err("fsi: register access err (%s)\n", __func__);
185 __fsi_reg_write((u32)(fsi->base + reg), data);
188 static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
191 pr_err("fsi: register access err (%s)\n", __func__);
195 return __fsi_reg_read((u32)(fsi->base + reg));
198 static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
201 pr_err("fsi: register access err (%s)\n", __func__);
205 __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
208 static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data)
212 if ((reg < MREG_START) ||
214 pr_err("fsi: register access err (%s)\n", __func__);
218 spin_lock_irqsave(&master->lock, flags);
219 __fsi_reg_write((u32)(master->base + reg), data);
220 spin_unlock_irqrestore(&master->lock, flags);
223 static u32 fsi_master_read(struct fsi_master *master, u32 reg)
228 if ((reg < MREG_START) ||
230 pr_err("fsi: register access err (%s)\n", __func__);
234 spin_lock_irqsave(&master->lock, flags);
235 ret = __fsi_reg_read((u32)(master->base + reg));
236 spin_unlock_irqrestore(&master->lock, flags);
241 static void fsi_master_mask_set(struct fsi_master *master,
242 u32 reg, u32 mask, u32 data)
246 if ((reg < MREG_START) ||
248 pr_err("fsi: register access err (%s)\n", __func__);
252 spin_lock_irqsave(&master->lock, flags);
253 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
254 spin_unlock_irqrestore(&master->lock, flags);
261 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
266 static int fsi_is_port_a(struct fsi_priv *fsi)
268 return fsi->master->base == fsi->base;
271 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
273 struct snd_soc_pcm_runtime *rtd = substream->private_data;
278 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
280 struct snd_soc_dai *dai = fsi_get_dai(substream);
281 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
284 return &master->fsia;
286 return &master->fsib;
289 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
291 int is_porta = fsi_is_port_a(fsi);
292 struct fsi_master *master = fsi_get_master(fsi);
294 return is_porta ? master->info->porta_flags :
295 master->info->portb_flags;
298 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
301 u32 flags = fsi_get_info_flags(fsi);
303 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
310 return (mode & flags) != mode;
313 static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play)
315 int is_porta = fsi_is_port_a(fsi);
319 data = is_play ? (1 << 0) : (1 << 4);
321 data = is_play ? (1 << 8) : (1 << 12);
326 static void fsi_stream_push(struct fsi_priv *fsi,
327 struct snd_pcm_substream *substream,
331 fsi->substream = substream;
332 fsi->buff_len = buffer_len;
333 fsi->buff_offset = 0;
334 fsi->period_len = period_len;
338 static void fsi_stream_pop(struct fsi_priv *fsi)
340 fsi->substream = NULL;
342 fsi->buff_offset = 0;
347 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
350 u32 reg = is_play ? DOFF_ST : DIFF_ST;
353 status = fsi_reg_read(fsi, reg);
354 data_num = 0x1ff & (status >> 8);
355 data_num *= fsi->chan_num;
360 static int fsi_len2num(int len, int width)
365 #define fsi_num2offset(a, b) fsi_num2len(a, b)
366 static int fsi_num2len(int num, int width)
375 static u8 *fsi_dma_get_area(struct fsi_priv *fsi)
377 return fsi->substream->runtime->dma_area + fsi->buff_offset;
380 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
385 start = (u16 *)fsi_dma_get_area(fsi);
387 for (i = 0; i < num; i++)
388 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
391 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
396 start = (u16 *)fsi_dma_get_area(fsi);
398 for (i = 0; i < num; i++)
399 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
402 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
407 start = (u32 *)fsi_dma_get_area(fsi);
409 for (i = 0; i < num; i++)
410 fsi_reg_write(fsi, DODT, *(start + i));
413 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
418 start = (u32 *)fsi_dma_get_area(fsi);
420 for (i = 0; i < num; i++)
421 *(start + i) = fsi_reg_read(fsi, DIDT);
428 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
430 u32 data = fsi_port_ab_io_bit(fsi, is_play);
431 struct fsi_master *master = fsi_get_master(fsi);
433 fsi_master_mask_set(master, master->core->imsk, data, data);
434 fsi_master_mask_set(master, master->core->iemsk, data, data);
437 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
439 u32 data = fsi_port_ab_io_bit(fsi, is_play);
440 struct fsi_master *master = fsi_get_master(fsi);
442 fsi_master_mask_set(master, master->core->imsk, data, 0);
443 fsi_master_mask_set(master, master->core->iemsk, data, 0);
446 static u32 fsi_irq_get_status(struct fsi_master *master)
448 return fsi_master_read(master, master->core->int_st);
451 static void fsi_irq_clear_all_status(struct fsi_master *master)
453 fsi_master_write(master, master->core->int_st, 0);
456 static void fsi_irq_clear_status(struct fsi_priv *fsi)
459 struct fsi_master *master = fsi_get_master(fsi);
461 data |= fsi_port_ab_io_bit(fsi, 0);
462 data |= fsi_port_ab_io_bit(fsi, 1);
464 /* clear interrupt factor */
465 fsi_master_mask_set(master, master->core->int_st, data, 0);
469 * SPDIF master clock function
471 * These functions are used later FSI2
473 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
475 struct fsi_master *master = fsi_get_master(fsi);
478 if (master->core->ver < 2) {
479 pr_err("fsi: register access err (%s)\n", __func__);
484 fsi_master_mask_set(master, fsi->mst_ctrl, val, val);
486 fsi_master_mask_set(master, fsi->mst_ctrl, val, 0);
493 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
495 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
496 struct fsi_master *master = fsi_get_master(fsi);
499 fsi_master_mask_set(master, CLK_RST, val, val);
501 fsi_master_mask_set(master, CLK_RST, val, 0);
504 static void fsi_fifo_init(struct fsi_priv *fsi,
506 struct snd_soc_dai *dai)
508 struct fsi_master *master = fsi_get_master(fsi);
511 /* get on-chip RAM capacity */
512 shift = fsi_master_read(master, FIFO_SZ);
513 shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT;
514 shift &= OUT_SZ_MASK;
515 fsi->fifo_max_num = 256 << shift;
516 dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max_num);
519 * The maximum number of sample data varies depending
520 * on the number of channels selected for the format.
522 * FIFOs are used in 4-channel units in 3-channel mode
523 * and in 8-channel units in 5- to 7-channel mode
524 * meaning that more FIFOs than the required size of DPRAM
527 * ex) if 256 words of DP-RAM is connected
528 * 1 channel: 256 (256 x 1 = 256)
529 * 2 channels: 128 (128 x 2 = 256)
530 * 3 channels: 64 ( 64 x 3 = 192)
531 * 4 channels: 64 ( 64 x 4 = 256)
532 * 5 channels: 32 ( 32 x 5 = 160)
533 * 6 channels: 32 ( 32 x 6 = 192)
534 * 7 channels: 32 ( 32 x 7 = 224)
535 * 8 channels: 32 ( 32 x 8 = 256)
537 for (i = 1; i < fsi->chan_num; i <<= 1)
538 fsi->fifo_max_num >>= 1;
539 dev_dbg(dai->dev, "%d channel %d store\n",
540 fsi->chan_num, fsi->fifo_max_num);
542 ctrl = is_play ? DOFF_CTL : DIFF_CTL;
544 /* set interrupt generation factor */
545 fsi_reg_write(fsi, ctrl, IRQ_HALF);
548 fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
551 static void fsi_soft_all_reset(struct fsi_master *master)
554 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
558 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
559 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
563 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int is_play)
565 struct snd_pcm_runtime *runtime;
566 struct snd_pcm_substream *substream = NULL;
568 u32 status_reg = is_play ? DOFF_ST : DIFF_ST;
569 int data_residue_num;
574 void (*fn)(struct fsi_priv *fsi, int size);
578 !fsi->substream->runtime)
582 substream = fsi->substream;
583 runtime = substream->runtime;
585 /* FSI FIFO has limit.
586 * So, this driver can not send periods data at a time
588 if (fsi->buff_offset >=
589 fsi_num2offset(fsi->period_num + 1, fsi->period_len)) {
592 fsi->period_num = (fsi->period_num + 1) % runtime->periods;
594 if (0 == fsi->period_num)
595 fsi->buff_offset = 0;
598 /* get 1 channel data width */
599 ch_width = frames_to_bytes(runtime, 1) / fsi->chan_num;
601 /* get residue data number of alsa */
602 data_residue_num = fsi_len2num(fsi->buff_len - fsi->buff_offset,
609 * data_num_max : number of FSI fifo free space
610 * data_num : number of ALSA residue data
612 data_num_max = fsi->fifo_max_num * fsi->chan_num;
613 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
615 data_num = data_residue_num;
619 fn = fsi_dma_soft_push16;
622 fn = fsi_dma_soft_push32;
631 * data_num_max : number of ALSA free space
632 * data_num : number of data in FSI fifo
634 data_num_max = data_residue_num;
635 data_num = fsi_get_fifo_data_num(fsi, is_play);
639 fn = fsi_dma_soft_pop16;
642 fn = fsi_dma_soft_pop32;
649 data_num = min(data_num, data_num_max);
653 /* update buff_offset */
654 fsi->buff_offset += fsi_num2offset(data_num, ch_width);
656 /* check fifo status */
657 status = fsi_reg_read(fsi, status_reg);
659 struct snd_soc_dai *dai = fsi_get_dai(substream);
661 if (status & ERR_OVER)
662 dev_err(dai->dev, "over run\n");
663 if (status & ERR_UNDER)
664 dev_err(dai->dev, "under run\n");
666 fsi_reg_write(fsi, status_reg, 0);
669 fsi_irq_enable(fsi, is_play);
672 snd_pcm_period_elapsed(substream);
677 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
679 return fsi_fifo_data_ctrl(fsi, startup, 0);
682 static int fsi_data_push(struct fsi_priv *fsi, int startup)
684 return fsi_fifo_data_ctrl(fsi, startup, 1);
687 static irqreturn_t fsi_interrupt(int irq, void *data)
689 struct fsi_master *master = data;
690 u32 int_st = fsi_irq_get_status(master);
692 /* clear irq status */
693 fsi_master_mask_set(master, SOFT_RST, IR, 0);
694 fsi_master_mask_set(master, SOFT_RST, IR, IR);
696 if (int_st & INT_A_OUT)
697 fsi_data_push(&master->fsia, 0);
698 if (int_st & INT_B_OUT)
699 fsi_data_push(&master->fsib, 0);
700 if (int_st & INT_A_IN)
701 fsi_data_pop(&master->fsia, 0);
702 if (int_st & INT_B_IN)
703 fsi_data_pop(&master->fsib, 0);
705 fsi_irq_clear_all_status(master);
714 static int fsi_dai_startup(struct snd_pcm_substream *substream,
715 struct snd_soc_dai *dai)
717 struct fsi_priv *fsi = fsi_get_priv(substream);
718 u32 flags = fsi_get_info_flags(fsi);
719 struct fsi_master *master = fsi_get_master(fsi);
723 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
727 pm_runtime_get_sync(dai->dev);
730 data = is_play ? (1 << 0) : (1 << 4);
731 is_master = fsi_is_master_mode(fsi, is_play);
733 fsi_reg_mask_set(fsi, CKG1, data, data);
735 fsi_reg_mask_set(fsi, CKG1, data, 0);
737 /* clock inversion (CKG2) */
739 if (SH_FSI_LRM_INV & flags)
741 if (SH_FSI_BRM_INV & flags)
743 if (SH_FSI_LRS_INV & flags)
745 if (SH_FSI_BRS_INV & flags)
748 fsi_reg_write(fsi, CKG2, data);
752 reg = is_play ? DO_FMT : DI_FMT;
753 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
755 case SH_FSI_FMT_MONO:
759 case SH_FSI_FMT_MONO_DELAY:
772 fsi->chan_num = is_play ?
773 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
774 data = CR_TDM | (fsi->chan_num - 1);
776 case SH_FSI_FMT_TDM_DELAY:
777 fsi->chan_num = is_play ?
778 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
779 data = CR_TDM_D | (fsi->chan_num - 1);
781 case SH_FSI_FMT_SPDIF:
782 if (master->core->ver < 2) {
783 dev_err(dai->dev, "This FSI can not use SPDIF\n");
788 fsi_spdif_clk_ctrl(fsi, 1);
789 fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010);
792 dev_err(dai->dev, "unknown format.\n");
795 fsi_reg_write(fsi, reg, data);
798 fsi_irq_disable(fsi, is_play);
799 fsi_irq_clear_status(fsi);
802 fsi_fifo_init(fsi, is_play, dai);
807 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
808 struct snd_soc_dai *dai)
810 struct fsi_priv *fsi = fsi_get_priv(substream);
811 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
813 fsi_irq_disable(fsi, is_play);
814 fsi_clk_ctrl(fsi, 0);
816 pm_runtime_put_sync(dai->dev);
819 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
820 struct snd_soc_dai *dai)
822 struct fsi_priv *fsi = fsi_get_priv(substream);
823 struct snd_pcm_runtime *runtime = substream->runtime;
824 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
828 case SNDRV_PCM_TRIGGER_START:
829 fsi_stream_push(fsi, substream,
830 frames_to_bytes(runtime, runtime->buffer_size),
831 frames_to_bytes(runtime, runtime->period_size));
832 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
834 case SNDRV_PCM_TRIGGER_STOP:
835 fsi_irq_disable(fsi, is_play);
843 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
844 struct snd_pcm_hw_params *params,
845 struct snd_soc_dai *dai)
847 struct fsi_priv *fsi = fsi_get_priv(substream);
848 struct fsi_master *master = fsi_get_master(fsi);
849 int (*set_rate)(int is_porta, int rate) = master->info->set_rate;
850 int fsi_ver = master->core->ver;
851 int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
854 /* if slave mode, set_rate is not needed */
855 if (!fsi_is_master_mode(fsi, is_play))
858 /* it is error if no set_rate */
862 ret = set_rate(fsi_is_port_a(fsi), params_rate(params));
866 switch (ret & SH_FSI_ACKMD_MASK) {
869 case SH_FSI_ACKMD_512:
872 case SH_FSI_ACKMD_256:
875 case SH_FSI_ACKMD_128:
878 case SH_FSI_ACKMD_64:
881 case SH_FSI_ACKMD_32:
883 dev_err(dai->dev, "unsupported ACKMD\n");
889 switch (ret & SH_FSI_BPFMD_MASK) {
892 case SH_FSI_BPFMD_32:
895 case SH_FSI_BPFMD_64:
898 case SH_FSI_BPFMD_128:
901 case SH_FSI_BPFMD_256:
904 case SH_FSI_BPFMD_512:
907 case SH_FSI_BPFMD_16:
909 dev_err(dai->dev, "unsupported ACKMD\n");
915 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
917 fsi_clk_ctrl(fsi, 1);
925 static struct snd_soc_dai_ops fsi_dai_ops = {
926 .startup = fsi_dai_startup,
927 .shutdown = fsi_dai_shutdown,
928 .trigger = fsi_dai_trigger,
929 .hw_params = fsi_dai_hw_params,
936 static struct snd_pcm_hardware fsi_pcm_hardware = {
937 .info = SNDRV_PCM_INFO_INTERLEAVED |
938 SNDRV_PCM_INFO_MMAP |
939 SNDRV_PCM_INFO_MMAP_VALID |
940 SNDRV_PCM_INFO_PAUSE,
947 .buffer_bytes_max = 64 * 1024,
948 .period_bytes_min = 32,
949 .period_bytes_max = 8192,
955 static int fsi_pcm_open(struct snd_pcm_substream *substream)
957 struct snd_pcm_runtime *runtime = substream->runtime;
960 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
962 ret = snd_pcm_hw_constraint_integer(runtime,
963 SNDRV_PCM_HW_PARAM_PERIODS);
968 static int fsi_hw_params(struct snd_pcm_substream *substream,
969 struct snd_pcm_hw_params *hw_params)
971 return snd_pcm_lib_malloc_pages(substream,
972 params_buffer_bytes(hw_params));
975 static int fsi_hw_free(struct snd_pcm_substream *substream)
977 return snd_pcm_lib_free_pages(substream);
980 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
982 struct snd_pcm_runtime *runtime = substream->runtime;
983 struct fsi_priv *fsi = fsi_get_priv(substream);
986 location = (fsi->buff_offset - 1);
990 return bytes_to_frames(runtime, location);
993 static struct snd_pcm_ops fsi_pcm_ops = {
994 .open = fsi_pcm_open,
995 .ioctl = snd_pcm_lib_ioctl,
996 .hw_params = fsi_hw_params,
997 .hw_free = fsi_hw_free,
998 .pointer = fsi_pointer,
1005 #define PREALLOC_BUFFER (32 * 1024)
1006 #define PREALLOC_BUFFER_MAX (32 * 1024)
1008 static void fsi_pcm_free(struct snd_pcm *pcm)
1010 snd_pcm_lib_preallocate_free_for_all(pcm);
1013 static int fsi_pcm_new(struct snd_card *card,
1014 struct snd_soc_dai *dai,
1015 struct snd_pcm *pcm)
1018 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1019 * in MMAP mode (i.e. aplay -M)
1021 return snd_pcm_lib_preallocate_pages_for_all(
1023 SNDRV_DMA_TYPE_CONTINUOUS,
1024 snd_dma_continuous_data(GFP_KERNEL),
1025 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1032 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1037 .formats = FSI_FMTS,
1043 .formats = FSI_FMTS,
1047 .ops = &fsi_dai_ops,
1053 .formats = FSI_FMTS,
1059 .formats = FSI_FMTS,
1063 .ops = &fsi_dai_ops,
1067 static struct snd_soc_platform_driver fsi_soc_platform = {
1068 .ops = &fsi_pcm_ops,
1069 .pcm_new = fsi_pcm_new,
1070 .pcm_free = fsi_pcm_free,
1077 static int fsi_probe(struct platform_device *pdev)
1079 struct fsi_master *master;
1080 const struct platform_device_id *id_entry;
1081 struct resource *res;
1085 id_entry = pdev->id_entry;
1087 dev_err(&pdev->dev, "unknown fsi device\n");
1091 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1092 irq = platform_get_irq(pdev, 0);
1093 if (!res || (int)irq <= 0) {
1094 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1099 master = kzalloc(sizeof(*master), GFP_KERNEL);
1101 dev_err(&pdev->dev, "Could not allocate master\n");
1106 master->base = ioremap_nocache(res->start, resource_size(res));
1107 if (!master->base) {
1109 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1113 /* master setting */
1115 master->info = pdev->dev.platform_data;
1116 master->core = (struct fsi_core *)id_entry->driver_data;
1117 spin_lock_init(&master->lock);
1120 master->fsia.base = master->base;
1121 master->fsia.master = master;
1122 master->fsia.mst_ctrl = A_MST_CTLR;
1125 master->fsib.base = master->base + 0x40;
1126 master->fsib.master = master;
1127 master->fsib.mst_ctrl = B_MST_CTLR;
1129 pm_runtime_enable(&pdev->dev);
1130 pm_runtime_resume(&pdev->dev);
1131 dev_set_drvdata(&pdev->dev, master);
1133 fsi_soft_all_reset(master);
1135 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1136 id_entry->name, master);
1138 dev_err(&pdev->dev, "irq request err\n");
1142 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1144 dev_err(&pdev->dev, "cannot snd soc register\n");
1148 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1151 free_irq(irq, master);
1153 iounmap(master->base);
1154 pm_runtime_disable(&pdev->dev);
1162 static int fsi_remove(struct platform_device *pdev)
1164 struct fsi_master *master;
1166 master = dev_get_drvdata(&pdev->dev);
1168 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1169 snd_soc_unregister_platform(&pdev->dev);
1171 pm_runtime_disable(&pdev->dev);
1173 free_irq(master->irq, master);
1175 iounmap(master->base);
1181 static int fsi_runtime_nop(struct device *dev)
1183 /* Runtime PM callback shared between ->runtime_suspend()
1184 * and ->runtime_resume(). Simply returns success.
1186 * This driver re-initializes all registers after
1187 * pm_runtime_get_sync() anyway so there is no need
1188 * to save and restore registers here.
1193 static struct dev_pm_ops fsi_pm_ops = {
1194 .runtime_suspend = fsi_runtime_nop,
1195 .runtime_resume = fsi_runtime_nop,
1198 static struct fsi_core fsi1_core = {
1207 static struct fsi_core fsi2_core = {
1211 .int_st = CPU_INT_ST,
1216 static struct platform_device_id fsi_id_table[] = {
1217 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1218 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1221 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1223 static struct platform_driver fsi_driver = {
1225 .name = "fsi-pcm-audio",
1229 .remove = fsi_remove,
1230 .id_table = fsi_id_table,
1233 static int __init fsi_mobile_init(void)
1235 return platform_driver_register(&fsi_driver);
1238 static void __exit fsi_mobile_exit(void)
1240 platform_driver_unregister(&fsi_driver);
1243 module_init(fsi_mobile_init);
1244 module_exit(fsi_mobile_exit);
1246 MODULE_LICENSE("GPL");
1247 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1248 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");