sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <sound/core.h>
  32 #include <sound/pcm.h>
  33 #include <sound/pcm_params.h>
  34 #include <sound/initval.h>
  35 #include <sound/soc.h>
  36
  37 #include <plat/dma.h>
  38 #include <plat/mcbsp.h>
  39 #include "mcbsp.h"
  40 #include "omap-mcbsp.h"
  41 #include "omap-pcm.h"
  42
  43 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  44
  45 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  46         xhandler_get, xhandler_put) \
  47 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  48         .info = omap_mcbsp_st_info_volsw, \
  49         .get = xhandler_get, .put = xhandler_put, \
  50         .private_value = (unsigned long) &(struct soc_mixer_control) \
  51         {.min = xmin, .max = xmax} }
  52
  53 enum {
  54         OMAP_MCBSP_WORD_8 = 0,
  55         OMAP_MCBSP_WORD_12,
  56         OMAP_MCBSP_WORD_16,
  57         OMAP_MCBSP_WORD_20,
  58         OMAP_MCBSP_WORD_24,
  59         OMAP_MCBSP_WORD_32,
  60 };
  61
  62 /*
  63  * Stream DMA parameters. DMA request line and port address are set runtime
  64  * since they are different between OMAP1 and later OMAPs
  65  */
  66 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
  67 {
  68         struct snd_soc_pcm_runtime *rtd = substream->private_data;
  69         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  70         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  71         struct omap_pcm_dma_data *dma_data;
  72         int words;
  73
  74         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  75
  76         /*
  77          * Configure McBSP threshold based on either:
  78          * packet_size, when the sDMA is in packet mode, or based on the
  79          * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
  80          * for mono streams.
  81          */
  82         if (dma_data->packet_size)
  83                 words = dma_data->packet_size;
  84         else if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
  85                 words = snd_pcm_lib_period_bytes(substream) /
  86                                                 (mcbsp->wlen / 8);
  87         else
  88                 words = 1;
  89
  90         /* Configure McBSP internal buffer usage */
  91         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  92                 omap_mcbsp_set_tx_threshold(mcbsp, words);
  93         else
  94                 omap_mcbsp_set_rx_threshold(mcbsp, words);
  95 }
  96
  97 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  98                                     struct snd_pcm_hw_rule *rule)
  99 {
 100         struct snd_interval *buffer_size = hw_param_interval(params,
 101                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 102         struct snd_interval *channels = hw_param_interval(params,
 103                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 104         struct omap_mcbsp *mcbsp = rule->private;
 105         struct snd_interval frames;
 106         int size;
 107
 108         snd_interval_any(&frames);
 109         size = mcbsp->pdata->buffer_size;
 110
 111         frames.min = size / channels->min;
 112         frames.integer = 1;
 113         return snd_interval_refine(buffer_size, &frames);
 114 }
 115
 116 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 117                                   struct snd_soc_dai *cpu_dai)
 118 {
 119         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 120         int err = 0;
 121
 122         if (!cpu_dai->active)
 123                 err = omap_mcbsp_request(mcbsp);
 124
 125         /*
 126          * OMAP3 McBSP FIFO is word structured.
 127          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 128          * McBSP1,3,4,5 has 128 word long buffer
 129          * This means that the size of the FIFO depends on the sample format.
 130          * For example on McBSP3:
 131          * 16bit samples: size is 128 * 2 = 256 bytes
 132          * 32bit samples: size is 128 * 4 = 512 bytes
 133          * It is simpler to place constraint for buffer and period based on
 134          * channels.
 135          * McBSP3 as example again (16 or 32 bit samples):
 136          * 1 channel (mono): size is 128 frames (128 words)
 137          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 138          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 139          */
 140         if (mcbsp->pdata->buffer_size) {
 141                 /*
 142                 * Rule for the buffer size. We should not allow
 143                 * smaller buffer than the FIFO size to avoid underruns.
 144                 * This applies only for the playback stream.
 145                 */
 146                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 147                         snd_pcm_hw_rule_add(substream->runtime, 0,
 148                                             SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 149                                             omap_mcbsp_hwrule_min_buffersize,
 150                                             mcbsp,
 151                                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 152
 153                 /* Make sure, that the period size is always even */
 154                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 155                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 156         }
 157
 158         return err;
 159 }
 160
 161 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 162                                     struct snd_soc_dai *cpu_dai)
 163 {
 164         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 165
 166         if (!cpu_dai->active) {
 167                 omap_mcbsp_free(mcbsp);
 168                 mcbsp->configured = 0;
 169         }
 170 }
 171
 172 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 173                                   struct snd_soc_dai *cpu_dai)
 174 {
 175         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 176         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 177
 178         switch (cmd) {
 179         case SNDRV_PCM_TRIGGER_START:
 180         case SNDRV_PCM_TRIGGER_RESUME:
 181         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 182                 mcbsp->active++;
 183                 omap_mcbsp_start(mcbsp, play, !play);
 184                 break;
 185
 186         case SNDRV_PCM_TRIGGER_STOP:
 187         case SNDRV_PCM_TRIGGER_SUSPEND:
 188         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 189                 omap_mcbsp_stop(mcbsp, play, !play);
 190                 mcbsp->active--;
 191                 break;
 192         default:
 193                 err = -EINVAL;
 194         }
 195
 196         return err;
 197 }
 198
 199 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 200                         struct snd_pcm_substream *substream,
 201                         struct snd_soc_dai *dai)
 202 {
 203         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 204         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 205         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 206         u16 fifo_use;
 207         snd_pcm_sframes_t delay;
 208
 209         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 210                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 211         else
 212                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 213
 214         /*
 215          * Divide the used locations with the channel count to get the
 216          * FIFO usage in samples (don't care about partial samples in the
 217          * buffer).
 218          */
 219         delay = fifo_use / substream->runtime->channels;
 220
 221         return delay;
 222 }
 223
 224 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 225                                     struct snd_pcm_hw_params *params,
 226                                     struct snd_soc_dai *cpu_dai)
 227 {
 228         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 229         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 230         struct omap_pcm_dma_data *dma_data;
 231         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 232         int pkt_size = 0;
 233         unsigned int format, div, framesize, master;
 234
 235         dma_data = &mcbsp->dma_data[substream->stream];
 236         channels = params_channels(params);
 237
 238         switch (params_format(params)) {
 239         case SNDRV_PCM_FORMAT_S16_LE:
 240                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
 241                 wlen = 16;
 242                 break;
 243         case SNDRV_PCM_FORMAT_S32_LE:
 244                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
 245                 wlen = 32;
 246                 break;
 247         default:
 248                 return -EINVAL;
 249         }
 250         if (mcbsp->pdata->buffer_size) {
 251                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 252                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 253                         int period_words, max_thrsh;
 254
 255                         period_words = params_period_bytes(params) / (wlen / 8);
 256                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 257                                 max_thrsh = mcbsp->max_tx_thres;
 258                         else
 259                                 max_thrsh = mcbsp->max_rx_thres;
 260                         /*
 261                          * If the period contains less or equal number of words,
 262                          * we are using the original threshold mode setup:
 263                          * McBSP threshold = sDMA frame size = period_size
 264                          * Otherwise we switch to sDMA packet mode:
 265                          * McBSP threshold = sDMA packet size
 266                          * sDMA frame size = period size
 267                          */
 268                         if (period_words > max_thrsh) {
 269                                 int divider = 0;
 270
 271                                 /*
 272                                  * Look for the biggest threshold value, which
 273                                  * divides the period size evenly.
 274                                  */
 275                                 divider = period_words / max_thrsh;
 276                                 if (period_words % max_thrsh)
 277                                         divider++;
 278                                 while (period_words % divider &&
 279                                         divider < period_words)
 280                                         divider++;
 281                                 if (divider == period_words)
 282                                         return -EINVAL;
 283
 284                                 pkt_size = period_words / divider;
 285                                 sync_mode = OMAP_DMA_SYNC_PACKET;
 286                         } else {
 287                                 sync_mode = OMAP_DMA_SYNC_FRAME;
 288                         }
 289                 } else if (channels > 1) {
 290                         /* Use packet mode for non mono streams */
 291                         pkt_size = channels;
 292                         sync_mode = OMAP_DMA_SYNC_PACKET;
 293                 }
 294         }
 295
 296         dma_data->sync_mode = sync_mode;
 297         dma_data->packet_size = pkt_size;
 298
 299         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 300
 301         if (mcbsp->configured) {
 302                 /* McBSP already configured by another stream */
 303                 return 0;
 304         }
 305
 306         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
 307         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
 308         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
 309         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
 310         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 311         wpf = channels;
 312         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 313                               format == SND_SOC_DAIFMT_LEFT_J)) {
 314                 /* Use dual-phase frames */
 315                 regs->rcr2      |= RPHASE;
 316                 regs->xcr2      |= XPHASE;
 317                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 318                 wpf--;
 319                 regs->rcr2      |= RFRLEN2(wpf - 1);
 320                 regs->xcr2      |= XFRLEN2(wpf - 1);
 321         }
 322
 323         regs->rcr1      |= RFRLEN1(wpf - 1);
 324         regs->xcr1      |= XFRLEN1(wpf - 1);
 325
 326         switch (params_format(params)) {
 327         case SNDRV_PCM_FORMAT_S16_LE:
 328                 /* Set word lengths */
 329                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 330                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 331                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 332                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 333                 break;
 334         case SNDRV_PCM_FORMAT_S32_LE:
 335                 /* Set word lengths */
 336                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 337                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 338                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 339                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 340                 break;
 341         default:
 342                 /* Unsupported PCM format */
 343                 return -EINVAL;
 344         }
 345
 346         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 347          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 348         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 349         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 350                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
 351                 framesize = (mcbsp->in_freq / div) / params_rate(params);
 352
 353                 if (framesize < wlen * channels) {
 354                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 355                                         "channels\n", __func__);
 356                         return -EINVAL;
 357                 }
 358         } else
 359                 framesize = wlen * channels;
 360
 361         /* Set FS period and length in terms of bit clock periods */
 362         regs->srgr2     &= ~FPER(0xfff);
 363         regs->srgr1     &= ~FWID(0xff);
 364         switch (format) {
 365         case SND_SOC_DAIFMT_I2S:
 366         case SND_SOC_DAIFMT_LEFT_J:
 367                 regs->srgr2     |= FPER(framesize - 1);
 368                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 369                 break;
 370         case SND_SOC_DAIFMT_DSP_A:
 371         case SND_SOC_DAIFMT_DSP_B:
 372                 regs->srgr2     |= FPER(framesize - 1);
 373                 regs->srgr1     |= FWID(0);
 374                 break;
 375         }
 376
 377         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
 378         mcbsp->wlen = wlen;
 379         mcbsp->configured = 1;
 380
 381         return 0;
 382 }
 383
 384 /*
 385  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 386  * cache is initialized here
 387  */
 388 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 389                                       unsigned int fmt)
 390 {
 391         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 392         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 393         bool inv_fs = false;
 394
 395         if (mcbsp->configured)
 396                 return 0;
 397
 398         mcbsp->fmt = fmt;
 399         memset(regs, 0, sizeof(*regs));
 400         /* Generic McBSP register settings */
 401         regs->spcr2     |= XINTM(3) | FREE;
 402         regs->spcr1     |= RINTM(3);
 403         /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
 404         if (!mcbsp->pdata->has_ccr) {
 405                 regs->rcr2      |= RFIG;
 406                 regs->xcr2      |= XFIG;
 407         }
 408
 409         /* Configure XCCR/RCCR only for revisions which have ccr registers */
 410         if (mcbsp->pdata->has_ccr) {
 411                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 412                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 413         }
 414
 415         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 416         case SND_SOC_DAIFMT_I2S:
 417                 /* 1-bit data delay */
 418                 regs->rcr2      |= RDATDLY(1);
 419                 regs->xcr2      |= XDATDLY(1);
 420                 break;
 421         case SND_SOC_DAIFMT_LEFT_J:
 422                 /* 0-bit data delay */
 423                 regs->rcr2      |= RDATDLY(0);
 424                 regs->xcr2      |= XDATDLY(0);
 425                 regs->spcr1     |= RJUST(2);
 426                 /* Invert FS polarity configuration */
 427                 inv_fs = true;
 428                 break;
 429         case SND_SOC_DAIFMT_DSP_A:
 430                 /* 1-bit data delay */
 431                 regs->rcr2      |= RDATDLY(1);
 432                 regs->xcr2      |= XDATDLY(1);
 433                 /* Invert FS polarity configuration */
 434                 inv_fs = true;
 435                 break;
 436         case SND_SOC_DAIFMT_DSP_B:
 437                 /* 0-bit data delay */
 438                 regs->rcr2      |= RDATDLY(0);
 439                 regs->xcr2      |= XDATDLY(0);
 440                 /* Invert FS polarity configuration */
 441                 inv_fs = true;
 442                 break;
 443         default:
 444                 /* Unsupported data format */
 445                 return -EINVAL;
 446         }
 447
 448         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 449         case SND_SOC_DAIFMT_CBS_CFS:
 450                 /* McBSP master. Set FS and bit clocks as outputs */
 451                 regs->pcr0      |= FSXM | FSRM |
 452                                    CLKXM | CLKRM;
 453                 /* Sample rate generator drives the FS */
 454                 regs->srgr2     |= FSGM;
 455                 break;
 456         case SND_SOC_DAIFMT_CBM_CFM:
 457                 /* McBSP slave */
 458                 break;
 459         default:
 460                 /* Unsupported master/slave configuration */
 461                 return -EINVAL;
 462         }
 463
 464         /* Set bit clock (CLKX/CLKR) and FS polarities */
 465         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 466         case SND_SOC_DAIFMT_NB_NF:
 467                 /*
 468                  * Normal BCLK + FS.
 469                  * FS active low. TX data driven on falling edge of bit clock
 470                  * and RX data sampled on rising edge of bit clock.
 471                  */
 472                 regs->pcr0      |= FSXP | FSRP |
 473                                    CLKXP | CLKRP;
 474                 break;
 475         case SND_SOC_DAIFMT_NB_IF:
 476                 regs->pcr0      |= CLKXP | CLKRP;
 477                 break;
 478         case SND_SOC_DAIFMT_IB_NF:
 479                 regs->pcr0      |= FSXP | FSRP;
 480                 break;
 481         case SND_SOC_DAIFMT_IB_IF:
 482                 break;
 483         default:
 484                 return -EINVAL;
 485         }
 486         if (inv_fs == true)
 487                 regs->pcr0 ^= FSXP | FSRP;
 488
 489         return 0;
 490 }
 491
 492 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 493                                      int div_id, int div)
 494 {
 495         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 496         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 497
 498         if (div_id != OMAP_MCBSP_CLKGDV)
 499                 return -ENODEV;
 500
 501         mcbsp->clk_div = div;
 502         regs->srgr1     &= ~CLKGDV(0xff);
 503         regs->srgr1     |= CLKGDV(div - 1);
 504
 505         return 0;
 506 }
 507
 508 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 509                                          int clk_id, unsigned int freq,
 510                                          int dir)
 511 {
 512         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 513         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 514         int err = 0;
 515
 516         if (mcbsp->active) {
 517                 if (freq == mcbsp->in_freq)
 518                         return 0;
 519                 else
 520                         return -EBUSY;
 521         }
 522
 523         mcbsp->in_freq = freq;
 524         regs->srgr2 &= ~CLKSM;
 525         regs->pcr0 &= ~SCLKME;
 526
 527         switch (clk_id) {
 528         case OMAP_MCBSP_SYSCLK_CLK:
 529                 regs->srgr2     |= CLKSM;
 530                 break;
 531         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 532                 if (cpu_class_is_omap1()) {
 533                         err = -EINVAL;
 534                         break;
 535                 }
 536                 err = omap2_mcbsp_set_clks_src(mcbsp,
 537                                                MCBSP_CLKS_PRCM_SRC);
 538                 break;
 539         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 540                 if (cpu_class_is_omap1()) {
 541                         err = 0;
 542                         break;
 543                 }
 544                 err = omap2_mcbsp_set_clks_src(mcbsp,
 545                                                MCBSP_CLKS_PAD_SRC);
 546                 break;
 547
 548         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 549                 regs->srgr2     |= CLKSM;
 550         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 551                 regs->pcr0      |= SCLKME;
 552                 break;
 553         default:
 554                 err = -ENODEV;
 555         }
 556
 557         return err;
 558 }
 559
 560 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
 561         .startup        = omap_mcbsp_dai_startup,
 562         .shutdown       = omap_mcbsp_dai_shutdown,
 563         .trigger        = omap_mcbsp_dai_trigger,
 564         .delay          = omap_mcbsp_dai_delay,
 565         .hw_params      = omap_mcbsp_dai_hw_params,
 566         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 567         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 568         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 569 };
 570
 571 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
 572 {
 573         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 574
 575         pm_runtime_enable(mcbsp->dev);
 576
 577         return 0;
 578 }
 579
 580 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
 581 {
 582         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 583
 584         pm_runtime_disable(mcbsp->dev);
 585
 586         return 0;
 587 }
 588
 589 static struct snd_soc_dai_driver omap_mcbsp_dai = {
 590         .probe = omap_mcbsp_probe,
 591         .remove = omap_mcbsp_remove,
 592         .playback = {
 593                 .channels_min = 1,
 594                 .channels_max = 16,
 595                 .rates = OMAP_MCBSP_RATES,
 596                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 597         },
 598         .capture = {
 599                 .channels_min = 1,
 600                 .channels_max = 16,
 601                 .rates = OMAP_MCBSP_RATES,
 602                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 603         },
 604         .ops = &mcbsp_dai_ops,
 605 };
 606
 607 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 608                         struct snd_ctl_elem_info *uinfo)
 609 {
 610         struct soc_mixer_control *mc =
 611                 (struct soc_mixer_control *)kcontrol->private_value;
 612         int max = mc->max;
 613         int min = mc->min;
 614
 615         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 616         uinfo->count = 1;
 617         uinfo->value.integer.min = min;
 618         uinfo->value.integer.max = max;
 619         return 0;
 620 }
 621
 622 #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel)                           \
 623 static int                                                              \
 624 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
 625                                         struct snd_ctl_elem_value *uc)  \
 626 {                                                                       \
 627         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 628         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 629         struct soc_mixer_control *mc =                                  \
 630                 (struct soc_mixer_control *)kc->private_value;          \
 631         int max = mc->max;                                              \
 632         int min = mc->min;                                              \
 633         int val = uc->value.integer.value[0];                           \
 634                                                                         \
 635         if (val < min || val > max)                                     \
 636                 return -EINVAL;                                         \
 637                                                                         \
 638         /* OMAP McBSP implementation uses index values 0..4 */          \
 639         return omap_st_set_chgain(mcbsp, channel, val);                 \
 640 }                                                                       \
 641                                                                         \
 642 static int                                                              \
 643 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
 644                                         struct snd_ctl_elem_value *uc)  \
 645 {                                                                       \
 646         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 647         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 648         s16 chgain;                                                     \
 649                                                                         \
 650         if (omap_st_get_chgain(mcbsp, channel, &chgain))                \
 651                 return -EAGAIN;                                         \
 652                                                                         \
 653         uc->value.integer.value[0] = chgain;                            \
 654         return 0;                                                       \
 655 }
 656
 657 OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
 658 OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
 659
 660 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 661                                 struct snd_ctl_elem_value *ucontrol)
 662 {
 663         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 664         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 665         u8 value = ucontrol->value.integer.value[0];
 666
 667         if (value == omap_st_is_enabled(mcbsp))
 668                 return 0;
 669
 670         if (value)
 671                 omap_st_enable(mcbsp);
 672         else
 673                 omap_st_disable(mcbsp);
 674
 675         return 1;
 676 }
 677
 678 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 679                                 struct snd_ctl_elem_value *ucontrol)
 680 {
 681         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 682         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 683
 684         ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
 685         return 0;
 686 }
 687
 688 #define OMAP_MCBSP_ST_CONTROLS(port)                                      \
 689 static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
 690 SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0,              \
 691                omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),           \
 692 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
 693                               -32768, 32767,                              \
 694                               omap_mcbsp_get_st_ch0_volume,               \
 695                               omap_mcbsp_set_st_ch0_volume),              \
 696 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
 697                               -32768, 32767,                              \
 698                               omap_mcbsp_get_st_ch1_volume,               \
 699                               omap_mcbsp_set_st_ch1_volume),              \
 700 }
 701
 702 OMAP_MCBSP_ST_CONTROLS(2);
 703 OMAP_MCBSP_ST_CONTROLS(3);
 704
 705 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 706 {
 707         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 708         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 709
 710         if (!mcbsp->st_data) {
 711                 dev_warn(mcbsp->dev, "No sidetone data for port\n");
 712                 return 0;
 713         }
 714
 715         switch (mcbsp->id) {
 716         case 2: /* McBSP 2 */
 717                 return snd_soc_add_dai_controls(cpu_dai,
 718                                         omap_mcbsp2_st_controls,
 719                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 720         case 3: /* McBSP 3 */
 721                 return snd_soc_add_dai_controls(cpu_dai,
 722                                         omap_mcbsp3_st_controls,
 723                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 724         default:
 725                 break;
 726         }
 727
 728         return -EINVAL;
 729 }
 730 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 731
 732 static struct omap_mcbsp_platform_data omap2420_pdata = {
 733         .reg_step = 4,
 734         .reg_size = 2,
 735 };
 736
 737 static struct omap_mcbsp_platform_data omap2430_pdata = {
 738         .reg_step = 4,
 739         .reg_size = 4,
 740         .has_ccr = true,
 741 };
 742
 743 static struct omap_mcbsp_platform_data omap3_pdata = {
 744         .reg_step = 4,
 745         .reg_size = 4,
 746         .has_ccr = true,
 747         .has_wakeup = true,
 748 };
 749
 750 static struct omap_mcbsp_platform_data omap4_pdata = {
 751         .reg_step = 4,
 752         .reg_size = 4,
 753         .has_ccr = true,
 754         .has_wakeup = true,
 755 };
 756
 757 static const struct of_device_id omap_mcbsp_of_match[] = {
 758         {
 759                 .compatible = "ti,omap2420-mcbsp",
 760                 .data = &omap2420_pdata,
 761         },
 762         {
 763                 .compatible = "ti,omap2430-mcbsp",
 764                 .data = &omap2430_pdata,
 765         },
 766         {
 767                 .compatible = "ti,omap3-mcbsp",
 768                 .data = &omap3_pdata,
 769         },
 770         {
 771                 .compatible = "ti,omap4-mcbsp",
 772                 .data = &omap4_pdata,
 773         },
 774         { },
 775 };
 776 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
 777
 778 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 779 {
 780         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 781         struct omap_mcbsp *mcbsp;
 782         const struct of_device_id *match;
 783         int ret;
 784
 785         match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
 786         if (match) {
 787                 struct device_node *node = pdev->dev.of_node;
 788                 int buffer_size;
 789
 790                 pdata = devm_kzalloc(&pdev->dev,
 791                                      sizeof(struct omap_mcbsp_platform_data),
 792                                      GFP_KERNEL);
 793                 if (!pdata)
 794                         return -ENOMEM;
 795
 796                 memcpy(pdata, match->data, sizeof(*pdata));
 797                 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
 798                         pdata->buffer_size = buffer_size;
 799         } else if (!pdata) {
 800                 dev_err(&pdev->dev, "missing platform data.\n");
 801                 return -EINVAL;
 802         }
 803         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
 804         if (!mcbsp)
 805                 return -ENOMEM;
 806
 807         mcbsp->id = pdev->id;
 808         mcbsp->pdata = pdata;
 809         mcbsp->dev = &pdev->dev;
 810         platform_set_drvdata(pdev, mcbsp);
 811
 812         ret = omap_mcbsp_init(pdev);
 813         if (!ret)
 814                 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
 815
 816         return ret;
 817 }
 818
 819 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
 820 {
 821         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 822
 823         snd_soc_unregister_dai(&pdev->dev);
 824
 825         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 826                 mcbsp->pdata->ops->free(mcbsp->id);
 827
 828         omap_mcbsp_sysfs_remove(mcbsp);
 829
 830         clk_put(mcbsp->fclk);
 831
 832         platform_set_drvdata(pdev, NULL);
 833
 834         return 0;
 835 }
 836
 837 static struct platform_driver asoc_mcbsp_driver = {
 838         .driver = {
 839                         .name = "omap-mcbsp",
 840                         .owner = THIS_MODULE,
 841                         .of_match_table = omap_mcbsp_of_match,
 842         },
 843
 844         .probe = asoc_mcbsp_probe,
 845         .remove = __devexit_p(asoc_mcbsp_remove),
 846 };
 847
 848 module_platform_driver(asoc_mcbsp_driver);
 849
 850 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
 851 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 852 MODULE_LICENSE("GPL");