2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/driver.h>
21 #include <linux/regulator/machine.h>
22 #include <linux/regulator/consumer.h>
23 #include <sound/core.h>
24 #include <sound/tlv.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
33 #define SGTL5000_DAP_REG_OFFSET 0x0100
34 #define SGTL5000_MAX_REG_OFFSET 0x013A
36 /* default value of sgtl5000 registers except DAP */
37 static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET >> 1] = {
38 0xa011, /* 0x0000, CHIP_ID. 11 stand for revison 17 */
39 0x0000, /* 0x0002, CHIP_DIG_POWER. */
40 0x0008, /* 0x0004, CHIP_CKL_CTRL */
41 0x0010, /* 0x0006, CHIP_I2S_CTRL */
42 0x0000, /* 0x0008, reserved */
43 0x0008, /* 0x000A, CHIP_SSS_CTRL */
44 0x0000, /* 0x000C, reserved */
45 0x020c, /* 0x000E, CHIP_ADCDAC_CTRL */
46 0x3c3c, /* 0x0010, CHIP_DAC_VOL */
47 0x0000, /* 0x0012, reserved */
48 0x015f, /* 0x0014, CHIP_PAD_STRENGTH */
49 0x0000, /* 0x0016, reserved */
50 0x0000, /* 0x0018, reserved */
51 0x0000, /* 0x001A, reserved */
52 0x0000, /* 0x001E, reserved */
53 0x0000, /* 0x0020, CHIP_ANA_ADC_CTRL */
54 0x1818, /* 0x0022, CHIP_ANA_HP_CTRL */
55 0x0111, /* 0x0024, CHIP_ANN_CTRL */
56 0x0000, /* 0x0026, CHIP_LINREG_CTRL */
57 0x0000, /* 0x0028, CHIP_REF_CTRL */
58 0x0000, /* 0x002A, CHIP_MIC_CTRL */
59 0x0000, /* 0x002C, CHIP_LINE_OUT_CTRL */
60 0x0404, /* 0x002E, CHIP_LINE_OUT_VOL */
61 0x7060, /* 0x0030, CHIP_ANA_POWER */
62 0x5000, /* 0x0032, CHIP_PLL_CTRL */
63 0x0000, /* 0x0034, CHIP_CLK_TOP_CTRL */
64 0x0000, /* 0x0036, CHIP_ANA_STATUS */
65 0x0000, /* 0x0038, reserved */
66 0x0000, /* 0x003A, CHIP_ANA_TEST2 */
67 0x0000, /* 0x003C, CHIP_SHORT_CTRL */
68 0x0000, /* reserved */
71 /* default value of dap registers */
72 static const u16 sgtl5000_dap_regs[] = {
73 0x0000, /* 0x0100, DAP_CONTROL */
74 0x0000, /* 0x0102, DAP_PEQ */
75 0x0040, /* 0x0104, DAP_BASS_ENHANCE */
76 0x051f, /* 0x0106, DAP_BASS_ENHANCE_CTRL */
77 0x0000, /* 0x0108, DAP_AUDIO_EQ */
78 0x0040, /* 0x010A, DAP_SGTL_SURROUND */
79 0x0000, /* 0x010C, DAP_FILTER_COEF_ACCESS */
80 0x0000, /* 0x010E, DAP_COEF_WR_B0_MSB */
81 0x0000, /* 0x0110, DAP_COEF_WR_B0_LSB */
82 0x0000, /* 0x0112, reserved */
83 0x0000, /* 0x0114, reserved */
84 0x002f, /* 0x0116, DAP_AUDIO_EQ_BASS_BAND0 */
85 0x002f, /* 0x0118, DAP_AUDIO_EQ_BAND0 */
86 0x002f, /* 0x011A, DAP_AUDIO_EQ_BAND2 */
87 0x002f, /* 0x011C, DAP_AUDIO_EQ_BAND3 */
88 0x002f, /* 0x011E, DAP_AUDIO_EQ_TREBLE_BAND4 */
89 0x8000, /* 0x0120, DAP_MAIN_CHAN */
90 0x0000, /* 0x0122, DAP_MIX_CHAN */
91 0x0510, /* 0x0124, DAP_AVC_CTRL */
92 0x1473, /* 0x0126, DAP_AVC_THRESHOLD */
93 0x0028, /* 0x0128, DAP_AVC_ATTACK */
94 0x0050, /* 0x012A, DAP_AVC_DECAY */
95 0x0000, /* 0x012C, DAP_COEF_WR_B1_MSB */
96 0x0000, /* 0x012E, DAP_COEF_WR_B1_LSB */
97 0x0000, /* 0x0130, DAP_COEF_WR_B2_MSB */
98 0x0000, /* 0x0132, DAP_COEF_WR_B2_LSB */
99 0x0000, /* 0x0134, DAP_COEF_WR_A1_MSB */
100 0x0000, /* 0x0136, DAP_COEF_WR_A1_LSB */
101 0x0000, /* 0x0138, DAP_COEF_WR_A2_MSB */
102 0x0000, /* 0x013A, DAP_COEF_WR_A2_LSB */
105 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
106 enum sgtl5000_regulator_supplies {
113 /* vddd is optional supply */
114 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
120 #define LDO_CONSUMER_NAME "VDDD_LDO"
121 #define LDO_VOLTAGE 1200000
123 static struct regulator_consumer_supply ldo_consumer[] = {
124 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
127 static struct regulator_init_data ldo_init_data = {
131 .valid_modes_mask = REGULATOR_MODE_NORMAL,
132 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
134 .num_consumer_supplies = 1,
135 .consumer_supplies = &ldo_consumer[0],
139 * sgtl5000 internal ldo regulator,
140 * enabled when VDDD not provided
142 struct ldo_regulator {
143 struct regulator_desc desc;
144 struct regulator_dev *dev;
150 /* sgtl5000 private structure in codec */
151 struct sgtl5000_priv {
152 int sysclk; /* sysclk rate */
153 int master; /* i2s master or not */
154 int fmt; /* i2s data format */
155 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
156 struct ldo_regulator *ldo;
160 * mic_bias power on/off share the same register bits with
161 * output impedance of mic bias, when power on mic bias, we
162 * need reclaim it to impedance value.
168 static int mic_bias_event(struct snd_soc_dapm_widget *w,
169 struct snd_kcontrol *kcontrol, int event)
172 case SND_SOC_DAPM_POST_PMU:
173 /* change mic bias resistor to 4Kohm */
174 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
175 SGTL5000_BIAS_R_4k, SGTL5000_BIAS_R_4k);
178 case SND_SOC_DAPM_PRE_PMD:
180 * SGTL5000_BIAS_R_8k as mask to clean the two bits
181 * of mic bias and output impedance
183 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
184 SGTL5000_BIAS_R_8k, 0);
191 * using codec assist to small pop, hp_powerup or lineout_powerup
192 * should stay setting until vag_powerup is fully ramped down,
193 * vag fully ramped down require 400ms.
195 static int small_pop_event(struct snd_soc_dapm_widget *w,
196 struct snd_kcontrol *kcontrol, int event)
199 case SND_SOC_DAPM_PRE_PMU:
200 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
201 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
204 case SND_SOC_DAPM_PRE_PMD:
205 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
206 SGTL5000_VAG_POWERUP, 0);
216 /* input sources for ADC */
217 static const char *adc_mux_text[] = {
221 static const struct soc_enum adc_enum =
222 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
224 static const struct snd_kcontrol_new adc_mux =
225 SOC_DAPM_ENUM("Capture Mux", adc_enum);
227 /* input sources for DAC */
228 static const char *dac_mux_text[] = {
232 static const struct soc_enum dac_enum =
233 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
235 static const struct snd_kcontrol_new dac_mux =
236 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
238 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
239 SND_SOC_DAPM_INPUT("LINE_IN"),
240 SND_SOC_DAPM_INPUT("MIC_IN"),
242 SND_SOC_DAPM_OUTPUT("HP_OUT"),
243 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
245 SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
247 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
249 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
251 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
252 SND_SOC_DAPM_PGA_E("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0,
254 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
256 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
257 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
259 /* aif for i2s input */
260 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
261 0, SGTL5000_CHIP_DIG_POWER,
264 /* aif for i2s output */
265 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
266 0, SGTL5000_CHIP_DIG_POWER,
269 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
271 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
274 /* routes for sgtl5000 */
275 static const struct snd_soc_dapm_route audio_map[] = {
276 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
277 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
279 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
280 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
282 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
283 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
284 {"LO", NULL, "DAC"}, /* dac --> line_out */
286 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
287 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
289 {"LINE_OUT", NULL, "LO"},
290 {"HP_OUT", NULL, "HP"},
293 /* custom function to fetch info of PCM playback volume */
294 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
295 struct snd_ctl_elem_info *uinfo)
297 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
299 uinfo->value.integer.min = 0;
300 uinfo->value.integer.max = 0xfc - 0x3c;
305 * custom function to get of PCM playback volume
307 * dac volume register
308 * 15-------------8-7--------------0
309 * | R channel vol | L channel vol |
310 * -------------------------------
312 * PCM volume with 0.5017 dB steps from 0 to -90 dB
314 * register values map to dB
315 * 0x3B and less = Reserved
319 * 0xFC and greater = Muted
321 * register value map to userspace value
323 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
324 * ------------------------------
325 * userspace value 0xc0 0
327 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
328 struct snd_ctl_elem_value *ucontrol)
330 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
335 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
337 /* get left channel volume */
338 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
340 /* get right channel volume */
341 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
343 /* make sure value fall in (0x3c,0xfc) */
344 l = clamp(l, 0x3c, 0xfc);
345 r = clamp(r, 0x3c, 0xfc);
347 /* invert it and map to userspace value */
351 ucontrol->value.integer.value[0] = l;
352 ucontrol->value.integer.value[1] = r;
358 * custom function to put of PCM playback volume
360 * dac volume register
361 * 15-------------8-7--------------0
362 * | R channel vol | L channel vol |
363 * -------------------------------
365 * PCM volume with 0.5017 dB steps from 0 to -90 dB
367 * register values map to dB
368 * 0x3B and less = Reserved
372 * 0xFC and greater = Muted
374 * userspace value map to register value
376 * userspace value 0xc0 0
377 * ------------------------------
378 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
380 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
383 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
388 l = ucontrol->value.integer.value[0];
389 r = ucontrol->value.integer.value[1];
391 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
392 l = clamp(l, 0, 0xfc - 0x3c);
393 r = clamp(r, 0, 0xfc - 0x3c);
395 /* invert it, get the value can be set to register */
399 /* shift to get the register value */
400 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
401 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
403 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
408 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
410 /* tlv for mic gain, 0db 20db 30db 40db */
411 static const unsigned int mic_gain_tlv[] = {
412 TLV_DB_RANGE_HEAD(4),
413 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
414 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
417 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
418 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
420 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
421 /* SOC_DOUBLE_S8_TLV with invert */
423 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
424 .name = "PCM Playback Volume",
425 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
426 SNDRV_CTL_ELEM_ACCESS_READWRITE,
427 .info = dac_info_volsw,
428 .get = dac_get_volsw,
429 .put = dac_put_volsw,
432 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
433 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
434 SGTL5000_CHIP_ANA_ADC_CTRL,
435 8, 2, 0, capture_6db_attenuate),
436 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
438 SOC_DOUBLE_TLV("Headphone Playback Volume",
439 SGTL5000_CHIP_ANA_HP_CTRL,
443 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
446 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
447 0, 4, 0, mic_gain_tlv),
450 /* mute the codec used by alsa core */
451 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
453 struct snd_soc_codec *codec = codec_dai->codec;
454 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
456 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
457 adcdac_ctrl, mute ? adcdac_ctrl : 0);
462 /* set codec format */
463 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
465 struct snd_soc_codec *codec = codec_dai->codec;
466 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
469 sgtl5000->master = 0;
471 * i2s clock and frame master setting.
473 * - clock and frame slave,
474 * - clock and frame master
476 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
477 case SND_SOC_DAIFMT_CBS_CFS:
479 case SND_SOC_DAIFMT_CBM_CFM:
480 i2sctl |= SGTL5000_I2S_MASTER;
481 sgtl5000->master = 1;
487 /* setting i2s data format */
488 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
489 case SND_SOC_DAIFMT_DSP_A:
490 i2sctl |= SGTL5000_I2S_MODE_PCM;
492 case SND_SOC_DAIFMT_DSP_B:
493 i2sctl |= SGTL5000_I2S_MODE_PCM;
494 i2sctl |= SGTL5000_I2S_LRALIGN;
496 case SND_SOC_DAIFMT_I2S:
497 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
499 case SND_SOC_DAIFMT_RIGHT_J:
500 i2sctl |= SGTL5000_I2S_MODE_RJ;
501 i2sctl |= SGTL5000_I2S_LRPOL;
503 case SND_SOC_DAIFMT_LEFT_J:
504 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
505 i2sctl |= SGTL5000_I2S_LRALIGN;
511 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
513 /* Clock inversion */
514 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
515 case SND_SOC_DAIFMT_NB_NF:
517 case SND_SOC_DAIFMT_IB_NF:
518 i2sctl |= SGTL5000_I2S_SCLK_INV;
524 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
529 /* set codec sysclk */
530 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
531 int clk_id, unsigned int freq, int dir)
533 struct snd_soc_codec *codec = codec_dai->codec;
534 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
537 case SGTL5000_SYSCLK:
538 sgtl5000->sysclk = freq;
548 * set clock according to i2s frame clock,
549 * sgtl5000 provide 2 clock sources.
550 * 1. sys_mclk. sample freq can only configure to
551 * 1/256, 1/384, 1/512 of sys_mclk.
552 * 2. pll. can derive any audio clocks.
554 * clock setting rules:
555 * 1. in slave mode, only sys_mclk can use.
556 * 2. as constraint by sys_mclk, sample freq should
557 * set to 32k, 44.1k and above.
558 * 3. using sys_mclk prefer to pll to save power.
560 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
562 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
564 int sys_fs; /* sample freq */
567 * sample freq should be divided by frame clock,
568 * if frame clock lower than 44.1khz, sample feq should set to
571 switch (frame_rate) {
585 /* set divided factor of frame clock */
586 switch (sys_fs / frame_rate) {
588 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
591 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
594 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
600 /* set the sys_fs according to frame rate */
603 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
606 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
609 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
612 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
615 dev_err(codec->dev, "frame rate %d not supported\n",
621 * calculate the divider of mclk/sample_freq,
622 * factor of freq =96k can only be 256, since mclk in range (12m,27m)
624 switch (sgtl5000->sysclk / sys_fs) {
626 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
627 SGTL5000_MCLK_FREQ_SHIFT;
630 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
631 SGTL5000_MCLK_FREQ_SHIFT;
634 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
635 SGTL5000_MCLK_FREQ_SHIFT;
638 /* if mclk not satisify the divider, use pll */
639 if (sgtl5000->master) {
640 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
641 SGTL5000_MCLK_FREQ_SHIFT;
644 "PLL not supported in slave mode\n");
649 /* if using pll, please check manual 6.4.2 for detail */
650 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
654 unsigned int in, int_div, frac_div;
656 if (sgtl5000->sysclk > 17000000) {
658 in = sgtl5000->sysclk / 2;
661 in = sgtl5000->sysclk;
672 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
673 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
675 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
677 snd_soc_update_bits(codec,
678 SGTL5000_CHIP_CLK_TOP_CTRL,
679 SGTL5000_INPUT_FREQ_DIV2,
680 SGTL5000_INPUT_FREQ_DIV2);
682 snd_soc_update_bits(codec,
683 SGTL5000_CHIP_CLK_TOP_CTRL,
684 SGTL5000_INPUT_FREQ_DIV2,
688 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
689 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
690 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
693 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
694 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
698 /* if using pll, clk_ctrl must be set after pll power up */
699 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
705 * Set PCM DAI bit size and sample rate.
706 * input: params_rate, params_fmt
708 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
709 struct snd_pcm_hw_params *params,
710 struct snd_soc_dai *dai)
712 struct snd_soc_pcm_runtime *rtd = substream->private_data;
713 struct snd_soc_codec *codec = rtd->codec;
714 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
715 int channels = params_channels(params);
720 /* sysclk should already set */
721 if (!sgtl5000->sysclk) {
722 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
726 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
727 stereo = SGTL5000_DAC_STEREO;
729 stereo = SGTL5000_ADC_STEREO;
731 /* set mono to save power */
732 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
733 channels == 1 ? 0 : stereo);
735 /* set codec clock base on lrclk */
736 ret = sgtl5000_set_clock(codec, params_rate(params));
740 /* set i2s data format */
741 switch (params_format(params)) {
742 case SNDRV_PCM_FORMAT_S16_LE:
743 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
745 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
746 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
747 SGTL5000_I2S_SCLKFREQ_SHIFT;
749 case SNDRV_PCM_FORMAT_S20_3LE:
750 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
751 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
752 SGTL5000_I2S_SCLKFREQ_SHIFT;
754 case SNDRV_PCM_FORMAT_S24_LE:
755 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
756 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
757 SGTL5000_I2S_SCLKFREQ_SHIFT;
759 case SNDRV_PCM_FORMAT_S32_LE:
760 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
762 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
763 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
764 SGTL5000_I2S_SCLKFREQ_SHIFT;
770 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL, i2s_ctl, i2s_ctl);
775 static int ldo_regulator_is_enabled(struct regulator_dev *dev)
777 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
782 static int ldo_regulator_enable(struct regulator_dev *dev)
784 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
785 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
788 if (ldo_regulator_is_enabled(dev))
791 /* set regulator value firstly */
792 reg = (1600 - ldo->voltage / 1000) / 50;
793 reg = clamp(reg, 0x0, 0xf);
795 /* amend the voltage value, unit: uV */
796 ldo->voltage = (1600 - reg * 50) * 1000;
798 /* set voltage to register */
799 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
800 (0x1 << 4) - 1, reg);
802 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
803 SGTL5000_LINEREG_D_POWERUP,
804 SGTL5000_LINEREG_D_POWERUP);
806 /* when internal ldo enabled, simple digital power can be disabled */
807 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
808 SGTL5000_LINREG_SIMPLE_POWERUP,
815 static int ldo_regulator_disable(struct regulator_dev *dev)
817 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
818 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
820 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
821 SGTL5000_LINEREG_D_POWERUP,
824 /* clear voltage info */
825 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
833 static int ldo_regulator_get_voltage(struct regulator_dev *dev)
835 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
840 static struct regulator_ops ldo_regulator_ops = {
841 .is_enabled = ldo_regulator_is_enabled,
842 .enable = ldo_regulator_enable,
843 .disable = ldo_regulator_disable,
844 .get_voltage = ldo_regulator_get_voltage,
847 static int ldo_regulator_register(struct snd_soc_codec *codec,
848 struct regulator_init_data *init_data,
851 struct ldo_regulator *ldo;
853 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
856 dev_err(codec->dev, "failed to allocate ldo_regulator\n");
860 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
861 if (!ldo->desc.name) {
863 dev_err(codec->dev, "failed to allocate decs name memory\n");
867 ldo->desc.type = REGULATOR_VOLTAGE;
868 ldo->desc.owner = THIS_MODULE;
869 ldo->desc.ops = &ldo_regulator_ops;
870 ldo->desc.n_voltages = 1;
872 ldo->codec_data = codec;
873 ldo->voltage = voltage;
875 ldo->dev = regulator_register(&ldo->desc, codec->dev,
877 if (IS_ERR(ldo->dev)) {
878 dev_err(codec->dev, "failed to register regulator\n");
879 kfree(ldo->desc.name);
882 return PTR_ERR(ldo->dev);
888 static int ldo_regulator_remove(struct snd_soc_codec *codec)
890 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
891 struct ldo_regulator *ldo = sgtl5000->ldo;
896 regulator_unregister(ldo->dev);
897 kfree(ldo->desc.name);
905 * common state changes:
907 * off --> standby --> prepare --> on
908 * standby --> prepare --> on
911 * on --> prepare --> standby
913 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
914 enum snd_soc_bias_level level)
917 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
920 case SND_SOC_BIAS_ON:
921 case SND_SOC_BIAS_PREPARE:
923 case SND_SOC_BIAS_STANDBY:
924 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
925 ret = regulator_bulk_enable(
926 ARRAY_SIZE(sgtl5000->supplies),
934 case SND_SOC_BIAS_OFF:
935 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
940 codec->dapm.bias_level = level;
944 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
945 SNDRV_PCM_FMTBIT_S20_3LE |\
946 SNDRV_PCM_FMTBIT_S24_LE |\
947 SNDRV_PCM_FMTBIT_S32_LE)
949 static struct snd_soc_dai_ops sgtl5000_ops = {
950 .hw_params = sgtl5000_pcm_hw_params,
951 .digital_mute = sgtl5000_digital_mute,
952 .set_fmt = sgtl5000_set_dai_fmt,
953 .set_sysclk = sgtl5000_set_dai_sysclk,
956 static struct snd_soc_dai_driver sgtl5000_dai = {
959 .stream_name = "Playback",
963 * only support 8~48K + 96K,
964 * TODO modify hw_param to support more
966 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
967 .formats = SGTL5000_FORMATS,
970 .stream_name = "Capture",
973 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
974 .formats = SGTL5000_FORMATS,
976 .ops = &sgtl5000_ops,
977 .symmetric_rates = 1,
980 static int sgtl5000_volatile_register(struct snd_soc_codec *codec,
984 case SGTL5000_CHIP_ID:
985 case SGTL5000_CHIP_ADCDAC_CTRL:
986 case SGTL5000_CHIP_ANA_STATUS:
993 #ifdef CONFIG_SUSPEND
994 static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state)
996 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1002 * restore all sgtl5000 registers,
1003 * since a big hole between dap and regular registers,
1004 * we will restore them respectively.
1006 static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
1008 u16 *cache = codec->reg_cache;
1010 int regular_regs = SGTL5000_CHIP_SHORT_CTRL >> 1;
1012 /* restore regular registers */
1013 for (i = 0; i < regular_regs; i++) {
1016 /* this regs depends on the others */
1017 if (reg == SGTL5000_CHIP_ANA_POWER ||
1018 reg == SGTL5000_CHIP_CLK_CTRL ||
1019 reg == SGTL5000_CHIP_LINREG_CTRL ||
1020 reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
1021 reg == SGTL5000_CHIP_CLK_CTRL)
1024 snd_soc_write(codec, reg, cache[i]);
1027 /* restore dap registers */
1028 for (i = SGTL5000_DAP_REG_OFFSET >> 1;
1029 i < SGTL5000_MAX_REG_OFFSET >> 1; i++) {
1032 snd_soc_write(codec, reg, cache[i]);
1036 * restore power and other regs according
1037 * to set_power() and set_clock()
1039 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
1040 cache[SGTL5000_CHIP_LINREG_CTRL >> 1]);
1042 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
1043 cache[SGTL5000_CHIP_ANA_POWER >> 1]);
1045 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
1046 cache[SGTL5000_CHIP_CLK_CTRL >> 1]);
1048 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
1049 cache[SGTL5000_CHIP_REF_CTRL >> 1]);
1051 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1052 cache[SGTL5000_CHIP_LINE_OUT_CTRL >> 1]);
1056 static int sgtl5000_resume(struct snd_soc_codec *codec)
1058 /* Bring the codec back up to standby to enable regulators */
1059 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1061 /* Restore registers by cached in memory */
1062 sgtl5000_restore_regs(codec);
1066 #define sgtl5000_suspend NULL
1067 #define sgtl5000_resume NULL
1068 #endif /* CONFIG_SUSPEND */
1071 * sgtl5000 has 3 internal power supplies:
1072 * 1. VAG, normally set to vdda/2
1073 * 2. chargepump, set to different value
1074 * according to voltage of vdda and vddio
1075 * 3. line out VAG, normally set to vddio/2
1077 * and should be set according to:
1078 * 1. vddd provided by external or not
1079 * 2. vdda and vddio voltage value. > 3.1v or not
1080 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1082 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1090 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1092 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1093 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1094 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1097 vddio = vddio / 1000;
1100 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1101 dev_err(codec->dev, "regulator voltage not set correctly\n");
1106 /* according to datasheet, maximum voltage of supplies */
1107 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1109 "exceed max voltage vdda %dmv vddio %dma vddd %dma\n",
1116 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1117 ana_pwr |= SGTL5000_DAC_STEREO |
1118 SGTL5000_ADC_STEREO |
1119 SGTL5000_REFTOP_POWERUP;
1120 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1122 if (vddio < 3100 && vdda < 3100) {
1123 /* enable internal oscillator used for charge pump */
1124 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1125 SGTL5000_INT_OSC_EN,
1126 SGTL5000_INT_OSC_EN);
1127 /* Enable VDDC charge pump */
1128 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1129 } else if (vddio >= 3100 && vdda >= 3100) {
1131 * if vddio and vddd > 3.1v,
1132 * charge pump should be clean before set ana_pwr
1134 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1135 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1137 /* VDDC use VDDIO rail */
1138 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1139 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1140 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1143 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1145 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1147 /* set voltage to register */
1148 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1149 (0x1 << 4) - 1, 0x8);
1152 * if vddd linear reg has been enabled,
1153 * simple digital supply should be clear to get
1154 * proper VDDD voltage.
1156 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1157 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1158 SGTL5000_LINREG_SIMPLE_POWERUP,
1161 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1162 SGTL5000_LINREG_SIMPLE_POWERUP |
1163 SGTL5000_STARTUP_POWERUP,
1167 * set ADC/DAC VAG to vdda / 2,
1168 * should stay in range (0.8v, 1.575v)
1171 if (vag <= SGTL5000_ANA_GND_BASE)
1173 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1174 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1175 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1177 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1179 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1180 vag << SGTL5000_ANA_GND_SHIFT,
1181 vag << SGTL5000_ANA_GND_SHIFT);
1183 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1185 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1187 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1188 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1189 vag = SGTL5000_LINE_OUT_GND_MAX;
1191 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1192 SGTL5000_LINE_OUT_GND_STP;
1194 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1195 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1196 SGTL5000_LINE_OUT_CURRENT_360u <<
1197 SGTL5000_LINE_OUT_CURRENT_SHIFT,
1198 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1199 SGTL5000_LINE_OUT_CURRENT_360u <<
1200 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1205 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1211 int external_vddd = 0;
1212 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1214 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1215 sgtl5000->supplies[i].supply = supply_names[i];
1217 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1218 sgtl5000->supplies);
1222 /* set internal ldo to 1.2v */
1223 int voltage = LDO_VOLTAGE;
1225 ret = ldo_regulator_register(codec, &ldo_init_data, voltage);
1228 "Failed to register vddd internal supplies: %d\n",
1233 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1235 ret = regulator_bulk_get(codec->dev,
1236 ARRAY_SIZE(sgtl5000->supplies),
1237 sgtl5000->supplies);
1240 ldo_regulator_remove(codec);
1242 "Failed to request supplies: %d\n", ret);
1248 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1249 sgtl5000->supplies);
1251 goto err_regulator_free;
1253 /* wait for all power rails bring up */
1256 /* read chip information */
1257 reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
1258 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1259 SGTL5000_PARTID_PART_ID) {
1261 "Device with ID register %x is not a sgtl5000\n", reg);
1263 goto err_regulator_disable;
1266 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1267 dev_info(codec->dev, "sgtl5000 revision %d\n", rev);
1270 * workaround for revision 0x11 and later,
1271 * roll back to use internal LDO
1273 if (external_vddd && rev >= 0x11) {
1274 int voltage = LDO_VOLTAGE;
1275 /* disable all regulator first */
1276 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1277 sgtl5000->supplies);
1278 /* free VDDD regulator */
1279 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1280 sgtl5000->supplies);
1282 ret = ldo_regulator_register(codec, &ldo_init_data, voltage);
1286 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1288 ret = regulator_bulk_get(codec->dev,
1289 ARRAY_SIZE(sgtl5000->supplies),
1290 sgtl5000->supplies);
1292 ldo_regulator_remove(codec);
1294 "Failed to request supplies: %d\n", ret);
1299 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1300 sgtl5000->supplies);
1302 goto err_regulator_free;
1304 /* wait for all power rails bring up */
1310 err_regulator_disable:
1311 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1312 sgtl5000->supplies);
1314 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1315 sgtl5000->supplies);
1317 ldo_regulator_remove(codec);
1322 static int sgtl5000_probe(struct snd_soc_codec *codec)
1325 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1327 /* setup i2c data ops */
1328 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
1330 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1334 ret = sgtl5000_enable_regulators(codec);
1338 /* power up sgtl5000 */
1339 ret = sgtl5000_set_power_regs(codec);
1343 /* enable small pop, introduce 400ms delay in turning off */
1344 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1346 SGTL5000_SMALL_POP);
1348 /* disable short cut detector */
1349 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1352 * set i2s as default input of sound switch
1353 * TODO: add sound switch to control and dapm widge.
1355 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1356 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1357 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1358 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1360 /* enable dac volume ramp by default */
1361 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1362 SGTL5000_DAC_VOL_RAMP_EN |
1363 SGTL5000_DAC_MUTE_RIGHT |
1364 SGTL5000_DAC_MUTE_LEFT);
1366 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1368 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1369 SGTL5000_HP_ZCD_EN |
1370 SGTL5000_ADC_ZCD_EN);
1372 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0);
1377 * Enable DAP in kcontrol and dapm.
1379 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1381 /* leading to standby state */
1382 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1386 snd_soc_add_controls(codec, sgtl5000_snd_controls,
1387 ARRAY_SIZE(sgtl5000_snd_controls));
1389 snd_soc_dapm_new_controls(&codec->dapm, sgtl5000_dapm_widgets,
1390 ARRAY_SIZE(sgtl5000_dapm_widgets));
1392 snd_soc_dapm_add_routes(&codec->dapm, audio_map,
1393 ARRAY_SIZE(audio_map));
1395 snd_soc_dapm_new_widgets(&codec->dapm);
1400 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1401 sgtl5000->supplies);
1402 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1403 sgtl5000->supplies);
1404 ldo_regulator_remove(codec);
1409 static int sgtl5000_remove(struct snd_soc_codec *codec)
1411 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1413 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1415 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1416 sgtl5000->supplies);
1417 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1418 sgtl5000->supplies);
1419 ldo_regulator_remove(codec);
1424 static struct snd_soc_codec_driver sgtl5000_driver = {
1425 .probe = sgtl5000_probe,
1426 .remove = sgtl5000_remove,
1427 .suspend = sgtl5000_suspend,
1428 .resume = sgtl5000_resume,
1429 .set_bias_level = sgtl5000_set_bias_level,
1430 .reg_cache_size = ARRAY_SIZE(sgtl5000_regs),
1431 .reg_word_size = sizeof(u16),
1432 .reg_cache_step = 2,
1433 .reg_cache_default = sgtl5000_regs,
1434 .volatile_register = sgtl5000_volatile_register,
1437 static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
1438 const struct i2c_device_id *id)
1440 struct sgtl5000_priv *sgtl5000;
1443 sgtl5000 = kzalloc(sizeof(struct sgtl5000_priv), GFP_KERNEL);
1448 * copy DAP default values to default value array.
1449 * sgtl5000 register space has a big hole, merge it
1450 * at init phase makes life easy.
1451 * FIXME: should we drop 'const' of sgtl5000_regs?
1453 memcpy((void *)(&sgtl5000_regs[0] + (SGTL5000_DAP_REG_OFFSET >> 1)),
1455 SGTL5000_MAX_REG_OFFSET - SGTL5000_DAP_REG_OFFSET);
1457 i2c_set_clientdata(client, sgtl5000);
1459 ret = snd_soc_register_codec(&client->dev,
1460 &sgtl5000_driver, &sgtl5000_dai, 1);
1462 dev_err(&client->dev, "Failed to register codec: %d\n", ret);
1470 static __devexit int sgtl5000_i2c_remove(struct i2c_client *client)
1472 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1474 snd_soc_unregister_codec(&client->dev);
1480 static const struct i2c_device_id sgtl5000_id[] = {
1485 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1487 static struct i2c_driver sgtl5000_i2c_driver = {
1490 .owner = THIS_MODULE,
1492 .probe = sgtl5000_i2c_probe,
1493 .remove = __devexit_p(sgtl5000_i2c_remove),
1494 .id_table = sgtl5000_id,
1497 static int __init sgtl5000_modinit(void)
1499 return i2c_add_driver(&sgtl5000_i2c_driver);
1501 module_init(sgtl5000_modinit);
1503 static void __exit sgtl5000_exit(void)
1505 i2c_del_driver(&sgtl5000_i2c_driver);
1507 module_exit(sgtl5000_exit);
1509 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1510 MODULE_AUTHOR("Zeng Zhaoming <zhaoming.zeng@freescale.com>");
1511 MODULE_LICENSE("GPL");