ff46ba5f27746b39a838ccd937a863275ac7a607
[pandora-kernel.git] / sound / pci / oxygen / oxygen_pcm.c
1 /*
2  * C-Media CMI8788 driver - PCM code
3  *
4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5  *
6  *
7  *  This driver is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License, version 2.
9  *
10  *  This driver is distributed in the hope that it will be useful,
11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  *  GNU General Public License for more details.
14  *
15  *  You should have received a copy of the GNU General Public License
16  *  along with this driver; if not, write to the Free Software
17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
18  */
19
20 #include <sound/driver.h>
21 #include <linux/pci.h>
22 #include <sound/control.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include "oxygen.h"
27
28 static struct snd_pcm_hardware oxygen_hardware[PCM_COUNT] = {
29         [PCM_A] = {
30                 .info = SNDRV_PCM_INFO_MMAP |
31                         SNDRV_PCM_INFO_MMAP_VALID |
32                         SNDRV_PCM_INFO_INTERLEAVED |
33                         SNDRV_PCM_INFO_PAUSE |
34                         SNDRV_PCM_INFO_SYNC_START,
35                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
36                            SNDRV_PCM_FMTBIT_S32_LE,
37                 .rates = SNDRV_PCM_RATE_44100 |
38                          SNDRV_PCM_RATE_48000 |
39                          SNDRV_PCM_RATE_96000 |
40                          SNDRV_PCM_RATE_192000,
41                 .rate_min = 44100,
42                 .rate_max = 192000,
43                 .channels_min = 2,
44                 .channels_max = 2,
45                 .buffer_bytes_max = 256 * 1024,
46                 .period_bytes_min = 128,
47                 .period_bytes_max = 128 * 1024,
48                 .periods_min = 2,
49                 .periods_max = 2048,
50         },
51         [PCM_B] = {
52                 .info = SNDRV_PCM_INFO_MMAP |
53                         SNDRV_PCM_INFO_MMAP_VALID |
54                         SNDRV_PCM_INFO_INTERLEAVED |
55                         SNDRV_PCM_INFO_PAUSE |
56                         SNDRV_PCM_INFO_SYNC_START,
57                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
58                            SNDRV_PCM_FMTBIT_S32_LE,
59                 .rates = SNDRV_PCM_RATE_32000 |
60                          SNDRV_PCM_RATE_44100 |
61                          SNDRV_PCM_RATE_48000 |
62                          SNDRV_PCM_RATE_64000 |
63                          SNDRV_PCM_RATE_88200 |
64                          SNDRV_PCM_RATE_96000 |
65                          SNDRV_PCM_RATE_176400 |
66                          SNDRV_PCM_RATE_192000,
67                 .rate_min = 32000,
68                 .rate_max = 192000,
69                 .channels_min = 2,
70                 .channels_max = 2,
71                 .buffer_bytes_max = 256 * 1024,
72                 .period_bytes_min = 128,
73                 .period_bytes_max = 128 * 1024,
74                 .periods_min = 2,
75                 .periods_max = 2048,
76         },
77         [PCM_C] = {
78                 .info = SNDRV_PCM_INFO_MMAP |
79                         SNDRV_PCM_INFO_MMAP_VALID |
80                         SNDRV_PCM_INFO_INTERLEAVED |
81                         SNDRV_PCM_INFO_PAUSE |
82                         SNDRV_PCM_INFO_SYNC_START,
83                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
84                            SNDRV_PCM_FMTBIT_S32_LE,
85                 .rates = SNDRV_PCM_RATE_44100 |
86                          SNDRV_PCM_RATE_48000 |
87                          SNDRV_PCM_RATE_88200 |
88                          SNDRV_PCM_RATE_96000,
89                 .rate_min = 44100,
90                 .rate_max = 96000,
91                 .channels_min = 2,
92                 .channels_max = 2,
93                 .buffer_bytes_max = 256 * 1024,
94                 .period_bytes_min = 128,
95                 .period_bytes_max = 128 * 1024,
96                 .periods_min = 2,
97                 .periods_max = 2048,
98         },
99         [PCM_SPDIF] = {
100                 .info = SNDRV_PCM_INFO_MMAP |
101                         SNDRV_PCM_INFO_MMAP_VALID |
102                         SNDRV_PCM_INFO_INTERLEAVED |
103                         SNDRV_PCM_INFO_PAUSE |
104                         SNDRV_PCM_INFO_SYNC_START,
105                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
106                            SNDRV_PCM_FMTBIT_S32_LE,
107                 .rates = SNDRV_PCM_RATE_32000 |
108                          SNDRV_PCM_RATE_44100 |
109                          SNDRV_PCM_RATE_48000 |
110                          SNDRV_PCM_RATE_64000 |
111                          SNDRV_PCM_RATE_88200 |
112                          SNDRV_PCM_RATE_96000 |
113                          SNDRV_PCM_RATE_176400 |
114                          SNDRV_PCM_RATE_192000,
115                 .rate_min = 32000,
116                 .rate_max = 192000,
117                 .channels_min = 2,
118                 .channels_max = 2,
119                 .buffer_bytes_max = 256 * 1024,
120                 .period_bytes_min = 128,
121                 .period_bytes_max = 128 * 1024,
122                 .periods_min = 2,
123                 .periods_max = 2048,
124         },
125         [PCM_MULTICH] = {
126                 .info = SNDRV_PCM_INFO_MMAP |
127                         SNDRV_PCM_INFO_MMAP_VALID |
128                         SNDRV_PCM_INFO_INTERLEAVED |
129                         SNDRV_PCM_INFO_PAUSE |
130                         SNDRV_PCM_INFO_SYNC_START,
131                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
132                            SNDRV_PCM_FMTBIT_S32_LE,
133                 .rates = SNDRV_PCM_RATE_32000 |
134                          SNDRV_PCM_RATE_44100 |
135                          SNDRV_PCM_RATE_48000 |
136                          SNDRV_PCM_RATE_64000 |
137                          SNDRV_PCM_RATE_88200 |
138                          SNDRV_PCM_RATE_96000 |
139                          SNDRV_PCM_RATE_176400 |
140                          SNDRV_PCM_RATE_192000,
141                 .rate_min = 32000,
142                 .rate_max = 192000,
143                 .channels_min = 2,
144                 .channels_max = 8,
145                 .buffer_bytes_max = 2048 * 1024,
146                 .period_bytes_min = 128,
147                 .period_bytes_max = 256 * 1024,
148                 .periods_min = 2,
149                 .periods_max = 16384,
150         },
151         [PCM_AC97] = {
152                 .info = SNDRV_PCM_INFO_MMAP |
153                         SNDRV_PCM_INFO_MMAP_VALID |
154                         SNDRV_PCM_INFO_INTERLEAVED |
155                         SNDRV_PCM_INFO_PAUSE |
156                         SNDRV_PCM_INFO_SYNC_START,
157                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
158                 .rates = SNDRV_PCM_RATE_48000,
159                 .rate_min = 48000,
160                 .rate_max = 48000,
161                 .channels_min = 2,
162                 .channels_max = 2,
163                 .buffer_bytes_max = 256 * 1024,
164                 .period_bytes_min = 128,
165                 .period_bytes_max = 128 * 1024,
166                 .periods_min = 2,
167                 .periods_max = 2048,
168         },
169 };
170
171 static inline unsigned int
172 oxygen_substream_channel(struct snd_pcm_substream *substream)
173 {
174         return (unsigned int)(uintptr_t)substream->runtime->private_data;
175 }
176
177 static int oxygen_open(struct snd_pcm_substream *substream,
178                        unsigned int channel)
179 {
180         struct oxygen *chip = snd_pcm_substream_chip(substream);
181         struct snd_pcm_runtime *runtime = substream->runtime;
182         int err;
183
184         runtime->private_data = (void *)(uintptr_t)channel;
185         runtime->hw = oxygen_hardware[channel];
186         err = snd_pcm_hw_constraint_step(runtime, 0,
187                                          SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
188         if (err < 0)
189                 return err;
190         err = snd_pcm_hw_constraint_step(runtime, 0,
191                                          SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
192         if (err < 0)
193                 return err;
194         if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
195                 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
196                 if (err < 0)
197                         return err;
198         }
199         if (runtime->hw.channels_max > 2) {
200                 err = snd_pcm_hw_constraint_step(runtime, 0,
201                                                  SNDRV_PCM_HW_PARAM_CHANNELS,
202                                                  2);
203                 if (err < 0)
204                         return err;
205         }
206         snd_pcm_set_sync(substream);
207         chip->streams[channel] = substream;
208
209         mutex_lock(&chip->mutex);
210         chip->pcm_active |= 1 << channel;
211         if (channel == PCM_SPDIF) {
212                 chip->spdif_pcm_bits = chip->spdif_bits;
213                 chip->spdif_pcm_ctl->vd[0].access &=
214                         ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
215                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
216                                SNDRV_CTL_EVENT_MASK_INFO,
217                                &chip->spdif_pcm_ctl->id);
218         }
219         mutex_unlock(&chip->mutex);
220
221         return 0;
222 }
223
224 static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
225 {
226         return oxygen_open(substream, PCM_A);
227 }
228
229 static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
230 {
231         return oxygen_open(substream, PCM_B);
232 }
233
234 static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
235 {
236         return oxygen_open(substream, PCM_C);
237 }
238
239 static int oxygen_spdif_open(struct snd_pcm_substream *substream)
240 {
241         return oxygen_open(substream, PCM_SPDIF);
242 }
243
244 static int oxygen_multich_open(struct snd_pcm_substream *substream)
245 {
246         return oxygen_open(substream, PCM_MULTICH);
247 }
248
249 static int oxygen_ac97_open(struct snd_pcm_substream *substream)
250 {
251         return oxygen_open(substream, PCM_AC97);
252 }
253
254 static int oxygen_close(struct snd_pcm_substream *substream)
255 {
256         struct oxygen *chip = snd_pcm_substream_chip(substream);
257         unsigned int channel = oxygen_substream_channel(substream);
258
259         mutex_lock(&chip->mutex);
260         chip->pcm_active &= ~(1 << channel);
261         if (channel == PCM_SPDIF) {
262                 chip->spdif_pcm_ctl->vd[0].access |=
263                         SNDRV_CTL_ELEM_ACCESS_INACTIVE;
264                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
265                                SNDRV_CTL_EVENT_MASK_INFO,
266                                &chip->spdif_pcm_ctl->id);
267         }
268         if (channel == PCM_SPDIF || channel == PCM_MULTICH)
269                 oxygen_update_spdif_source(chip);
270         mutex_unlock(&chip->mutex);
271
272         chip->streams[channel] = NULL;
273         return 0;
274 }
275
276 static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
277 {
278         if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
279                 return OXYGEN_FORMAT_24;
280         else
281                 return OXYGEN_FORMAT_16;
282 }
283
284 static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
285 {
286         switch (params_rate(hw_params)) {
287         case 32000:
288                 return OXYGEN_RATE_32000;
289         case 44100:
290                 return OXYGEN_RATE_44100;
291         default: /* 48000 */
292                 return OXYGEN_RATE_48000;
293         case 64000:
294                 return OXYGEN_RATE_64000;
295         case 88200:
296                 return OXYGEN_RATE_88200;
297         case 96000:
298                 return OXYGEN_RATE_96000;
299         case 176400:
300                 return OXYGEN_RATE_176400;
301         case 192000:
302                 return OXYGEN_RATE_192000;
303         }
304 }
305
306 static unsigned int oxygen_i2s_magic2(struct snd_pcm_hw_params *hw_params)
307 {
308         return params_rate(hw_params) <= 96000 ? 0x10 : 0x00;
309 }
310
311 static unsigned int oxygen_i2s_format(struct snd_pcm_hw_params *hw_params)
312 {
313         if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
314                 return OXYGEN_I2S_FORMAT_24;
315         else
316                 return OXYGEN_I2S_FORMAT_16;
317 }
318
319 static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
320 {
321         switch (params_channels(hw_params)) {
322         default: /* 2 */
323                 return OXYGEN_PLAY_CHANNELS_2;
324         case 4:
325                 return OXYGEN_PLAY_CHANNELS_4;
326         case 6:
327                 return OXYGEN_PLAY_CHANNELS_6;
328         case 8:
329                 return OXYGEN_PLAY_CHANNELS_8;
330         }
331 }
332
333 static const unsigned int channel_base_registers[PCM_COUNT] = {
334         [PCM_A] = OXYGEN_DMA_A_ADDRESS,
335         [PCM_B] = OXYGEN_DMA_B_ADDRESS,
336         [PCM_C] = OXYGEN_DMA_C_ADDRESS,
337         [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
338         [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
339         [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
340 };
341
342 static int oxygen_hw_params(struct snd_pcm_substream *substream,
343                             struct snd_pcm_hw_params *hw_params)
344 {
345         struct oxygen *chip = snd_pcm_substream_chip(substream);
346         unsigned int channel = oxygen_substream_channel(substream);
347         int err;
348
349         err = snd_pcm_lib_malloc_pages(substream,
350                                        params_buffer_bytes(hw_params));
351         if (err < 0)
352                 return err;
353
354         oxygen_write32(chip, channel_base_registers[channel],
355                        (u32)substream->runtime->dma_addr);
356         if (channel == PCM_MULTICH) {
357                 oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
358                                params_buffer_bytes(hw_params) / 4 - 1);
359                 oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
360                                params_period_bytes(hw_params) / 4 - 1);
361         } else {
362                 oxygen_write16(chip, channel_base_registers[channel] + 4,
363                                params_buffer_bytes(hw_params) / 4 - 1);
364                 oxygen_write16(chip, channel_base_registers[channel] + 6,
365                                params_period_bytes(hw_params) / 4 - 1);
366         }
367         return 0;
368 }
369
370 static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
371                                   struct snd_pcm_hw_params *hw_params)
372 {
373         struct oxygen *chip = snd_pcm_substream_chip(substream);
374         int err;
375
376         err = oxygen_hw_params(substream, hw_params);
377         if (err < 0)
378                 return err;
379
380         spin_lock_irq(&chip->reg_lock);
381         oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
382                              oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
383                              OXYGEN_REC_FORMAT_A_MASK);
384         oxygen_write8_masked(chip, OXYGEN_I2S_A_FORMAT,
385                              oxygen_rate(hw_params) |
386                              oxygen_i2s_magic2(hw_params) |
387                              oxygen_i2s_format(hw_params),
388                              OXYGEN_I2S_RATE_MASK |
389                              OXYGEN_I2S_MAGIC2_MASK |
390                              OXYGEN_I2S_FORMAT_MASK);
391         oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x08);
392         spin_unlock_irq(&chip->reg_lock);
393
394         mutex_lock(&chip->mutex);
395         chip->model->set_adc_params(chip, hw_params);
396         mutex_unlock(&chip->mutex);
397         return 0;
398 }
399
400 static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
401                                   struct snd_pcm_hw_params *hw_params)
402 {
403         struct oxygen *chip = snd_pcm_substream_chip(substream);
404         int err;
405
406         err = oxygen_hw_params(substream, hw_params);
407         if (err < 0)
408                 return err;
409
410         spin_lock_irq(&chip->reg_lock);
411         oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
412                              oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
413                              OXYGEN_REC_FORMAT_B_MASK);
414         oxygen_write8_masked(chip, OXYGEN_I2S_B_FORMAT,
415                              oxygen_rate(hw_params) |
416                              oxygen_i2s_magic2(hw_params) |
417                              oxygen_i2s_format(hw_params),
418                              OXYGEN_I2S_RATE_MASK |
419                              OXYGEN_I2S_MAGIC2_MASK |
420                              OXYGEN_I2S_FORMAT_MASK);
421         oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x10);
422         spin_unlock_irq(&chip->reg_lock);
423
424         mutex_lock(&chip->mutex);
425         chip->model->set_adc_params(chip, hw_params);
426         mutex_unlock(&chip->mutex);
427         return 0;
428 }
429
430 static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
431                                   struct snd_pcm_hw_params *hw_params)
432 {
433         struct oxygen *chip = snd_pcm_substream_chip(substream);
434         int err;
435
436         err = oxygen_hw_params(substream, hw_params);
437         if (err < 0)
438                 return err;
439
440         spin_lock_irq(&chip->reg_lock);
441         oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
442                              oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
443                              OXYGEN_REC_FORMAT_C_MASK);
444         oxygen_clear_bits8(chip, OXYGEN_REC_ROUTING, 0x20);
445         spin_unlock_irq(&chip->reg_lock);
446         return 0;
447 }
448
449 static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
450                                   struct snd_pcm_hw_params *hw_params)
451 {
452         struct oxygen *chip = snd_pcm_substream_chip(substream);
453         int err;
454
455         err = oxygen_hw_params(substream, hw_params);
456         if (err < 0)
457                 return err;
458
459         spin_lock_irq(&chip->reg_lock);
460         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
461                             OXYGEN_SPDIF_OUT_ENABLE);
462         oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
463                              oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
464                              OXYGEN_SPDIF_FORMAT_MASK);
465         oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
466                               oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
467                               OXYGEN_SPDIF_OUT_RATE_MASK);
468         oxygen_update_spdif_source(chip);
469         spin_unlock_irq(&chip->reg_lock);
470         return 0;
471 }
472
473 static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
474                                     struct snd_pcm_hw_params *hw_params)
475 {
476         struct oxygen *chip = snd_pcm_substream_chip(substream);
477         int err;
478
479         err = oxygen_hw_params(substream, hw_params);
480         if (err < 0)
481                 return err;
482
483         spin_lock_irq(&chip->reg_lock);
484         oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
485                              oxygen_play_channels(hw_params),
486                              OXYGEN_PLAY_CHANNELS_MASK);
487         oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
488                              oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
489                              OXYGEN_MULTICH_FORMAT_MASK);
490         oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
491                               oxygen_rate(hw_params) | oxygen_i2s_format(hw_params),
492                               OXYGEN_I2S_RATE_MASK | OXYGEN_I2S_FORMAT_MASK);
493         oxygen_clear_bits16(chip, OXYGEN_PLAY_ROUTING, 0x001f);
494         oxygen_update_dac_routing(chip);
495         oxygen_update_spdif_source(chip);
496         spin_unlock_irq(&chip->reg_lock);
497
498         mutex_lock(&chip->mutex);
499         chip->model->set_dac_params(chip, hw_params);
500         mutex_unlock(&chip->mutex);
501         return 0;
502 }
503
504 static int oxygen_ac97_hw_params(struct snd_pcm_substream *substream,
505                                  struct snd_pcm_hw_params *hw_params)
506 {
507         struct oxygen *chip = snd_pcm_substream_chip(substream);
508         int err;
509
510         err = oxygen_hw_params(substream, hw_params);
511         if (err < 0)
512                 return err;
513
514         spin_lock_irq(&chip->reg_lock);
515         oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
516                              oxygen_format(hw_params) << OXYGEN_AC97_FORMAT_SHIFT,
517                              OXYGEN_AC97_FORMAT_MASK);
518         spin_unlock_irq(&chip->reg_lock);
519         return 0;
520 }
521
522 static int oxygen_hw_free(struct snd_pcm_substream *substream)
523 {
524         struct oxygen *chip = snd_pcm_substream_chip(substream);
525         unsigned int channel = oxygen_substream_channel(substream);
526
527         spin_lock_irq(&chip->reg_lock);
528         chip->interrupt_mask &= ~(1 << channel);
529         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
530         spin_unlock_irq(&chip->reg_lock);
531
532         return snd_pcm_lib_free_pages(substream);
533 }
534
535 static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
536 {
537         struct oxygen *chip = snd_pcm_substream_chip(substream);
538
539         spin_lock_irq(&chip->reg_lock);
540         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
541                             OXYGEN_SPDIF_OUT_ENABLE);
542         spin_unlock_irq(&chip->reg_lock);
543         return oxygen_hw_free(substream);
544 }
545
546 static int oxygen_prepare(struct snd_pcm_substream *substream)
547 {
548         struct oxygen *chip = snd_pcm_substream_chip(substream);
549         unsigned int channel = oxygen_substream_channel(substream);
550         unsigned int channel_mask = 1 << channel;
551
552         spin_lock_irq(&chip->reg_lock);
553         oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
554         oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
555
556         chip->interrupt_mask |= channel_mask;
557         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
558         spin_unlock_irq(&chip->reg_lock);
559         return 0;
560 }
561
562 static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
563 {
564         struct oxygen *chip = snd_pcm_substream_chip(substream);
565         struct snd_pcm_substream *s;
566         unsigned int mask = 0;
567         int running;
568
569         switch (cmd) {
570         case SNDRV_PCM_TRIGGER_STOP:
571         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
572                 running = 0;
573                 break;
574         case SNDRV_PCM_TRIGGER_START:
575         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
576                 running = 1;
577                 break;
578         default:
579                 return -EINVAL;
580         }
581
582         snd_pcm_group_for_each_entry(s, substream) {
583                 if (snd_pcm_substream_chip(s) == chip) {
584                         mask |= 1 << oxygen_substream_channel(s);
585                         snd_pcm_trigger_done(s, substream);
586                 }
587         }
588
589         spin_lock(&chip->reg_lock);
590         if (running)
591                 chip->pcm_running |= mask;
592         else
593                 chip->pcm_running &= ~mask;
594         oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
595         spin_unlock(&chip->reg_lock);
596         return 0;
597 }
598
599 static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
600 {
601         struct oxygen *chip = snd_pcm_substream_chip(substream);
602         struct snd_pcm_runtime *runtime = substream->runtime;
603         unsigned int channel = oxygen_substream_channel(substream);
604         u32 curr_addr;
605
606         /* no spinlock, this read should be atomic */
607         curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
608         return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
609 }
610
611 static struct snd_pcm_ops oxygen_rec_a_ops = {
612         .open      = oxygen_rec_a_open,
613         .close     = oxygen_close,
614         .ioctl     = snd_pcm_lib_ioctl,
615         .hw_params = oxygen_rec_a_hw_params,
616         .hw_free   = oxygen_hw_free,
617         .prepare   = oxygen_prepare,
618         .trigger   = oxygen_trigger,
619         .pointer   = oxygen_pointer,
620 };
621
622 static struct snd_pcm_ops oxygen_rec_b_ops = {
623         .open      = oxygen_rec_b_open,
624         .close     = oxygen_close,
625         .ioctl     = snd_pcm_lib_ioctl,
626         .hw_params = oxygen_rec_b_hw_params,
627         .hw_free   = oxygen_hw_free,
628         .prepare   = oxygen_prepare,
629         .trigger   = oxygen_trigger,
630         .pointer   = oxygen_pointer,
631 };
632
633 static struct snd_pcm_ops oxygen_rec_c_ops = {
634         .open      = oxygen_rec_c_open,
635         .close     = oxygen_close,
636         .ioctl     = snd_pcm_lib_ioctl,
637         .hw_params = oxygen_rec_c_hw_params,
638         .hw_free   = oxygen_hw_free,
639         .prepare   = oxygen_prepare,
640         .trigger   = oxygen_trigger,
641         .pointer   = oxygen_pointer,
642 };
643
644 static struct snd_pcm_ops oxygen_spdif_ops = {
645         .open      = oxygen_spdif_open,
646         .close     = oxygen_close,
647         .ioctl     = snd_pcm_lib_ioctl,
648         .hw_params = oxygen_spdif_hw_params,
649         .hw_free   = oxygen_spdif_hw_free,
650         .prepare   = oxygen_prepare,
651         .trigger   = oxygen_trigger,
652         .pointer   = oxygen_pointer,
653 };
654
655 static struct snd_pcm_ops oxygen_multich_ops = {
656         .open      = oxygen_multich_open,
657         .close     = oxygen_close,
658         .ioctl     = snd_pcm_lib_ioctl,
659         .hw_params = oxygen_multich_hw_params,
660         .hw_free   = oxygen_hw_free,
661         .prepare   = oxygen_prepare,
662         .trigger   = oxygen_trigger,
663         .pointer   = oxygen_pointer,
664 };
665
666 static struct snd_pcm_ops oxygen_ac97_ops = {
667         .open      = oxygen_ac97_open,
668         .close     = oxygen_close,
669         .ioctl     = snd_pcm_lib_ioctl,
670         .hw_params = oxygen_ac97_hw_params,
671         .hw_free   = oxygen_hw_free,
672         .prepare   = oxygen_prepare,
673         .trigger   = oxygen_trigger,
674         .pointer   = oxygen_pointer,
675 };
676
677 static void oxygen_pcm_free(struct snd_pcm *pcm)
678 {
679         snd_pcm_lib_preallocate_free_for_all(pcm);
680 }
681
682 int __devinit oxygen_pcm_init(struct oxygen *chip)
683 {
684         struct snd_pcm *pcm;
685         int err;
686
687         err = snd_pcm_new(chip->card, "Analog", 0, 1, 1, &pcm);
688         if (err < 0)
689                 return err;
690         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops);
691         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
692                         chip->model->record_from_dma_b ?
693                         &oxygen_rec_b_ops : &oxygen_rec_a_ops);
694         pcm->private_data = chip;
695         pcm->private_free = oxygen_pcm_free;
696         strcpy(pcm->name, "Analog");
697         snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
698                                       SNDRV_DMA_TYPE_DEV,
699                                       snd_dma_pci_data(chip->pci),
700                                       512 * 1024, 2048 * 1024);
701         snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
702                                       SNDRV_DMA_TYPE_DEV,
703                                       snd_dma_pci_data(chip->pci),
704                                       128 * 1024, 256 * 1024);
705
706         err = snd_pcm_new(chip->card, "Digital", 1, 1, 1, &pcm);
707         if (err < 0)
708                 return err;
709         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_spdif_ops);
710         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &oxygen_rec_c_ops);
711         pcm->private_data = chip;
712         pcm->private_free = oxygen_pcm_free;
713         strcpy(pcm->name, "Digital");
714         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
715                                               snd_dma_pci_data(chip->pci),
716                                               128 * 1024, 256 * 1024);
717
718         if (chip->has_2nd_ac97_codec) {
719                 err = snd_pcm_new(chip->card, "AC97", 2, 1, 0, &pcm);
720                 if (err < 0)
721                         return err;
722                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
723                                 &oxygen_ac97_ops);
724                 pcm->private_data = chip;
725                 pcm->private_free = oxygen_pcm_free;
726                 strcpy(pcm->name, "Front Panel");
727                 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
728                                                       snd_dma_pci_data(chip->pci),
729                                                       128 * 1024, 256 * 1024);
730         }
731         return 0;
732 }