2 * C-Media CMI8788 driver - PCM code
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <sound/control.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
27 /* most DMA channels have a 16-bit counter for 32-bit words */
28 #define BUFFER_BYTES_MAX ((1 << 16) * 4)
29 /* the multichannel DMA channel has a 24-bit counter */
30 #define BUFFER_BYTES_MAX_MULTICH ((1 << 24) * 4)
32 #define PERIOD_BYTES_MIN 64
34 #define DEFAULT_BUFFER_BYTES (BUFFER_BYTES_MAX / 2)
35 #define DEFAULT_BUFFER_BYTES_MULTICH (1024 * 1024)
37 static const struct snd_pcm_hardware oxygen_stereo_hardware = {
38 .info = SNDRV_PCM_INFO_MMAP |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_INTERLEAVED |
41 SNDRV_PCM_INFO_PAUSE |
42 SNDRV_PCM_INFO_SYNC_START,
43 .formats = SNDRV_PCM_FMTBIT_S16_LE |
44 SNDRV_PCM_FMTBIT_S32_LE,
45 .rates = SNDRV_PCM_RATE_32000 |
46 SNDRV_PCM_RATE_44100 |
47 SNDRV_PCM_RATE_48000 |
48 SNDRV_PCM_RATE_64000 |
49 SNDRV_PCM_RATE_88200 |
50 SNDRV_PCM_RATE_96000 |
51 SNDRV_PCM_RATE_176400 |
52 SNDRV_PCM_RATE_192000,
57 .buffer_bytes_max = BUFFER_BYTES_MAX,
58 .period_bytes_min = PERIOD_BYTES_MIN,
59 .period_bytes_max = BUFFER_BYTES_MAX / 2,
61 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
63 static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
64 .info = SNDRV_PCM_INFO_MMAP |
65 SNDRV_PCM_INFO_MMAP_VALID |
66 SNDRV_PCM_INFO_INTERLEAVED |
67 SNDRV_PCM_INFO_PAUSE |
68 SNDRV_PCM_INFO_SYNC_START,
69 .formats = SNDRV_PCM_FMTBIT_S16_LE |
70 SNDRV_PCM_FMTBIT_S32_LE,
71 .rates = SNDRV_PCM_RATE_32000 |
72 SNDRV_PCM_RATE_44100 |
73 SNDRV_PCM_RATE_48000 |
74 SNDRV_PCM_RATE_64000 |
75 SNDRV_PCM_RATE_88200 |
76 SNDRV_PCM_RATE_96000 |
77 SNDRV_PCM_RATE_176400 |
78 SNDRV_PCM_RATE_192000,
83 .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
84 .period_bytes_min = PERIOD_BYTES_MIN,
85 .period_bytes_max = BUFFER_BYTES_MAX_MULTICH / 2,
87 .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
89 static const struct snd_pcm_hardware oxygen_ac97_hardware = {
90 .info = SNDRV_PCM_INFO_MMAP |
91 SNDRV_PCM_INFO_MMAP_VALID |
92 SNDRV_PCM_INFO_INTERLEAVED |
93 SNDRV_PCM_INFO_PAUSE |
94 SNDRV_PCM_INFO_SYNC_START,
95 .formats = SNDRV_PCM_FMTBIT_S16_LE,
96 .rates = SNDRV_PCM_RATE_48000,
101 .buffer_bytes_max = BUFFER_BYTES_MAX,
102 .period_bytes_min = PERIOD_BYTES_MIN,
103 .period_bytes_max = BUFFER_BYTES_MAX / 2,
105 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
108 static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
109 [PCM_A] = &oxygen_stereo_hardware,
110 [PCM_B] = &oxygen_stereo_hardware,
111 [PCM_C] = &oxygen_stereo_hardware,
112 [PCM_SPDIF] = &oxygen_stereo_hardware,
113 [PCM_MULTICH] = &oxygen_multichannel_hardware,
114 [PCM_AC97] = &oxygen_ac97_hardware,
117 static inline unsigned int
118 oxygen_substream_channel(struct snd_pcm_substream *substream)
120 return (unsigned int)(uintptr_t)substream->runtime->private_data;
123 static int oxygen_open(struct snd_pcm_substream *substream,
124 unsigned int channel)
126 struct oxygen *chip = snd_pcm_substream_chip(substream);
127 struct snd_pcm_runtime *runtime = substream->runtime;
130 runtime->private_data = (void *)(uintptr_t)channel;
131 if (channel == PCM_B && chip->has_ac97_1 &&
132 (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
133 runtime->hw = oxygen_ac97_hardware;
135 runtime->hw = *oxygen_hardware[channel];
138 runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
139 SNDRV_PCM_RATE_64000);
140 runtime->hw.rate_min = 44100;
143 runtime->hw.channels_max = chip->model.dac_channels;
146 if (chip->model.pcm_hardware_filter)
147 chip->model.pcm_hardware_filter(channel, &runtime->hw);
148 err = snd_pcm_hw_constraint_step(runtime, 0,
149 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
152 err = snd_pcm_hw_constraint_step(runtime, 0,
153 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
156 if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
157 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
161 if (runtime->hw.channels_max > 2) {
162 err = snd_pcm_hw_constraint_step(runtime, 0,
163 SNDRV_PCM_HW_PARAM_CHANNELS,
168 if (channel == PCM_MULTICH) {
169 err = snd_pcm_hw_constraint_minmax
170 (runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 0, 8192000);
174 snd_pcm_set_sync(substream);
175 chip->streams[channel] = substream;
177 mutex_lock(&chip->mutex);
178 chip->pcm_active |= 1 << channel;
179 if (channel == PCM_SPDIF) {
180 chip->spdif_pcm_bits = chip->spdif_bits;
181 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
182 ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
183 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
184 SNDRV_CTL_EVENT_MASK_INFO,
185 &chip->controls[CONTROL_SPDIF_PCM]->id);
187 mutex_unlock(&chip->mutex);
192 static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
194 return oxygen_open(substream, PCM_A);
197 static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
199 return oxygen_open(substream, PCM_B);
202 static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
204 return oxygen_open(substream, PCM_C);
207 static int oxygen_spdif_open(struct snd_pcm_substream *substream)
209 return oxygen_open(substream, PCM_SPDIF);
212 static int oxygen_multich_open(struct snd_pcm_substream *substream)
214 return oxygen_open(substream, PCM_MULTICH);
217 static int oxygen_ac97_open(struct snd_pcm_substream *substream)
219 return oxygen_open(substream, PCM_AC97);
222 static int oxygen_close(struct snd_pcm_substream *substream)
224 struct oxygen *chip = snd_pcm_substream_chip(substream);
225 unsigned int channel = oxygen_substream_channel(substream);
227 mutex_lock(&chip->mutex);
228 chip->pcm_active &= ~(1 << channel);
229 if (channel == PCM_SPDIF) {
230 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
231 SNDRV_CTL_ELEM_ACCESS_INACTIVE;
232 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
233 SNDRV_CTL_EVENT_MASK_INFO,
234 &chip->controls[CONTROL_SPDIF_PCM]->id);
236 if (channel == PCM_SPDIF || channel == PCM_MULTICH)
237 oxygen_update_spdif_source(chip);
238 mutex_unlock(&chip->mutex);
240 chip->streams[channel] = NULL;
244 static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
246 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
247 return OXYGEN_FORMAT_24;
249 return OXYGEN_FORMAT_16;
252 static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
254 switch (params_rate(hw_params)) {
256 return OXYGEN_RATE_32000;
258 return OXYGEN_RATE_44100;
260 return OXYGEN_RATE_48000;
262 return OXYGEN_RATE_64000;
264 return OXYGEN_RATE_88200;
266 return OXYGEN_RATE_96000;
268 return OXYGEN_RATE_176400;
270 return OXYGEN_RATE_192000;
274 static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
276 if (params_rate(hw_params) <= 96000)
277 return OXYGEN_I2S_MCLK_256;
279 return OXYGEN_I2S_MCLK_128;
282 static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
284 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
285 return OXYGEN_I2S_BITS_24;
287 return OXYGEN_I2S_BITS_16;
290 static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
292 switch (params_channels(hw_params)) {
294 return OXYGEN_PLAY_CHANNELS_2;
296 return OXYGEN_PLAY_CHANNELS_4;
298 return OXYGEN_PLAY_CHANNELS_6;
300 return OXYGEN_PLAY_CHANNELS_8;
304 static const unsigned int channel_base_registers[PCM_COUNT] = {
305 [PCM_A] = OXYGEN_DMA_A_ADDRESS,
306 [PCM_B] = OXYGEN_DMA_B_ADDRESS,
307 [PCM_C] = OXYGEN_DMA_C_ADDRESS,
308 [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
309 [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
310 [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
313 static int oxygen_hw_params(struct snd_pcm_substream *substream,
314 struct snd_pcm_hw_params *hw_params)
316 struct oxygen *chip = snd_pcm_substream_chip(substream);
317 unsigned int channel = oxygen_substream_channel(substream);
320 err = snd_pcm_lib_malloc_pages(substream,
321 params_buffer_bytes(hw_params));
325 oxygen_write32(chip, channel_base_registers[channel],
326 (u32)substream->runtime->dma_addr);
327 if (channel == PCM_MULTICH) {
328 oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
329 params_buffer_bytes(hw_params) / 4 - 1);
330 oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
331 params_period_bytes(hw_params) / 4 - 1);
333 oxygen_write16(chip, channel_base_registers[channel] + 4,
334 params_buffer_bytes(hw_params) / 4 - 1);
335 oxygen_write16(chip, channel_base_registers[channel] + 6,
336 params_period_bytes(hw_params) / 4 - 1);
341 static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
342 struct snd_pcm_hw_params *hw_params)
344 struct oxygen *chip = snd_pcm_substream_chip(substream);
347 err = oxygen_hw_params(substream, hw_params);
351 spin_lock_irq(&chip->reg_lock);
352 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
353 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
354 OXYGEN_REC_FORMAT_A_MASK);
355 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
356 oxygen_rate(hw_params) |
357 oxygen_i2s_mclk(hw_params) |
358 chip->model.adc_i2s_format |
359 oxygen_i2s_bits(hw_params),
360 OXYGEN_I2S_RATE_MASK |
361 OXYGEN_I2S_FORMAT_MASK |
362 OXYGEN_I2S_MCLK_MASK |
363 OXYGEN_I2S_BITS_MASK);
364 spin_unlock_irq(&chip->reg_lock);
366 mutex_lock(&chip->mutex);
367 chip->model.set_adc_params(chip, hw_params);
368 mutex_unlock(&chip->mutex);
372 static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
373 struct snd_pcm_hw_params *hw_params)
375 struct oxygen *chip = snd_pcm_substream_chip(substream);
379 err = oxygen_hw_params(substream, hw_params);
383 is_ac97 = chip->has_ac97_1 &&
384 (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
386 spin_lock_irq(&chip->reg_lock);
387 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
388 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
389 OXYGEN_REC_FORMAT_B_MASK);
391 oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
392 oxygen_rate(hw_params) |
393 oxygen_i2s_mclk(hw_params) |
394 chip->model.adc_i2s_format |
395 oxygen_i2s_bits(hw_params),
396 OXYGEN_I2S_RATE_MASK |
397 OXYGEN_I2S_FORMAT_MASK |
398 OXYGEN_I2S_MCLK_MASK |
399 OXYGEN_I2S_BITS_MASK);
400 spin_unlock_irq(&chip->reg_lock);
403 mutex_lock(&chip->mutex);
404 chip->model.set_adc_params(chip, hw_params);
405 mutex_unlock(&chip->mutex);
410 static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
411 struct snd_pcm_hw_params *hw_params)
413 struct oxygen *chip = snd_pcm_substream_chip(substream);
416 err = oxygen_hw_params(substream, hw_params);
420 spin_lock_irq(&chip->reg_lock);
421 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
422 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
423 OXYGEN_REC_FORMAT_C_MASK);
424 spin_unlock_irq(&chip->reg_lock);
428 static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
429 struct snd_pcm_hw_params *hw_params)
431 struct oxygen *chip = snd_pcm_substream_chip(substream);
434 err = oxygen_hw_params(substream, hw_params);
438 mutex_lock(&chip->mutex);
439 spin_lock_irq(&chip->reg_lock);
440 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
441 OXYGEN_SPDIF_OUT_ENABLE);
442 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
443 oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
444 OXYGEN_SPDIF_FORMAT_MASK);
445 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
446 oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
447 OXYGEN_SPDIF_OUT_RATE_MASK);
448 oxygen_update_spdif_source(chip);
449 spin_unlock_irq(&chip->reg_lock);
450 mutex_unlock(&chip->mutex);
454 static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
455 struct snd_pcm_hw_params *hw_params)
457 struct oxygen *chip = snd_pcm_substream_chip(substream);
460 err = oxygen_hw_params(substream, hw_params);
464 mutex_lock(&chip->mutex);
465 spin_lock_irq(&chip->reg_lock);
466 oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
467 oxygen_play_channels(hw_params),
468 OXYGEN_PLAY_CHANNELS_MASK);
469 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
470 oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
471 OXYGEN_MULTICH_FORMAT_MASK);
472 oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
473 oxygen_rate(hw_params) |
474 chip->model.dac_i2s_format |
475 oxygen_i2s_mclk(hw_params) |
476 oxygen_i2s_bits(hw_params),
477 OXYGEN_I2S_RATE_MASK |
478 OXYGEN_I2S_FORMAT_MASK |
479 OXYGEN_I2S_MCLK_MASK |
480 OXYGEN_I2S_BITS_MASK);
481 oxygen_update_spdif_source(chip);
482 spin_unlock_irq(&chip->reg_lock);
484 chip->model.set_dac_params(chip, hw_params);
485 oxygen_update_dac_routing(chip);
486 mutex_unlock(&chip->mutex);
490 static int oxygen_hw_free(struct snd_pcm_substream *substream)
492 struct oxygen *chip = snd_pcm_substream_chip(substream);
493 unsigned int channel = oxygen_substream_channel(substream);
494 unsigned int channel_mask = 1 << channel;
496 spin_lock_irq(&chip->reg_lock);
497 chip->interrupt_mask &= ~channel_mask;
498 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
500 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
501 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
502 spin_unlock_irq(&chip->reg_lock);
504 return snd_pcm_lib_free_pages(substream);
507 static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
509 struct oxygen *chip = snd_pcm_substream_chip(substream);
511 spin_lock_irq(&chip->reg_lock);
512 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
513 OXYGEN_SPDIF_OUT_ENABLE);
514 spin_unlock_irq(&chip->reg_lock);
515 return oxygen_hw_free(substream);
518 static int oxygen_prepare(struct snd_pcm_substream *substream)
520 struct oxygen *chip = snd_pcm_substream_chip(substream);
521 unsigned int channel = oxygen_substream_channel(substream);
522 unsigned int channel_mask = 1 << channel;
524 spin_lock_irq(&chip->reg_lock);
525 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
526 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
528 chip->interrupt_mask |= channel_mask;
529 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
530 spin_unlock_irq(&chip->reg_lock);
534 static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
536 struct oxygen *chip = snd_pcm_substream_chip(substream);
537 struct snd_pcm_substream *s;
538 unsigned int mask = 0;
542 case SNDRV_PCM_TRIGGER_STOP:
543 case SNDRV_PCM_TRIGGER_START:
544 case SNDRV_PCM_TRIGGER_SUSPEND:
547 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
548 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
555 snd_pcm_group_for_each_entry(s, substream) {
556 if (snd_pcm_substream_chip(s) == chip) {
557 mask |= 1 << oxygen_substream_channel(s);
558 snd_pcm_trigger_done(s, substream);
562 spin_lock(&chip->reg_lock);
564 if (cmd == SNDRV_PCM_TRIGGER_START)
565 chip->pcm_running |= mask;
567 chip->pcm_running &= ~mask;
568 oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
570 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
571 oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
573 oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
575 spin_unlock(&chip->reg_lock);
579 static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
581 struct oxygen *chip = snd_pcm_substream_chip(substream);
582 struct snd_pcm_runtime *runtime = substream->runtime;
583 unsigned int channel = oxygen_substream_channel(substream);
586 /* no spinlock, this read should be atomic */
587 curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
588 return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
591 static struct snd_pcm_ops oxygen_rec_a_ops = {
592 .open = oxygen_rec_a_open,
593 .close = oxygen_close,
594 .ioctl = snd_pcm_lib_ioctl,
595 .hw_params = oxygen_rec_a_hw_params,
596 .hw_free = oxygen_hw_free,
597 .prepare = oxygen_prepare,
598 .trigger = oxygen_trigger,
599 .pointer = oxygen_pointer,
602 static struct snd_pcm_ops oxygen_rec_b_ops = {
603 .open = oxygen_rec_b_open,
604 .close = oxygen_close,
605 .ioctl = snd_pcm_lib_ioctl,
606 .hw_params = oxygen_rec_b_hw_params,
607 .hw_free = oxygen_hw_free,
608 .prepare = oxygen_prepare,
609 .trigger = oxygen_trigger,
610 .pointer = oxygen_pointer,
613 static struct snd_pcm_ops oxygen_rec_c_ops = {
614 .open = oxygen_rec_c_open,
615 .close = oxygen_close,
616 .ioctl = snd_pcm_lib_ioctl,
617 .hw_params = oxygen_rec_c_hw_params,
618 .hw_free = oxygen_hw_free,
619 .prepare = oxygen_prepare,
620 .trigger = oxygen_trigger,
621 .pointer = oxygen_pointer,
624 static struct snd_pcm_ops oxygen_spdif_ops = {
625 .open = oxygen_spdif_open,
626 .close = oxygen_close,
627 .ioctl = snd_pcm_lib_ioctl,
628 .hw_params = oxygen_spdif_hw_params,
629 .hw_free = oxygen_spdif_hw_free,
630 .prepare = oxygen_prepare,
631 .trigger = oxygen_trigger,
632 .pointer = oxygen_pointer,
635 static struct snd_pcm_ops oxygen_multich_ops = {
636 .open = oxygen_multich_open,
637 .close = oxygen_close,
638 .ioctl = snd_pcm_lib_ioctl,
639 .hw_params = oxygen_multich_hw_params,
640 .hw_free = oxygen_hw_free,
641 .prepare = oxygen_prepare,
642 .trigger = oxygen_trigger,
643 .pointer = oxygen_pointer,
646 static struct snd_pcm_ops oxygen_ac97_ops = {
647 .open = oxygen_ac97_open,
648 .close = oxygen_close,
649 .ioctl = snd_pcm_lib_ioctl,
650 .hw_params = oxygen_hw_params,
651 .hw_free = oxygen_hw_free,
652 .prepare = oxygen_prepare,
653 .trigger = oxygen_trigger,
654 .pointer = oxygen_pointer,
657 static void oxygen_pcm_free(struct snd_pcm *pcm)
659 snd_pcm_lib_preallocate_free_for_all(pcm);
662 int oxygen_pcm_init(struct oxygen *chip)
668 outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
669 ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
670 CAPTURE_0_FROM_I2S_2));
672 err = snd_pcm_new(chip->card, "Multichannel",
677 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
678 &oxygen_multich_ops);
679 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
680 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
682 else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
683 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
685 pcm->private_data = chip;
686 pcm->private_free = oxygen_pcm_free;
687 strcpy(pcm->name, "Multichannel");
689 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
691 snd_dma_pci_data(chip->pci),
692 DEFAULT_BUFFER_BYTES_MULTICH,
693 BUFFER_BYTES_MAX_MULTICH);
695 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
697 snd_dma_pci_data(chip->pci),
698 DEFAULT_BUFFER_BYTES,
702 outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
703 ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
705 err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
709 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
712 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
714 pcm->private_data = chip;
715 pcm->private_free = oxygen_pcm_free;
716 strcpy(pcm->name, "Digital");
717 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
718 snd_dma_pci_data(chip->pci),
719 DEFAULT_BUFFER_BYTES,
723 if (chip->has_ac97_1) {
724 outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
725 ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
728 ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
731 err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
736 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
738 oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
739 OXYGEN_REC_B_ROUTE_AC97_1,
740 OXYGEN_REC_B_ROUTE_MASK);
743 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
745 pcm->private_data = chip;
746 pcm->private_free = oxygen_pcm_free;
747 strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
748 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
749 snd_dma_pci_data(chip->pci),
750 DEFAULT_BUFFER_BYTES,