recipes/linux/logicpd-pxa270-2.6.19.2/pxa25x_cpufreq-r1.patch

   1 Index: git/arch/arm/Kconfig
   2 ===================================================================
   3 --- git.orig/arch/arm/Kconfig   2006-07-04 21:48:58.000000000 +0100
   4 +++ git/arch/arm/Kconfig        2006-07-05 09:46:49.000000000 +0100
   5 @@ -690,7 +690,7 @@
   6
   7  endmenu
   8
   9 -if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP)
  10 +if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA)
  11
  12  menu "CPU Frequency scaling"
  13
  14 @@ -717,6 +717,12 @@
  15
  16           If in doubt, say Y.
  17
  18 +config CPU_FREQ_PXA25x
  19 +       bool
  20 +       select CPU_FREQ_TABLE
  21 +       depends on CPU_FREQ && PXA25x
  22 +       default y
  23 +
  24  endmenu
  25
  26  endif
  27 Index: git/arch/arm/mach-pxa/Makefile
  28 ===================================================================
  29 --- git.orig/arch/arm/mach-pxa/Makefile 2006-07-05 09:44:45.000000000 +0100
  30 +++ git/arch/arm/mach-pxa/Makefile      2006-07-05 09:45:43.000000000 +0100
  31 @@ -29,6 +29,9 @@
  32
  33  obj-$(CONFIG_LEDS) += $(led-y)
  34
  35 +# CPU freq support
  36 +obj-$(CONFIG_CPU_FREQ_PXA25x) += cpu-pxa25x.o
  37 +
  38  # Misc features
  39  obj-$(CONFIG_PM) += pm.o sleep.o
  40  obj-$(CONFIG_PXA_KEYS) += pxa_keys.o
  41 Index: git/arch/arm/mach-pxa/cpu-pxa25x.c
  42 ===================================================================
  43 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  44 +++ git/arch/arm/mach-pxa/cpu-pxa25x.c  2006-07-05 09:45:43.000000000 +0100
  45 @@ -0,0 +1,353 @@
  46 +/*
  47 + *  linux/arch/arm/mach-pxa/cpu-pxa.c
  48 + *
  49 + *  Copyright (C) 2002,2003 Intrinsyc Software
  50 + *
  51 + * This program is free software; you can redistribute it and/or modify
  52 + * it under the terms of the GNU General Public License as published by
  53 + * the Free Software Foundation; either version 2 of the License, or
  54 + * (at your option) any later version.
  55 + *
  56 + * This program is distributed in the hope that it will be useful,
  57 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  58 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  59 + * GNU General Public License for more details.
  60 + *
  61 + * You should have received a copy of the GNU General Public License
  62 + * along with this program; if not, write to the Free Software
  63 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  64 + *
  65 + * History:
  66 + *   31-Jul-2002 : Initial version [FB]
  67 + *   29-Jan-2003 : added PXA255 support [FB]
  68 + *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
  69 + *   18-Jul-2005 : updated for latest kernel (2.6.13-rc), cleanup for submission
  70 + *                 (Ian Campbell, Arcom Control Systems)
  71 + *
  72 + * Note:
  73 + *   This driver may change the memory bus clock rate, but will not do any
  74 + *   platform specific access timing changes... for example if you have flash
  75 + *   memory connected to CS0, you will need to register a platform specific
  76 + *   notifier which will adjust the memory access strobes to maintain a
  77 + *   minimum strobe width.
  78 + *
  79 + */
  80 +
  81 +#include <linux/kernel.h>
  82 +#include <linux/module.h>
  83 +#include <linux/sched.h>
  84 +#include <linux/init.h>
  85 +#include <linux/cpufreq.h>
  86 +#include <linux/moduleparam.h>
  87 +
  88 +#include <asm/hardware.h>
  89 +
  90 +#include <asm/arch/pxa-regs.h>
  91 +
  92 +#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "pxa25x", msg)
  93 +
  94 +struct pxa_freqs {
  95 +       unsigned int khz;
  96 +       unsigned int membus;
  97 +       unsigned int cccr;
  98 +       unsigned int div2;
  99 +};
 100 +
 101 +/* Define the refresh period in mSec for the SDRAM and the number of rows */
 102 +#define SDRAM_TREF          64         /* standard 64ms SDRAM */
 103 +#define SDRAM_ROWS          8192       /* 64MB=8192 32MB=4096 */
 104 +#define MDREFR_DRI(x)       ((x*SDRAM_TREF)/(SDRAM_ROWS*32))
 105 +
 106 +#define CCLKCFG_TURBO       0x1
 107 +#define CCLKCFG_FCS         0x2
 108 +#define PXA25x_MIN_FREQ     99532
 109 +#define PXA25x_MAX_FREQ     398131
 110 +#define MDREFR_DB2_MASK     (MDREFR_K2DB2 | MDREFR_K1DB2)
 111 +#define MDREFR_DRI_MASK     0xFFF
 112 +
 113 +/* Use the run mode frequencies for performance */
 114 +static struct pxa_freqs pxa25x_performance_freqs[] = {
 115 +       /* CPU   MEMBUS  CCCR   DIV2 */
 116 +       {99532,   99532, 0x121, 1},     /* run= 99, turbo= 99, PXbus=50,  SDRAM=50 */
 117 +       {132710, 132710, 0x123, 1},     /* run=133, turbo=133, PXbus=66,  SDRAM=66 */
 118 +       {199065,  99532, 0x141, 0},     /* run=199, turbo=199, PXbus=99,  SDRAM=99 */
 119 +       {265421, 132710, 0x143, 1},     /* run=265, turbo=265, PXbus=133, SDRAM=66 */
 120 +       {331776, 165888, 0x145, 1},     /* run=331, turbo=331, PXbus=166, SDRAM=83 */
 121 +       {398131,  99532, 0x161, 0},     /* run=398, turbo=398, PXbus=196, SDRAM=99 */
 122 +};
 123 +
 124 +static struct cpufreq_frequency_table pxa25x_performance_freq_table[ARRAY_SIZE(pxa25x_performance_freqs)+1];
 125 +
 126 +/* Use the turbo mode frequencies for powersave */
 127 +static struct pxa_freqs pxa25x_powersave_freqs[] = {
 128 +       /* CPU   MEMBUS CCCR   DIV2 */
 129 +       {99532,  99532, 0x121, 1},      /* run=99,  turbo= 99, PXbus=50, SDRAM=50 */
 130 +       {199065, 99532, 0x221, 0},      /* run=99,  turbo=199, PXbus=50, SDRAM=99 */
 131 +       {298598, 99532, 0x321, 0},      /* run=99,  turbo=287, PXbus=50, SDRAM=99 */
 132 +       {398131, 99532, 0x241, 0},      /* run=199, turbo=398, PXbus=99, SDRAM=99 */
 133 +};
 134 +
 135 +static struct cpufreq_frequency_table pxa25x_powersave_freq_table[ARRAY_SIZE(pxa25x_powersave_freqs)+1];
 136 +
 137 +extern unsigned get_clk_frequency_khz(int info);
 138 +
 139 +static unsigned int max_frequency = PXA25x_MAX_FREQ;
 140 +static int performance = 0;
 141 +
 142 +/*
 143 + * This option can be used if you have one of the 200MHz PXA25x parts by adding
 144 + * cpu_pxa25x.max_frequency=199065 to the kernel command line
 145 + */
 146 +module_param(max_frequency, int, 0);
 147 +MODULE_PARM_DESC(max_frequency, "Set the maximum cpu frequency");
 148 +
 149 +module_param(performance, int, 0);
 150 +MODULE_PARM_DESC(performance, "Use performance instead of powersave frequency tables");
 151 +
 152 +static void pxa_select_freq_table(struct cpufreq_policy *policy,
 153 +                                 struct pxa_freqs ** settings,
 154 +                                 struct cpufreq_frequency_table **table)
 155 +{
 156 +       cpufreq_frequency_table_put_attr(policy->cpu);
 157 +
 158 +       if (performance) {
 159 +               dprintk("selecting performance tables\n");
 160 +               cpufreq_frequency_table_get_attr(pxa25x_performance_freq_table, policy->cpu);
 161 +               if (settings)
 162 +                       *settings = pxa25x_performance_freqs;
 163 +               if (table)
 164 +                       *table = pxa25x_performance_freq_table;
 165 +       } else {
 166 +               dprintk("selecting powersave tables\n");
 167 +               cpufreq_frequency_table_get_attr(pxa25x_powersave_freq_table, policy->cpu);
 168 +               if (settings)
 169 +                       *settings = pxa25x_powersave_freqs;
 170 +               if (table)
 171 +                       *table = pxa25x_powersave_freq_table;
 172 +       }
 173 +}
 174 +
 175 +/* find a valid frequency point */
 176 +static int pxa_verify_policy(struct cpufreq_policy *policy)
 177 +{
 178 +       int ret;
 179 +       struct cpufreq_frequency_table *pxa_freqs_table;
 180 +
 181 +       pxa_select_freq_table(policy, NULL, &pxa_freqs_table);
 182 +
 183 +       ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
 184 +
 185 +       dprintk("verified CPU policy: %dKhz min to %dKhz max\n",
 186 +               policy->min, policy->max);
 187 +
 188 +       return ret;
 189 +}
 190 +
 191 +static int pxa_set_target(struct cpufreq_policy *policy,
 192 +                         unsigned int target_freq, unsigned int relation)
 193 +{
 194 +       int idx;
 195 +       struct cpufreq_freqs freqs;
 196 +       struct pxa_freqs *pxa_freq_settings;
 197 +       struct cpufreq_frequency_table *pxa_freqs_table;
 198 +       unsigned long flags;
 199 +       unsigned int unused;
 200 +       unsigned int preset_mdrefr, postset_mdrefr;
 201 +       void *ramstart;
 202 +
 203 +       /* Get the current policy */
 204 +       pxa_select_freq_table(policy, &pxa_freq_settings, &pxa_freqs_table);
 205 +
 206 +       /* Lookup the next frequency */
 207 +       if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
 208 +                                          target_freq, relation, &idx))
 209 +               return -EINVAL;
 210 +
 211 +       freqs.old = get_clk_frequency_khz(0);
 212 +       freqs.new = pxa_freq_settings[idx].khz;
 213 +       freqs.cpu = policy->cpu;
 214 +
 215 +       if (freqs.new == freqs.old && pxa_freq_settings[idx].cccr == CCCR)
 216 +               return 0;
 217 +
 218 +       dprintk("changing CPU frequency to %d.%03d Mhz (SDRAM %d Mhz, CCCR %#04x)\n",
 219 +               freqs.new / 1000, freqs.new % 1000,
 220 +               (pxa_freq_settings[idx].div2) ?
 221 +               (pxa_freq_settings[idx].membus / 2000) :
 222 +               (pxa_freq_settings[idx].membus / 1000),
 223 +               pxa_freq_settings[idx].cccr);
 224 +
 225 +       ramstart = phys_to_virt(0xa0000000);
 226 +
 227 +       /*
 228 +        * Tell everyone what we're about to do...
 229 +        * you should add a notify client with any platform specific
 230 +        * Vcc changing capability
 231 +        */
 232 +       cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 233 +
 234 +       /* Calculate the next MDREFR.  If we're slowing down the SDRAM clock
 235 +        * we need to preset the smaller DRI before the change.  If we're speeding
 236 +        * up we need to set the larger DRI value after the change.
 237 +        */
 238 +       preset_mdrefr = postset_mdrefr = MDREFR;
 239 +       if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) {
 240 +               preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
 241 +                       MDREFR_DRI(pxa_freq_settings[idx].membus);
 242 +       }
 243 +       postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
 244 +               MDREFR_DRI(pxa_freq_settings[idx].membus);
 245 +
 246 +       /* If we're dividing the memory clock by two for the SDRAM clock, this
 247 +        * must be set prior to the change.  Clearing the divide must be done
 248 +        * after the change.
 249 +        */
 250 +       if (pxa_freq_settings[idx].div2) {
 251 +               preset_mdrefr |= MDREFR_DB2_MASK;
 252 +               postset_mdrefr |= MDREFR_DB2_MASK;
 253 +       } else {
 254 +               postset_mdrefr &= ~MDREFR_DB2_MASK;
 255 +       }
 256 +
 257 +       local_irq_save(flags);
 258 +
 259 +       /* Set new the CCCR */
 260 +       CCCR = pxa_freq_settings[idx].cccr;
 261 +
 262 +       __asm__ __volatile__("                              \
 263 +        ldr r4, [%1] ;          /* load MDREFR */           \
 264 +        b   2f ;                                            \
 265 +        .align  5 ;                                         \
 266 +1:                                                          \
 267 +        str %4, [%1] ;          /* preset the MDREFR */     \
 268 +        mcr p14, 0, %2, c6, c0, 0 ; /* set CCLKCFG[FCS] */  \
 269 +        str %5, [%1] ;          /* postset the MDREFR */    \
 270 +                                                            \
 271 +        b   3f       ;                                      \
 272 +2:      b   1b       ;                                      \
 273 +3:      nop          ;                                      \
 274 +        "
 275 +       : "=&r"(unused)
 276 +       : "r"(&MDREFR), "r"(CCLKCFG_TURBO | CCLKCFG_FCS),
 277 +         "r"(ramstart), "r"(preset_mdrefr),
 278 +         "r"(postset_mdrefr)
 279 +       : "r4", "r5");
 280 +       local_irq_restore(flags);
 281 +
 282 +       /*
 283 +        * Tell everyone what we've just done...
 284 +        * you should add a notify client with any platform specific
 285 +        * SDRAM refresh timer adjustments
 286 +        */
 287 +       cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 288 +
 289 +       return 0;
 290 +}
 291 +
 292 +static unsigned int pxa_cpufreq_get(unsigned int cpu)
 293 +{
 294 +       return get_clk_frequency_khz(0);
 295 +}
 296 +
 297 +static int pxa_cpufreq_init(struct cpufreq_policy *policy)
 298 +{
 299 +       int i;
 300 +
 301 +       if (policy->cpu != 0)
 302 +               return -ENODEV;
 303 +
 304 +       /* set default policy and cpuinfo */
 305 +       policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 306 +       policy->cpuinfo.max_freq = max_frequency;
 307 +       policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
 308 +       policy->cpuinfo.transition_latency = 1000000;   /* FIXME: 1 ms, assumed */
 309 +       policy->cur = get_clk_frequency_khz(0);         /* current freq */
 310 +       policy->min = policy->max = policy->cur;
 311 +       policy->min = pxa25x_powersave_freqs[0].khz;
 312 +       policy->max = pxa25x_powersave_freqs[sizeof(pxa25x_powersave_freqs)/sizeof(*pxa25x_powersave_freqs)-1].khz;
 313 +
 314 +       /* Generate the run cpufreq_frequency_table struct */
 315 +       for (i = 0; i < ARRAY_SIZE(pxa25x_performance_freqs); i++) {
 316 +               pxa25x_performance_freq_table[i].frequency = pxa25x_performance_freqs[i].khz;
 317 +               pxa25x_performance_freq_table[i].index = i;
 318 +       }
 319 +       pxa25x_performance_freq_table[i].frequency = CPUFREQ_TABLE_END;
 320 +
 321 +       /* Generate the turbo cpufreq_frequency_table struct */
 322 +       for (i = 0; i < ARRAY_SIZE(pxa25x_powersave_freqs); i++) {
 323 +               pxa25x_powersave_freq_table[i].frequency = pxa25x_powersave_freqs[i].khz;
 324 +               pxa25x_powersave_freq_table[i].index = i;
 325 +       }
 326 +       pxa25x_powersave_freq_table[i].frequency = CPUFREQ_TABLE_END;
 327 +
 328 +       /* calls cpufreq_frequency_table_get_attr */
 329 +       pxa_select_freq_table(policy, NULL, NULL);
 330 +
 331 +       printk(KERN_INFO "pxa25x: CPU frequency change support initialized (%s tables)\n",
 332 +              performance ? "performance" : "powersave");
 333 +
 334 +       return 0;
 335 +}
 336 +
 337 +static ssize_t show_pxa25x_freq_model_attr(struct cpufreq_policy * policy, char *buf)
 338 +{
 339 +       return sprintf (buf, "%s\n", performance ? "performance" : "powersave");
 340 +}
 341 +
 342 +static ssize_t store_pxa25x_freq_model_attr(struct cpufreq_policy * policy, const char *buf, size_t count)
 343 +{
 344 +       unsigned int ret;
 345 +       char str[16];
 346 +
 347 +       ret = sscanf(buf, "%15s", str);
 348 +       if (ret != 1)
 349 +               return -EINVAL;
 350 +
 351 +       if (strnicmp(str,"performance",16)==0)
 352 +               performance = 1;
 353 +       else if (strnicmp(str,"powersave",16)==0)
 354 +               performance = 0;
 355 +       else
 356 +               return -EINVAL;
 357 +
 358 +       ret = cpufreq_update_policy(policy->cpu);
 359 +
 360 +       return ret ? ret : count;
 361 +}
 362 +
 363 +struct freq_attr pxa25x_freq_model_attr = {
 364 +       .attr = { .name = "pxa25x_freq_model", .mode = 0644, .owner=THIS_MODULE },
 365 +       .show = show_pxa25x_freq_model_attr,
 366 +       .store = store_pxa25x_freq_model_attr,
 367 +};
 368 +
 369 +static struct freq_attr* pxa_cpufreq_attr[] = {
 370 +        &cpufreq_freq_attr_scaling_available_freqs,
 371 +       &pxa25x_freq_model_attr,
 372 +        NULL,
 373 +};
 374 +
 375 +static struct cpufreq_driver pxa_cpufreq_driver = {
 376 +       .verify = pxa_verify_policy,
 377 +       .target = pxa_set_target,
 378 +       .init   = pxa_cpufreq_init,
 379 +       .get    = pxa_cpufreq_get,
 380 +       .name   = "pxa25x",
 381 +       .attr   = pxa_cpufreq_attr,
 382 +};
 383 +
 384 +static int __init pxa_cpu_init(void)
 385 +{
 386 +       return cpufreq_register_driver(&pxa_cpufreq_driver);
 387 +}
 388 +
 389 +static void __exit pxa_cpu_exit(void)
 390 +{
 391 +       cpufreq_unregister_driver(&pxa_cpufreq_driver);
 392 +}
 393 +
 394 +MODULE_AUTHOR("Intrinsyc Software Inc.");
 395 +MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
 396 +MODULE_LICENSE("GPL");
 397 +module_init(pxa_cpu_init);
 398 +module_exit(pxa_cpu_exit);