pvr/sgxinit.c

   1 /**********************************************************************
   2  *
   3  * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful but, except
  10  * as otherwise stated in writing, without any warranty; without even the
  11  * implied warranty of merchantability or fitness for a particular purpose.
  12  * See the GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * Imagination Technologies Ltd. <gpl-support@imgtec.com>
  23  * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
  24  *
  25  ******************************************************************************/
  26
  27 #include <stddef.h>
  28
  29 #include <linux/workqueue.h>
  30 #include <linux/io.h>
  31 #include <linux/slab.h>
  32 #include <linux/sched.h>
  33
  34 #include "sgxdefs.h"
  35 #include "sgxmmu.h"
  36 #include "services_headers.h"
  37 #include "buffer_manager.h"
  38 #include "sgxapi_km.h"
  39 #include "sgxinfo.h"
  40 #include "sgxinfokm.h"
  41 #include "sgxconfig.h"
  42 #include "sysconfig.h"
  43 #include "pvr_bridge_km.h"
  44 #include "sgx_bridge_km.h"
  45 #include "resman.h"
  46
  47 #include "pdump_km.h"
  48 #include "ra.h"
  49 #include "mmu.h"
  50 #include "handle.h"
  51 #include "perproc.h"
  52
  53 #include "sgxutils.h"
  54 #include "pvrversion.h"
  55 #include "sgx_options.h"
  56
  57 static IMG_BOOL SGX_ISRHandler(void *pvData);
  58
  59 static u32 gui32EventStatusServicesByISR;
  60
  61 static enum PVRSRV_ERROR SGXGetBuildInfoKM(struct PVRSRV_SGXDEV_INFO *psDevInfo,
  62                                     struct PVRSRV_DEVICE_NODE *psDeviceNode);
  63
  64 static void SGXCommandComplete(struct PVRSRV_DEVICE_NODE *psDeviceNode)
  65 {
  66         BUG_ON(in_irq());
  67
  68         SGXScheduleProcessQueuesKM(psDeviceNode);
  69 }
  70
  71 static u32 DeinitDevInfo(struct PVRSRV_SGXDEV_INFO *psDevInfo)
  72 {
  73         if (psDevInfo->psKernelCCBInfo != NULL)
  74                 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
  75                           sizeof(struct PVRSRV_SGX_CCB_INFO),
  76                           psDevInfo->psKernelCCBInfo, NULL);
  77
  78         return PVRSRV_OK;
  79 }
  80
  81 static enum PVRSRV_ERROR InitDevInfo(struct PVRSRV_PER_PROCESS_DATA *psPerProc,
  82                                 struct PVRSRV_DEVICE_NODE *psDeviceNode,
  83                                 struct SGX_BRIDGE_INIT_INFO *psInitInfo)
  84 {
  85         struct PVRSRV_SGXDEV_INFO *psDevInfo =
  86             (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
  87         enum PVRSRV_ERROR eError;
  88
  89         struct PVRSRV_SGX_CCB_INFO *psKernelCCBInfo = NULL;
  90
  91         PVR_UNREFERENCED_PARAMETER(psPerProc);
  92         psDevInfo->sScripts = psInitInfo->sScripts;
  93
  94         psDevInfo->psKernelCCBMemInfo =
  95             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelCCBMemInfo;
  96         psDevInfo->psKernelCCB =
  97             (struct PVRSRV_SGX_KERNEL_CCB *)psDevInfo->psKernelCCBMemInfo->
  98                                                     pvLinAddrKM;
  99
 100         psDevInfo->psKernelCCBCtlMemInfo =
 101             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelCCBCtlMemInfo;
 102         psDevInfo->psKernelCCBCtl =
 103             (struct PVRSRV_SGX_CCB_CTL *)psDevInfo->psKernelCCBCtlMemInfo->
 104                                                     pvLinAddrKM;
 105
 106         psDevInfo->psKernelCCBEventKickerMemInfo =
 107             (struct PVRSRV_KERNEL_MEM_INFO *)
 108                             psInitInfo->hKernelCCBEventKickerMemInfo;
 109         psDevInfo->pui32KernelCCBEventKicker =
 110             (u32 *)psDevInfo->psKernelCCBEventKickerMemInfo->pvLinAddrKM;
 111
 112         psDevInfo->psKernelSGXHostCtlMemInfo =
 113             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->
 114                                                     hKernelSGXHostCtlMemInfo;
 115         psDevInfo->psSGXHostCtl = (struct SGXMKIF_HOST_CTL __force __iomem *)
 116                 psDevInfo->psKernelSGXHostCtlMemInfo->pvLinAddrKM;
 117
 118         psDevInfo->psKernelSGXTA3DCtlMemInfo =
 119             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->
 120                                                     hKernelSGXTA3DCtlMemInfo;
 121
 122         psDevInfo->psKernelSGXMiscMemInfo =
 123             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXMiscMemInfo;
 124
 125         psDevInfo->psKernelHWPerfCBMemInfo =
 126             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelHWPerfCBMemInfo;
 127 #ifdef PVRSRV_USSE_EDM_STATUS_DEBUG
 128         psDevInfo->psKernelEDMStatusBufferMemInfo =
 129             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->
 130                                                   hKernelEDMStatusBufferMemInfo;
 131 #endif
 132
 133         eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
 134                             sizeof(struct PVRSRV_SGX_CCB_INFO),
 135                             (void **)&psKernelCCBInfo, NULL);
 136         if (eError != PVRSRV_OK) {
 137                 PVR_DPF(PVR_DBG_ERROR, "InitDevInfo: Failed to alloc memory");
 138                 goto failed_allockernelccb;
 139         }
 140
 141         OSMemSet(psKernelCCBInfo, 0, sizeof(struct PVRSRV_SGX_CCB_INFO));
 142         psKernelCCBInfo->psCCBMemInfo = psDevInfo->psKernelCCBMemInfo;
 143         psKernelCCBInfo->psCCBCtlMemInfo = psDevInfo->psKernelCCBCtlMemInfo;
 144         psKernelCCBInfo->psCommands = psDevInfo->psKernelCCB->asCommands;
 145         psKernelCCBInfo->pui32WriteOffset =
 146                                 &psDevInfo->psKernelCCBCtl->ui32WriteOffset;
 147         psKernelCCBInfo->pui32ReadOffset =
 148                                 &psDevInfo->psKernelCCBCtl->ui32ReadOffset;
 149         psDevInfo->psKernelCCBInfo = psKernelCCBInfo;
 150
 151         psDevInfo->ui32HostKickAddress = psInitInfo->ui32HostKickAddress;
 152
 153         psDevInfo->ui32GetMiscInfoAddress = psInitInfo->ui32GetMiscInfoAddress;
 154
 155         psDevInfo->bForcePTOff = IMG_FALSE;
 156
 157         psDevInfo->ui32CacheControl = psInitInfo->ui32CacheControl;
 158
 159         psDevInfo->ui32EDMTaskReg0 = psInitInfo->ui32EDMTaskReg0;
 160         psDevInfo->ui32EDMTaskReg1 = psInitInfo->ui32EDMTaskReg1;
 161         psDevInfo->ui32ClkGateStatusReg = psInitInfo->ui32ClkGateStatusReg;
 162         psDevInfo->ui32ClkGateStatusMask = psInitInfo->ui32ClkGateStatusMask;
 163
 164         OSMemCopy(&psDevInfo->asSGXDevData, &psInitInfo->asInitDevData,
 165                   sizeof(psDevInfo->asSGXDevData));
 166
 167         return PVRSRV_OK;
 168
 169 failed_allockernelccb:
 170         DeinitDevInfo(psDevInfo);
 171
 172         return eError;
 173 }
 174
 175 static enum PVRSRV_ERROR SGXRunScript(struct PVRSRV_SGXDEV_INFO *psDevInfo,
 176                                  union SGX_INIT_COMMAND *psScript,
 177                                  u32 ui32NumInitCommands)
 178 {
 179         u32 ui32PC;
 180         union SGX_INIT_COMMAND *psComm;
 181
 182         for (ui32PC = 0, psComm = psScript;
 183              ui32PC < ui32NumInitCommands; ui32PC++, psComm++) {
 184                 switch (psComm->eOp) {
 185                 case SGX_INIT_OP_WRITE_HW_REG:
 186                         {
 187                                 OSWriteHWReg(psDevInfo->pvRegsBaseKM,
 188                                              psComm->sWriteHWReg.ui32Offset,
 189                                              psComm->sWriteHWReg.ui32Value);
 190                                 PDUMPREG(psComm->sWriteHWReg.ui32Offset,
 191                                          psComm->sWriteHWReg.ui32Value);
 192                                 break;
 193                         }
 194 #if defined(PDUMP)
 195                 case SGX_INIT_OP_PDUMP_HW_REG:
 196                         {
 197                                 PDUMPREG(psComm->sPDumpHWReg.ui32Offset,
 198                                          psComm->sPDumpHWReg.ui32Value);
 199                                 break;
 200                         }
 201 #endif
 202                 case SGX_INIT_OP_HALT:
 203                         {
 204                                 return PVRSRV_OK;
 205                         }
 206                 case SGX_INIT_OP_ILLEGAL:
 207
 208                 default:
 209                         {
 210                                 PVR_DPF(PVR_DBG_ERROR,
 211                                      "SGXRunScript: PC %d: Illegal command: %d",
 212                                       ui32PC, psComm->eOp);
 213                                 return PVRSRV_ERROR_GENERIC;
 214                         }
 215                 }
 216
 217         }
 218
 219         return PVRSRV_ERROR_GENERIC;
 220 }
 221
 222 enum PVRSRV_ERROR SGXInitialise(struct PVRSRV_SGXDEV_INFO *psDevInfo,
 223                                   IMG_BOOL bHardwareRecovery)
 224 {
 225         enum PVRSRV_ERROR eError;
 226
 227         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 228                               "SGX initialisation script part 1\n");
 229         eError =
 230             SGXRunScript(psDevInfo, psDevInfo->sScripts.asInitCommandsPart1,
 231                          SGX_MAX_INIT_COMMANDS);
 232         if (eError != PVRSRV_OK) {
 233                 PVR_DPF(PVR_DBG_ERROR,
 234                          "SGXInitialise: SGXRunScript (part 1) failed (%d)",
 235                          eError);
 236                 return PVRSRV_ERROR_GENERIC;
 237         }
 238         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 239                               "End of SGX initialisation script part 1\n");
 240
 241         SGXReset(psDevInfo, PDUMP_FLAGS_CONTINUOUS);
 242
 243
 244
 245         *psDevInfo->pui32KernelCCBEventKicker = 0;
 246 #if defined(PDUMP)
 247         PDUMPMEM(NULL, psDevInfo->psKernelCCBEventKickerMemInfo, 0,
 248                  sizeof(*psDevInfo->pui32KernelCCBEventKicker),
 249                  PDUMP_FLAGS_CONTINUOUS,
 250                  MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
 251 #endif
 252
 253         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 254                               "SGX initialisation script part 2\n");
 255         eError =
 256             SGXRunScript(psDevInfo, psDevInfo->sScripts.asInitCommandsPart2,
 257                          SGX_MAX_INIT_COMMANDS);
 258         if (eError != PVRSRV_OK) {
 259                 PVR_DPF(PVR_DBG_ERROR,
 260                          "SGXInitialise: SGXRunScript (part 2) failed (%d)",
 261                          eError);
 262                 return PVRSRV_ERROR_GENERIC;
 263         }
 264         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 265                               "End of SGX initialisation script part 2\n");
 266
 267         SGXStartTimer(psDevInfo, (IMG_BOOL)!bHardwareRecovery);
 268
 269         if (bHardwareRecovery) {
 270                 struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 271                     psDevInfo->psSGXHostCtl;
 272
 273                 if (PollForValueKM(&psSGXHostCtl->ui32InterruptClearFlags, 0,
 274                      PVRSRV_USSE_EDM_INTERRUPT_HWR,
 275                      MAX_HW_TIME_US / WAIT_TRY_COUNT, 1000) != PVRSRV_OK) {
 276                         PVR_DPF(PVR_DBG_ERROR, "SGXInitialise: "
 277                                         "Wait for uKernel HW Recovery failed");
 278                         PVR_DBG_BREAK;
 279                         return PVRSRV_ERROR_RETRY;
 280                 }
 281         }
 282
 283         PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset ==
 284                    psDevInfo->psKernelCCBCtl->ui32WriteOffset);
 285
 286         return PVRSRV_OK;
 287 }
 288
 289 enum PVRSRV_ERROR SGXDeinitialise(void *hDevCookie)
 290 {
 291         struct PVRSRV_SGXDEV_INFO *psDevInfo = (struct PVRSRV_SGXDEV_INFO *)
 292                                                                    hDevCookie;
 293         enum PVRSRV_ERROR eError;
 294
 295         if (psDevInfo->pvRegsBaseKM == NULL)
 296                 return PVRSRV_OK;
 297
 298         eError = SGXRunScript(psDevInfo, psDevInfo->sScripts.asDeinitCommands,
 299                          SGX_MAX_DEINIT_COMMANDS);
 300         if (eError != PVRSRV_OK) {
 301                 PVR_DPF(PVR_DBG_ERROR,
 302                          "SGXDeinitialise: SGXRunScript failed (%d)", eError);
 303                 return PVRSRV_ERROR_GENERIC;
 304         }
 305
 306         return PVRSRV_OK;
 307 }
 308
 309 static enum PVRSRV_ERROR DevInitSGXPart1(void *pvDeviceNode)
 310 {
 311         struct PVRSRV_SGXDEV_INFO *psDevInfo;
 312         void *hKernelDevMemContext;
 313         struct IMG_DEV_PHYADDR sPDDevPAddr;
 314         u32 i;
 315         struct PVRSRV_DEVICE_NODE *psDeviceNode = (struct PVRSRV_DEVICE_NODE *)
 316                                                                    pvDeviceNode;
 317         struct DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap =
 318             psDeviceNode->sDevMemoryInfo.psDeviceMemoryHeap;
 319         enum PVRSRV_ERROR eError;
 320
 321         PDUMPCOMMENT("SGX Initialisation Part 1");
 322
 323         PDUMPCOMMENT("SGX Core Version Information: %s",
 324                      SGX_CORE_FRIENDLY_NAME);
 325         PDUMPCOMMENT("SGX Core Revision Information: multi rev support");
 326
 327         if (OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 328                        sizeof(struct PVRSRV_SGXDEV_INFO),
 329                        (void **)&psDevInfo, NULL) != PVRSRV_OK) {
 330                 PVR_DPF(PVR_DBG_ERROR,
 331                         "DevInitSGXPart1 : Failed to alloc memory for DevInfo");
 332                 return PVRSRV_ERROR_OUT_OF_MEMORY;
 333         }
 334         OSMemSet(psDevInfo, 0, sizeof(struct PVRSRV_SGXDEV_INFO));
 335
 336         psDevInfo->eDeviceType = DEV_DEVICE_TYPE;
 337         psDevInfo->eDeviceClass = DEV_DEVICE_CLASS;
 338
 339         psDeviceNode->pvDevice = (void *) psDevInfo;
 340
 341         psDevInfo->pvDeviceMemoryHeap = (void *) psDeviceMemoryHeap;
 342
 343         hKernelDevMemContext = BM_CreateContext(psDeviceNode, &sPDDevPAddr,
 344                                                 NULL, NULL);
 345
 346         psDevInfo->sKernelPDDevPAddr = sPDDevPAddr;
 347
 348         for (i = 0; i < psDeviceNode->sDevMemoryInfo.ui32HeapCount; i++) {
 349                 void *hDevMemHeap;
 350
 351                 switch (psDeviceMemoryHeap[i].DevMemHeapType) {
 352                 case DEVICE_MEMORY_HEAP_KERNEL:
 353                 case DEVICE_MEMORY_HEAP_SHARED:
 354                 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
 355                         {
 356                                 hDevMemHeap =
 357                                     BM_CreateHeap(hKernelDevMemContext,
 358                                                   &psDeviceMemoryHeap[i]);
 359
 360                                 psDeviceMemoryHeap[i].hDevMemHeap = hDevMemHeap;
 361                                 break;
 362                         }
 363                 }
 364         }
 365
 366         eError = MMU_BIFResetPDAlloc(psDevInfo);
 367         if (eError != PVRSRV_OK) {
 368                 PVR_DPF(PVR_DBG_ERROR,
 369                          "DevInitSGX : Failed to alloc memory for BIF reset");
 370                 return PVRSRV_ERROR_GENERIC;
 371         }
 372
 373         return PVRSRV_OK;
 374 }
 375
 376 enum PVRSRV_ERROR SGXGetInfoForSrvinitKM(void *hDevHandle,
 377                                 struct SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo)
 378 {
 379         struct PVRSRV_DEVICE_NODE *psDeviceNode;
 380         struct PVRSRV_SGXDEV_INFO *psDevInfo;
 381         enum PVRSRV_ERROR eError;
 382
 383         PDUMPCOMMENT("SGXGetInfoForSrvinit");
 384
 385         psDeviceNode = (struct PVRSRV_DEVICE_NODE *)hDevHandle;
 386         psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 387
 388         psInitInfo->sPDDevPAddr = psDevInfo->sKernelPDDevPAddr;
 389
 390         eError =
 391             PVRSRVGetDeviceMemHeapsKM(hDevHandle, &psInitInfo->asHeapInfo[0]);
 392         if (eError != PVRSRV_OK) {
 393                 PVR_DPF(PVR_DBG_ERROR, "SGXGetInfoForSrvinit: "
 394                                 "PVRSRVGetDeviceMemHeapsKM failed (%d)",
 395                          eError);
 396                 return PVRSRV_ERROR_GENERIC;
 397         }
 398
 399         return eError;
 400 }
 401
 402 enum PVRSRV_ERROR DevInitSGXPart2KM(struct PVRSRV_PER_PROCESS_DATA *psPerProc,
 403                                    void *hDevHandle,
 404                                    struct SGX_BRIDGE_INIT_INFO *psInitInfo)
 405 {
 406         struct PVRSRV_DEVICE_NODE *psDeviceNode;
 407         struct PVRSRV_SGXDEV_INFO *psDevInfo;
 408         enum PVRSRV_ERROR eError;
 409         struct SGX_DEVICE_MAP *psSGXDeviceMap;
 410         enum PVR_POWER_STATE eDefaultPowerState;
 411         u32 l;
 412
 413         PDUMPCOMMENT("SGX Initialisation Part 2");
 414
 415         psDeviceNode = (struct PVRSRV_DEVICE_NODE *)hDevHandle;
 416         psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 417
 418         eError = InitDevInfo(psPerProc, psDeviceNode, psInitInfo);
 419         if (eError != PVRSRV_OK) {
 420                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM: "
 421                                         "Failed to load EDM program");
 422                 goto failed_init_dev_info;
 423         }
 424
 425
 426         eError = SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
 427                                        (void **) &psSGXDeviceMap);
 428         if (eError != PVRSRV_OK) {
 429                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM: "
 430                                         "Failed to get device memory map!");
 431                 return PVRSRV_ERROR_INIT_FAILURE;
 432         }
 433
 434         if (psSGXDeviceMap->pvRegsCpuVBase) {
 435                 psDevInfo->pvRegsBaseKM = psSGXDeviceMap->pvRegsCpuVBase;
 436         } else {
 437                 psDevInfo->pvRegsBaseKM =
 438                     OSMapPhysToLin(psSGXDeviceMap->sRegsCpuPBase,
 439                                    psSGXDeviceMap->ui32RegsSize,
 440                                    PVRSRV_HAP_KERNEL_ONLY | PVRSRV_HAP_UNCACHED,
 441                                    NULL);
 442                 if (!psDevInfo->pvRegsBaseKM) {
 443                         PVR_DPF(PVR_DBG_ERROR,
 444                                  "DevInitSGXPart2KM: Failed to map in regs\n");
 445                         return PVRSRV_ERROR_BAD_MAPPING;
 446                 }
 447         }
 448         psDevInfo->ui32RegSize = psSGXDeviceMap->ui32RegsSize;
 449         psDevInfo->sRegsPhysBase = psSGXDeviceMap->sRegsSysPBase;
 450
 451         psDeviceNode->pvISRData = psDeviceNode;
 452
 453         PVR_ASSERT(psDeviceNode->pfnDeviceISR == SGX_ISRHandler);
 454
 455         pvr_dev_lock();
 456         l = readl(&psDevInfo->psSGXHostCtl->ui32PowerStatus);
 457         l |= PVRSRV_USSE_EDM_POWMAN_NO_WORK;
 458         writel(l, &psDevInfo->psSGXHostCtl->ui32PowerStatus);
 459         pvr_dev_unlock();
 460         eDefaultPowerState = PVRSRV_POWER_STATE_D3;
 461
 462         eError = PVRSRVRegisterPowerDevice(psDeviceNode->sDevId.ui32DeviceIndex,
 463                                            SGXPrePowerStateExt,
 464                                            SGXPostPowerStateExt,
 465                                            SGXPreClockSpeedChange,
 466                                            SGXPostClockSpeedChange,
 467                                            (void *) psDeviceNode,
 468                                            PVRSRV_POWER_STATE_D3,
 469                                            eDefaultPowerState);
 470         if (eError != PVRSRV_OK) {
 471                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM: "
 472                                 "failed to register device with power manager");
 473                 return eError;
 474         }
 475
 476         OSMemSet(psDevInfo->psKernelCCB, 0,
 477                  sizeof(struct PVRSRV_SGX_KERNEL_CCB));
 478         OSMemSet(psDevInfo->psKernelCCBCtl, 0,
 479                  sizeof(struct PVRSRV_SGX_CCB_CTL));
 480         OSMemSet(psDevInfo->pui32KernelCCBEventKicker, 0,
 481                  sizeof(*psDevInfo->pui32KernelCCBEventKicker));
 482         PDUMPCOMMENT("Initialise Kernel CCB");
 483         PDUMPMEM(NULL, psDevInfo->psKernelCCBMemInfo, 0,
 484                  sizeof(struct PVRSRV_SGX_KERNEL_CCB), PDUMP_FLAGS_CONTINUOUS,
 485                  MAKEUNIQUETAG(psDevInfo->psKernelCCBMemInfo));
 486         PDUMPCOMMENT("Initialise Kernel CCB Control");
 487         PDUMPMEM(NULL, psDevInfo->psKernelCCBCtlMemInfo, 0,
 488                  sizeof(struct PVRSRV_SGX_CCB_CTL), PDUMP_FLAGS_CONTINUOUS,
 489                  MAKEUNIQUETAG(psDevInfo->psKernelCCBCtlMemInfo));
 490         PDUMPCOMMENT("Initialise Kernel CCB Event Kicker");
 491         PDUMPMEM(NULL, psDevInfo->psKernelCCBEventKickerMemInfo, 0,
 492                  sizeof(*psDevInfo->pui32KernelCCBEventKicker),
 493                  PDUMP_FLAGS_CONTINUOUS,
 494                  MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
 495
 496         psDevInfo->hTimer = SGXOSTimerInit(psDeviceNode);
 497         if (!psDevInfo->hTimer)
 498                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM : "
 499                         "Failed to initialize HW recovery timer");
 500
 501         return PVRSRV_OK;
 502
 503 failed_init_dev_info:
 504         return eError;
 505 }
 506
 507 static enum PVRSRV_ERROR DevDeInitSGX(void *pvDeviceNode)
 508 {
 509         struct PVRSRV_DEVICE_NODE *psDeviceNode =
 510                 (struct PVRSRV_DEVICE_NODE *)pvDeviceNode;
 511         struct PVRSRV_SGXDEV_INFO *psDevInfo =
 512                 (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 513         enum PVRSRV_ERROR eError;
 514         u32 ui32Heap;
 515         struct DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
 516         struct SGX_DEVICE_MAP *psSGXDeviceMap;
 517
 518         if (!psDevInfo) {
 519                 PVR_DPF(PVR_DBG_ERROR, "DevDeInitSGX: Null DevInfo");
 520                 return PVRSRV_OK;
 521         }
 522         if (psDevInfo->hTimer) {
 523                 SGXOSTimerCancel(psDevInfo->hTimer);
 524                 SGXOSTimerDeInit(psDevInfo->hTimer);
 525                 psDevInfo->hTimer = NULL;
 526         }
 527
 528         MMU_BIFResetPDFree(psDevInfo);
 529
 530         DeinitDevInfo(psDevInfo);
 531
 532
 533         psDeviceMemoryHeap =
 534             (struct DEVICE_MEMORY_HEAP_INFO *)psDevInfo->pvDeviceMemoryHeap;
 535         for (ui32Heap = 0;
 536              ui32Heap < psDeviceNode->sDevMemoryInfo.ui32HeapCount;
 537              ui32Heap++) {
 538                 switch (psDeviceMemoryHeap[ui32Heap].DevMemHeapType) {
 539                 case DEVICE_MEMORY_HEAP_KERNEL:
 540                 case DEVICE_MEMORY_HEAP_SHARED:
 541                 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
 542                         {
 543                                 if (psDeviceMemoryHeap[ui32Heap].hDevMemHeap !=
 544                                     NULL)
 545                                         BM_DestroyHeap(psDeviceMemoryHeap
 546                                                        [ui32Heap].hDevMemHeap);
 547                                 break;
 548                         }
 549                 }
 550         }
 551
 552         if (!pvr_put_ctx(psDeviceNode->sDevMemoryInfo.pBMKernelContext))
 553                 pr_err("%s: kernel context still in use, can't free it",
 554                         __func__);
 555
 556         eError = PVRSRVRemovePowerDevice(
 557                                 ((struct PVRSRV_DEVICE_NODE *)pvDeviceNode)->
 558                                   sDevId.ui32DeviceIndex);
 559         if (eError != PVRSRV_OK)
 560                 return eError;
 561
 562         eError = SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
 563                                        (void **)&psSGXDeviceMap);
 564         if (eError != PVRSRV_OK) {
 565                 PVR_DPF(PVR_DBG_ERROR,
 566                          "DevDeInitSGX: Failed to get device memory map!");
 567                 return eError;
 568         }
 569
 570         if (!psSGXDeviceMap->pvRegsCpuVBase)
 571                 if (psDevInfo->pvRegsBaseKM != NULL)
 572                         OSUnMapPhysToLin(psDevInfo->pvRegsBaseKM,
 573                                          psDevInfo->ui32RegSize,
 574                                          PVRSRV_HAP_KERNEL_ONLY |
 575                                                  PVRSRV_HAP_UNCACHED,
 576                                          NULL);
 577
 578         OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 579                   sizeof(struct PVRSRV_SGXDEV_INFO), psDevInfo, NULL);
 580
 581         psDeviceNode->pvDevice = NULL;
 582
 583         if (psDeviceMemoryHeap != NULL)
 584                 OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 585                           sizeof(struct DEVICE_MEMORY_HEAP_INFO) *
 586                           psDeviceNode->sDevMemoryInfo.ui32HeapCount,
 587                           psDeviceMemoryHeap, NULL);
 588
 589         return PVRSRV_OK;
 590 }
 591
 592 #ifdef PVRSRV_USSE_EDM_STATUS_DEBUG
 593
 594 #define SGXMK_TRACE_BUFFER_SIZE         512
 595
 596 static void dump_edm(struct PVRSRV_SGXDEV_INFO *psDevInfo)
 597 {
 598         u32 *trace_buffer =
 599                 psDevInfo->psKernelEDMStatusBufferMemInfo->pvLinAddrKM;
 600         u32 last_code, write_offset;
 601         int i;
 602
 603         last_code = *trace_buffer;
 604         trace_buffer++;
 605         write_offset = *trace_buffer;
 606
 607         pr_err("Last SGX microkernel status code: 0x%x\n", last_code);
 608
 609         trace_buffer++;
 610         /* Dump the status values */
 611
 612         for (i = 0; i < SGXMK_TRACE_BUFFER_SIZE; i++) {
 613                 u32     *buf;
 614                 buf = trace_buffer + (((write_offset + i) %
 615                                         SGXMK_TRACE_BUFFER_SIZE) * 4);
 616                 pr_err("(MKT%u) %8.8X %8.8X %8.8X %8.8X\n", i,
 617                                 buf[2], buf[3], buf[1], buf[0]);
 618         }
 619 }
 620 #else
 621 static void dump_edm(struct PVRSRV_SGXDEV_INFO *psDevInfo) {}
 622 #endif
 623
 624 static void dump_process_info(struct PVRSRV_DEVICE_NODE *dev)
 625 {
 626         struct PVRSRV_SGXDEV_INFO *dev_info = dev->pvDevice;
 627         u32 page_dir = readl(dev_info->pvRegsBaseKM +
 628                                 EUR_CR_BIF_DIR_LIST_BASE0);
 629         struct BM_CONTEXT *bm_ctx;
 630         struct RESMAN_CONTEXT *res_ctx = NULL;
 631
 632         bm_ctx = bm_find_context(dev->sDevMemoryInfo.pBMContext, page_dir);
 633         if (bm_ctx)
 634                 res_ctx = pvr_get_resman_ctx(bm_ctx);
 635
 636         if (res_ctx) {
 637                 struct task_struct *tsk;
 638                 struct PVRSRV_PER_PROCESS_DATA *proc;
 639                 int pid;
 640
 641                 proc = pvr_get_proc_by_ctx(res_ctx);
 642                 pid = proc->ui32PID;
 643                 rcu_read_lock();
 644                 tsk = pid_task(find_vpid(pid), PIDTYPE_PID);
 645                 pr_err("PID = %d, process name = %s\n", pid, tsk->comm);
 646                 rcu_read_unlock();
 647         }
 648 }
 649
 650 static void dump_sgx_registers(struct PVRSRV_SGXDEV_INFO *psDevInfo)
 651 {
 652         pr_err("EVENT_STATUS =     0x%08X\n"
 653                 "EVENT_STATUS2 =    0x%08X\n"
 654                 "BIF_CTRL =         0x%08X\n"
 655                 "BIF_INT_STAT =     0x%08X\n"
 656                 "BIF_MEM_REQ_STAT = 0x%08X\n"
 657                 "BIF_FAULT  =       0x%08X\n"
 658                 "CLKGATECTL =       0x%08X\n",
 659                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_EVENT_STATUS),
 660                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_EVENT_STATUS2),
 661                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_CTRL),
 662                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_INT_STAT),
 663                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
 664                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_FAULT),
 665                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_CLKGATECTL));
 666 }
 667
 668 /* Should be called with pvr_lock held */
 669 void HWRecoveryResetSGX(struct PVRSRV_DEVICE_NODE *psDeviceNode)
 670 {
 671         enum PVRSRV_ERROR eError;
 672         struct PVRSRV_SGXDEV_INFO *psDevInfo =
 673             (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 674         struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 675                                         psDevInfo->psSGXHostCtl;
 676         u32 l;
 677         int max_retries = 10;
 678
 679         BUG_ON(!pvr_is_locked());
 680
 681         l = readl(&psSGXHostCtl->ui32InterruptClearFlags);
 682         l |= PVRSRV_USSE_EDM_INTERRUPT_HWR;
 683         writel(l, &psSGXHostCtl->ui32InterruptClearFlags);
 684
 685         pr_err("%s: SGX Hardware Recovery triggered\n", __func__);
 686
 687         dump_process_info(psDeviceNode);
 688         dump_sgx_registers(psDevInfo);
 689         dump_edm(psDevInfo);
 690
 691         PDUMPSUSPEND();
 692
 693         do {
 694                 eError = SGXInitialise(psDevInfo, IMG_TRUE);
 695                 if (eError != PVRSRV_ERROR_RETRY)
 696                         break;
 697         } while (max_retries--);
 698
 699         if (eError != PVRSRV_OK) {
 700                 pr_err("%s: recovery failed (%d). Disabling the driver",
 701                         __func__, eError);
 702                 pvr_disable();
 703
 704                 PDUMPRESUME();
 705
 706                 return;
 707         }
 708
 709         PDUMPRESUME();
 710
 711         SGXScheduleProcessQueues(psDeviceNode);
 712
 713         PVRSRVProcessQueues(IMG_TRUE);
 714 }
 715
 716 static unsigned long sgx_reset_forced;
 717
 718 static void SGXOSTimer(struct work_struct *work)
 719 {
 720         struct timer_work_data *data = container_of(work,
 721                                                     struct timer_work_data,
 722                                                     work.work);
 723         struct PVRSRV_DEVICE_NODE *psDeviceNode = data->psDeviceNode;
 724         struct PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
 725         static u32 ui32EDMTasks;
 726         static u32 ui32LockupCounter;
 727         static u32 ui32NumResets;
 728         u32 ui32CurrentEDMTasks;
 729         IMG_BOOL bLockup = IMG_FALSE;
 730         IMG_BOOL bPoweredDown;
 731
 732         pvr_lock();
 733
 734         if (!data->armed || pvr_is_disabled()) {
 735                 pvr_unlock();
 736                 return;
 737         }
 738
 739         psDevInfo->ui32TimeStamp++;
 740
 741 #if defined(NO_HARDWARE)
 742         bPoweredDown = IMG_TRUE;
 743 #else
 744         bPoweredDown = (IMG_BOOL) !SGXIsDevicePowered(psDeviceNode);
 745 #endif
 746
 747         if (bPoweredDown) {
 748                 ui32LockupCounter = 0;
 749         } else {
 750                 pvr_dev_lock();
 751                 ui32CurrentEDMTasks = OSReadHWReg(psDevInfo->pvRegsBaseKM,
 752                                                 psDevInfo->ui32EDMTaskReg0);
 753                 if (psDevInfo->ui32EDMTaskReg1 != 0)
 754                         ui32CurrentEDMTasks ^=
 755                             OSReadHWReg(psDevInfo->pvRegsBaseKM,
 756                                         psDevInfo->ui32EDMTaskReg1);
 757                 if ((ui32CurrentEDMTasks == ui32EDMTasks) &&
 758                     (psDevInfo->ui32NumResets == ui32NumResets)) {
 759                         ui32LockupCounter++;
 760                         if (ui32LockupCounter == 3) {
 761                                 ui32LockupCounter = 0;
 762                                 PVR_DPF(PVR_DBG_ERROR, "SGXOSTimer() "
 763                                         "detected SGX lockup (0x%x tasks)",
 764                                          ui32EDMTasks);
 765
 766                                 bLockup = IMG_TRUE;
 767                         }
 768                 } else {
 769                         ui32LockupCounter = 0;
 770                         ui32EDMTasks = ui32CurrentEDMTasks;
 771                         ui32NumResets = psDevInfo->ui32NumResets;
 772                 }
 773                 pvr_dev_unlock();
 774         }
 775
 776         bLockup |= cmpxchg(&sgx_reset_forced, 1, 0);
 777
 778         if (bLockup) {
 779                 struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 780                                                 psDevInfo->psSGXHostCtl;
 781                 u32 l;
 782
 783                 pvr_dev_lock();
 784                 l = readl(&psSGXHostCtl->ui32HostDetectedLockups);
 785                 l++;
 786                 writel(l, &psSGXHostCtl->ui32HostDetectedLockups);
 787
 788                 HWRecoveryResetSGX(psDeviceNode);
 789                 pvr_dev_unlock();
 790         }
 791
 792         queue_delayed_work(data->work_queue, &data->work,
 793                            msecs_to_jiffies(data->interval));
 794
 795         pvr_unlock();
 796 }
 797
 798 struct timer_work_data *
 799 SGXOSTimerInit(struct PVRSRV_DEVICE_NODE *psDeviceNode)
 800 {
 801         struct timer_work_data *data;
 802
 803         data = kzalloc(sizeof(struct timer_work_data), GFP_KERNEL);
 804         if (!data)
 805                 return NULL;
 806
 807         data->work_queue = create_workqueue("SGXOSTimer");
 808         if (!data->work_queue) {
 809                 kfree(data);
 810                 return NULL;
 811         }
 812
 813         data->interval = 150;
 814         data->psDeviceNode = psDeviceNode;
 815         INIT_DELAYED_WORK(&data->work, SGXOSTimer);
 816
 817         return data;
 818 }
 819
 820 void SGXOSTimerDeInit(struct timer_work_data *data)
 821 {
 822         data->armed = false;
 823         destroy_workqueue(data->work_queue);
 824         kfree(data);
 825 }
 826
 827 enum PVRSRV_ERROR SGXOSTimerEnable(struct timer_work_data *data)
 828 {
 829         if (!data)
 830                 return PVRSRV_ERROR_GENERIC;
 831
 832         if (queue_delayed_work(data->work_queue, &data->work,
 833                                msecs_to_jiffies(data->interval))) {
 834                 data->armed = true;
 835                 return PVRSRV_OK;
 836         }
 837
 838         return PVRSRV_ERROR_GENERIC;
 839 }
 840
 841 enum PVRSRV_ERROR SGXOSTimerCancel(struct timer_work_data *data)
 842 {
 843         if (!data)
 844                 return PVRSRV_ERROR_GENERIC;
 845
 846         data->armed = false;
 847         cancel_delayed_work(&data->work);
 848
 849         return PVRSRV_OK;
 850 }
 851
 852 int sgx_force_reset(void)
 853 {
 854         return !cmpxchg(&sgx_reset_forced, 0, 1);
 855 }
 856
 857 static IMG_BOOL SGX_ISRHandler(void *pvData)
 858 {
 859         IMG_BOOL bInterruptProcessed = IMG_FALSE;
 860
 861         {
 862                 u32 ui32EventStatus, ui32EventEnable;
 863                 u32 ui32EventClear = 0;
 864                 struct PVRSRV_DEVICE_NODE *psDeviceNode;
 865                 struct PVRSRV_SGXDEV_INFO *psDevInfo;
 866
 867                 if (pvData == NULL) {
 868                         PVR_DPF(PVR_DBG_ERROR,
 869                                  "SGX_ISRHandler: Invalid params\n");
 870                         return bInterruptProcessed;
 871                 }
 872
 873                 psDeviceNode = (struct PVRSRV_DEVICE_NODE *)pvData;
 874                 psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 875
 876                 ui32EventStatus =
 877                     OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
 878                 ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM,
 879                                                 EUR_CR_EVENT_HOST_ENABLE);
 880
 881                 gui32EventStatusServicesByISR = ui32EventStatus;
 882
 883                 ui32EventStatus &= ui32EventEnable;
 884
 885                 if (ui32EventStatus & EUR_CR_EVENT_STATUS_SW_EVENT_MASK)
 886                         ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK;
 887
 888                 if (ui32EventClear) {
 889                         bInterruptProcessed = IMG_TRUE;
 890
 891                         ui32EventClear |=
 892                             EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK;
 893
 894                         OSWriteHWReg(psDevInfo->pvRegsBaseKM,
 895                                      EUR_CR_EVENT_HOST_CLEAR, ui32EventClear);
 896                 }
 897         }
 898
 899         return bInterruptProcessed;
 900 }
 901
 902 static void SGX_MISRHandler(void *pvData)
 903 {
 904         struct PVRSRV_DEVICE_NODE *psDeviceNode =
 905                         (struct PVRSRV_DEVICE_NODE *)pvData;
 906         struct PVRSRV_SGXDEV_INFO *psDevInfo =
 907                         (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 908         struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 909                         psDevInfo->psSGXHostCtl;
 910         u32 l1, l2;
 911         int dev_idx;
 912         enum PVRSRV_ERROR err;
 913
 914         dev_idx = psDeviceNode->sDevId.ui32DeviceIndex;
 915
 916         pvr_dev_lock();
 917
 918         err = PVRSRVSetDevicePowerStateKM(dev_idx, PVRSRV_POWER_STATE_D0);
 919         BUG_ON(err != PVRSRV_OK);
 920
 921         l1 = readl(&psSGXHostCtl->ui32InterruptFlags);
 922         l2 = readl(&psSGXHostCtl->ui32InterruptClearFlags);
 923
 924         if ((l1 & PVRSRV_USSE_EDM_INTERRUPT_HWR) &&
 925             !(l2 & PVRSRV_USSE_EDM_INTERRUPT_HWR))
 926                 HWRecoveryResetSGX(psDeviceNode);
 927
 928         if (psDeviceNode->bReProcessDeviceCommandComplete)
 929                 SGXScheduleProcessQueues(psDeviceNode);
 930
 931         SGXTestActivePowerEvent(psDeviceNode);
 932
 933         pvr_dev_unlock();
 934 }
 935
 936 enum PVRSRV_ERROR SGXRegisterDevice(struct PVRSRV_DEVICE_NODE *psDeviceNode)
 937 {
 938         struct DEVICE_MEMORY_INFO *psDevMemoryInfo;
 939         struct DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
 940
 941         psDeviceNode->sDevId.eDeviceType = DEV_DEVICE_TYPE;
 942         psDeviceNode->sDevId.eDeviceClass = DEV_DEVICE_CLASS;
 943
 944         psDeviceNode->pfnInitDevice = DevInitSGXPart1;
 945         psDeviceNode->pfnDeInitDevice = DevDeInitSGX;
 946
 947         psDeviceNode->pfnInitDeviceCompatCheck = SGXDevInitCompatCheck;
 948
 949         psDeviceNode->pfnMMUInitialise = MMU_Initialise;
 950         psDeviceNode->pfnMMUFinalise = MMU_Finalise;
 951         psDeviceNode->pfnMMUInsertHeap = MMU_InsertHeap;
 952         psDeviceNode->pfnMMUCreate = MMU_Create;
 953         psDeviceNode->pfnMMUDelete = MMU_Delete;
 954         psDeviceNode->pfnMMUAlloc = MMU_Alloc;
 955         psDeviceNode->pfnMMUFree = MMU_Free;
 956         psDeviceNode->pfnMMUMapPages = MMU_MapPages;
 957         psDeviceNode->pfnMMUMapShadow = MMU_MapShadow;
 958         psDeviceNode->pfnMMUUnmapPages = MMU_UnmapPages;
 959         psDeviceNode->pfnMMUMapScatter = MMU_MapScatter;
 960         psDeviceNode->pfnMMUGetPhysPageAddr = MMU_GetPhysPageAddr;
 961         psDeviceNode->pfnMMUGetPDDevPAddr = MMU_GetPDDevPAddr;
 962
 963         psDeviceNode->pfnDeviceISR = SGX_ISRHandler;
 964         psDeviceNode->pfnDeviceMISR = SGX_MISRHandler;
 965
 966         psDeviceNode->pfnDeviceCommandComplete = SGXCommandComplete;
 967
 968         psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo;
 969
 970         psDevMemoryInfo->ui32AddressSpaceSizeLog2 =
 971             SGX_FEATURE_ADDRESS_SPACE_SIZE;
 972
 973         psDevMemoryInfo->ui32Flags = 0;
 974         psDevMemoryInfo->ui32HeapCount = SGX_MAX_HEAP_ID;
 975         psDevMemoryInfo->ui32SyncHeapID = SGX_SYNCINFO_HEAP_ID;
 976
 977         psDevMemoryInfo->ui32MappingHeapID = SGX_GENERAL_HEAP_ID;
 978
 979         if (OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
 980                        sizeof(struct DEVICE_MEMORY_HEAP_INFO) *
 981                        psDevMemoryInfo->ui32HeapCount,
 982                        (void **) &psDevMemoryInfo->psDeviceMemoryHeap,
 983                        NULL) != PVRSRV_OK) {
 984                 PVR_DPF(PVR_DBG_ERROR, "SGXRegisterDevice : "
 985                                 "Failed to alloc memory for "
 986                                 "struct DEVICE_MEMORY_HEAP_INFO");
 987                 return PVRSRV_ERROR_OUT_OF_MEMORY;
 988         }
 989         OSMemSet(psDevMemoryInfo->psDeviceMemoryHeap, 0,
 990                  sizeof(struct DEVICE_MEMORY_HEAP_INFO) *
 991                  psDevMemoryInfo->ui32HeapCount);
 992
 993         psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap;
 994
 995         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32HeapID =
 996             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_GENERAL_HEAP_ID);
 997         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].sDevVAddrBase.uiAddr =
 998             SGX_GENERAL_HEAP_BASE;
 999         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32HeapSize =
1000             SGX_GENERAL_HEAP_SIZE;
1001         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32Attribs =
1002             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1003             PVRSRV_HAP_SINGLE_PROCESS;
1004         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].pszName = "General";
1005         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].pszBSName = "General BS";
1006         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].DevMemHeapType =
1007             DEVICE_MEMORY_HEAP_PERCONTEXT;
1008
1009         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32DataPageSize =
1010             SGX_MMU_PAGE_SIZE;
1011
1012         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32HeapID =
1013             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID);
1014         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].sDevVAddrBase.uiAddr =
1015             SGX_TADATA_HEAP_BASE;
1016         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32HeapSize =
1017             SGX_TADATA_HEAP_SIZE;
1018         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32Attribs =
1019             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION
1020             | PVRSRV_HAP_MULTI_PROCESS;
1021         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].pszName = "TA Data";
1022         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].pszBSName = "TA Data BS";
1023         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].DevMemHeapType =
1024             DEVICE_MEMORY_HEAP_PERCONTEXT;
1025
1026         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32DataPageSize =
1027             SGX_MMU_PAGE_SIZE;
1028
1029         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32HeapID =
1030             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_CODE_HEAP_ID);
1031         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].sDevVAddrBase.uiAddr =
1032             SGX_KERNEL_CODE_HEAP_BASE;
1033         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32HeapSize =
1034             SGX_KERNEL_CODE_HEAP_SIZE;
1035         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32Attribs =
1036             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1037             PVRSRV_HAP_MULTI_PROCESS;
1038         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].pszName = "Kernel Code";
1039         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].pszBSName =
1040             "Kernel Code BS";
1041         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].DevMemHeapType =
1042             DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1043
1044         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32DataPageSize =
1045             SGX_MMU_PAGE_SIZE;
1046
1047         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32HeapID =
1048             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_DATA_HEAP_ID);
1049         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].sDevVAddrBase.uiAddr =
1050             SGX_KERNEL_DATA_HEAP_BASE;
1051         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32HeapSize =
1052             SGX_KERNEL_DATA_HEAP_SIZE;
1053         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32Attribs =
1054             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1055             PVRSRV_HAP_MULTI_PROCESS;
1056         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].pszName = "KernelData";
1057         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].pszBSName = "KernelData BS";
1058         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].DevMemHeapType =
1059             DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1060
1061         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32DataPageSize =
1062             SGX_MMU_PAGE_SIZE;
1063
1064         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32HeapID =
1065             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_PIXELSHADER_HEAP_ID);
1066         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].sDevVAddrBase.uiAddr =
1067             SGX_PIXELSHADER_HEAP_BASE;
1068         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32HeapSize =
1069             SGX_PIXELSHADER_HEAP_SIZE;
1070         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32Attribs =
1071             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1072             PVRSRV_HAP_SINGLE_PROCESS;
1073         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].pszName = "PixelShaderUSSE";
1074         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].pszBSName =
1075             "PixelShaderUSSE BS";
1076         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].DevMemHeapType =
1077             DEVICE_MEMORY_HEAP_PERCONTEXT;
1078
1079         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32DataPageSize =
1080             SGX_MMU_PAGE_SIZE;
1081
1082         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32HeapID =
1083             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_VERTEXSHADER_HEAP_ID);
1084         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].sDevVAddrBase.uiAddr =
1085             SGX_VERTEXSHADER_HEAP_BASE;
1086         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32HeapSize =
1087             SGX_VERTEXSHADER_HEAP_SIZE;
1088         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32Attribs =
1089             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1090             PVRSRV_HAP_SINGLE_PROCESS;
1091         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].pszName =
1092             "VertexShaderUSSE";
1093         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].pszBSName =
1094             "VertexShaderUSSE BS";
1095         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].DevMemHeapType =
1096             DEVICE_MEMORY_HEAP_PERCONTEXT;
1097
1098         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32DataPageSize =
1099             SGX_MMU_PAGE_SIZE;
1100
1101         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32HeapID =
1102             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_PDSPIXEL_CODEDATA_HEAP_ID);
1103         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].sDevVAddrBase.uiAddr =
1104             SGX_PDSPIXEL_CODEDATA_HEAP_BASE;
1105         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32HeapSize =
1106             SGX_PDSPIXEL_CODEDATA_HEAP_SIZE;
1107         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32Attribs =
1108             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1109             PVRSRV_HAP_SINGLE_PROCESS;
1110         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].pszName =
1111             "PDSPixelCodeData";
1112         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].pszBSName =
1113             "PDSPixelCodeData BS";
1114         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].DevMemHeapType =
1115             DEVICE_MEMORY_HEAP_PERCONTEXT;
1116
1117         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32DataPageSize =
1118             SGX_MMU_PAGE_SIZE;
1119
1120         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32HeapID =
1121             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_PDSVERTEX_CODEDATA_HEAP_ID);
1122         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].sDevVAddrBase.
1123             uiAddr = SGX_PDSVERTEX_CODEDATA_HEAP_BASE;
1124         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32HeapSize =
1125             SGX_PDSVERTEX_CODEDATA_HEAP_SIZE;
1126         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32Attribs =
1127             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1128             PVRSRV_HAP_SINGLE_PROCESS;
1129         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].pszName =
1130             "PDSVertexCodeData";
1131         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].pszBSName =
1132             "PDSVertexCodeData BS";
1133         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].DevMemHeapType =
1134             DEVICE_MEMORY_HEAP_PERCONTEXT;
1135
1136         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32DataPageSize =
1137             SGX_MMU_PAGE_SIZE;
1138
1139         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32HeapID =
1140             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_SYNCINFO_HEAP_ID);
1141         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].sDevVAddrBase.uiAddr =
1142             SGX_SYNCINFO_HEAP_BASE;
1143         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32HeapSize =
1144             SGX_SYNCINFO_HEAP_SIZE;
1145
1146         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32Attribs =
1147             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1148             PVRSRV_HAP_MULTI_PROCESS;
1149         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].pszName = "CacheCoherent";
1150         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].pszBSName = "CacheCoherent BS";
1151
1152         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].DevMemHeapType =
1153             DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1154
1155         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32DataPageSize =
1156             SGX_MMU_PAGE_SIZE;
1157
1158         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32HeapID =
1159             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_3DPARAMETERS_HEAP_ID);
1160         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].sDevVAddrBase.uiAddr =
1161             SGX_3DPARAMETERS_HEAP_BASE;
1162         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32HeapSize =
1163             SGX_3DPARAMETERS_HEAP_SIZE;
1164         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].pszName = "3DParameters";
1165         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].pszBSName =
1166             "3DParameters BS";
1167         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32Attribs =
1168             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1169             PVRSRV_HAP_SINGLE_PROCESS;
1170         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].DevMemHeapType =
1171             DEVICE_MEMORY_HEAP_PERCONTEXT;
1172
1173         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32DataPageSize =
1174             SGX_MMU_PAGE_SIZE;
1175
1176         return PVRSRV_OK;
1177 }
1178
1179 enum PVRSRV_ERROR SGXGetClientInfoKM(void *hDevCookie,
1180                                          struct SGX_CLIENT_INFO *psClientInfo)
1181 {
1182         struct PVRSRV_SGXDEV_INFO *psDevInfo =
1183             (struct PVRSRV_SGXDEV_INFO *)
1184                         ((struct PVRSRV_DEVICE_NODE *)hDevCookie)->pvDevice;
1185
1186         psDevInfo->ui32ClientRefCount++;
1187 #ifdef PDUMP
1188         if (psDevInfo->ui32ClientRefCount == 1)
1189                 psDevInfo->psKernelCCBInfo->ui32CCBDumpWOff = 0;
1190 #endif
1191         psClientInfo->ui32ProcessID = OSGetCurrentProcessIDKM();
1192
1193         OSMemCopy(&psClientInfo->asDevData, &psDevInfo->asSGXDevData,
1194                   sizeof(psClientInfo->asDevData));
1195
1196         return PVRSRV_OK;
1197 }
1198
1199 enum PVRSRV_ERROR SGXDevInitCompatCheck(struct PVRSRV_DEVICE_NODE *psDeviceNode)
1200 {
1201         struct PVRSRV_SGXDEV_INFO *psDevInfo;
1202         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo;
1203         enum PVRSRV_ERROR eError;
1204 #if !defined(NO_HARDWARE)
1205         u32 ui32BuildOptions, ui32BuildOptionsMismatch;
1206         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1207 #endif
1208
1209         if (psDeviceNode->sDevId.eDeviceType != PVRSRV_DEVICE_TYPE_SGX) {
1210                 PVR_DPF(PVR_DBG_ERROR,
1211                          "SGXDevInitCompatCheck: Device not of type SGX");
1212                 eError = PVRSRV_ERROR_INVALID_PARAMS;
1213                 goto exit;
1214         }
1215         psDevInfo = psDeviceNode->pvDevice;
1216         psMemInfo = psDevInfo->psKernelSGXMiscMemInfo;
1217
1218 #if !defined(NO_HARDWARE)
1219
1220         eError = SGXGetBuildInfoKM(psDevInfo, psDeviceNode);
1221         if (eError != PVRSRV_OK) {
1222                 PVR_DPF(PVR_DBG_ERROR, "SGXDevInitCompatCheck: "
1223                                 "Unable to validate device DDK version");
1224                 goto exit;
1225         }
1226         psSGXFeatures =
1227             &((struct PVRSRV_SGX_MISCINFO_INFO *)(psMemInfo->pvLinAddrKM))->
1228                                                             sSGXFeatures;
1229         if ((psSGXFeatures->ui32DDKVersion !=
1230              ((PVRVERSION_MAJ << 16) | (PVRVERSION_MIN << 8) |
1231               PVRVERSION_BRANCH)) ||
1232              (psSGXFeatures->ui32DDKBuild != PVRVERSION_BUILD)) {
1233                 PVR_DPF(PVR_DBG_ERROR, "SGXDevInitCompatCheck: "
1234                         "Incompatible driver DDK revision (%ld)"
1235                         "/device DDK revision (%ld).",
1236                          PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild);
1237                 eError = PVRSRV_ERROR_DDK_VERSION_MISMATCH;
1238                 goto exit;
1239         } else {
1240                 PVR_DPF(PVR_DBG_WARNING, "(Success) SGXInit: "
1241                                 "driver DDK (%ld) and device DDK (%ld) match",
1242                          PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild);
1243         }
1244
1245         ui32BuildOptions = psSGXFeatures->ui32BuildOptions;
1246         if (ui32BuildOptions != (SGX_BUILD_OPTIONS)) {
1247                 ui32BuildOptionsMismatch =
1248                     ui32BuildOptions ^ (SGX_BUILD_OPTIONS);
1249                 if (((SGX_BUILD_OPTIONS) & ui32BuildOptionsMismatch) != 0)
1250                         PVR_DPF(PVR_DBG_ERROR, "SGXInit: "
1251                                 "Mismatch in driver and microkernel build "
1252                                 "options; extra options present in driver: "
1253                                 "(0x%lx)",
1254                                  (SGX_BUILD_OPTIONS) &
1255                                  ui32BuildOptionsMismatch);
1256
1257                 if ((ui32BuildOptions & ui32BuildOptionsMismatch) != 0)
1258                         PVR_DPF(PVR_DBG_ERROR, "SGXInit: "
1259                                 "Mismatch in driver and microkernel build "
1260                                 "options; extra options present in "
1261                                 "microkernel: (0x%lx)",
1262                                  ui32BuildOptions & ui32BuildOptionsMismatch);
1263                 eError = PVRSRV_ERROR_BUILD_MISMATCH;
1264                 goto exit;
1265         } else {
1266                 PVR_DPF(PVR_DBG_WARNING, "(Success) SGXInit: "
1267                                 "Driver and microkernel build options match.");
1268         }
1269
1270 #endif
1271         eError = PVRSRV_OK;
1272 exit:
1273         return eError;
1274 }
1275
1276 static
1277 enum PVRSRV_ERROR SGXGetBuildInfoKM(struct PVRSRV_SGXDEV_INFO *psDevInfo,
1278                                     struct PVRSRV_DEVICE_NODE *psDeviceNode)
1279 {
1280         enum PVRSRV_ERROR eError;
1281         struct SGXMKIF_COMMAND sCommandData;
1282         struct PVRSRV_SGX_MISCINFO_INFO *psSGXMiscInfoInt;
1283         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1284
1285         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo =
1286             psDevInfo->psKernelSGXMiscMemInfo;
1287
1288         if (!psMemInfo->pvLinAddrKM) {
1289                 PVR_DPF(PVR_DBG_ERROR, "SGXGetMiscInfoKM: Invalid address.");
1290                 return PVRSRV_ERROR_INVALID_PARAMS;
1291         }
1292         psSGXMiscInfoInt = psMemInfo->pvLinAddrKM;
1293         psSGXMiscInfoInt->ui32MiscInfoFlags &= ~PVRSRV_USSE_MISCINFO_READY;
1294         psSGXFeatures = &psSGXMiscInfoInt->sSGXFeatures;
1295
1296         OSMemSet(psMemInfo->pvLinAddrKM, 0,
1297                  sizeof(struct PVRSRV_SGX_MISCINFO_INFO));
1298
1299         sCommandData.ui32Data[1] = psMemInfo->sDevVAddr.uiAddr;
1300
1301         OSMemSet(psSGXFeatures, 0, sizeof(*psSGXFeatures));
1302
1303         mb();
1304
1305         eError = SGXScheduleCCBCommandKM(psDeviceNode,
1306                                          SGXMKIF_COMMAND_REQUEST_SGXMISCINFO,
1307                                          &sCommandData, KERNEL_ID, 0);
1308
1309         if (eError != PVRSRV_OK) {
1310                 PVR_DPF(PVR_DBG_ERROR,
1311                          "SGXGetMiscInfoKM: SGXScheduleCCBCommandKM failed.");
1312                 return eError;
1313         }
1314
1315 #if !defined(NO_HARDWARE)
1316         {
1317                 IMG_BOOL bTimeout = IMG_TRUE;
1318
1319                 LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US) {
1320                         if ((psSGXMiscInfoInt->
1321                              ui32MiscInfoFlags & PVRSRV_USSE_MISCINFO_READY) !=
1322                             0) {
1323                                 bTimeout = IMG_FALSE;
1324                                 break;
1325                         }
1326                 }
1327                 END_LOOP_UNTIL_TIMEOUT();
1328
1329                 if (bTimeout)
1330                         return PVRSRV_ERROR_TIMEOUT;
1331         }
1332 #endif
1333
1334         return PVRSRV_OK;
1335 }
1336
1337 enum PVRSRV_ERROR SGXGetMiscInfoKM(struct PVRSRV_SGXDEV_INFO *psDevInfo,
1338                                        struct SGX_MISC_INFO *psMiscInfo,
1339                                        struct PVRSRV_DEVICE_NODE *psDeviceNode)
1340 {
1341         switch (psMiscInfo->eRequest) {
1342         case SGX_MISC_INFO_REQUEST_CLOCKSPEED:
1343                 {
1344                         psMiscInfo->uData.ui32SGXClockSpeed =
1345                             psDevInfo->ui32CoreClockSpeed;
1346                         return PVRSRV_OK;
1347                 }
1348
1349         case SGX_MISC_INFO_REQUEST_SGXREV:
1350                 {
1351                         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1352                         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo =
1353                             psDevInfo->psKernelSGXMiscMemInfo;
1354
1355                         SGXGetBuildInfoKM(psDevInfo, psDeviceNode);
1356                         psSGXFeatures =
1357                             &((struct PVRSRV_SGX_MISCINFO_INFO *)(psMemInfo->
1358                                                   pvLinAddrKM))->sSGXFeatures;
1359
1360                         psMiscInfo->uData.sSGXFeatures = *psSGXFeatures;
1361
1362                         PVR_DPF(PVR_DBG_MESSAGE, "SGXGetMiscInfoKM: "
1363                                         "Core 0x%lx, sw ID 0x%lx, "
1364                                         "sw Rev 0x%lx\n",
1365                                  psSGXFeatures->ui32CoreRev,
1366                                  psSGXFeatures->ui32CoreIdSW,
1367                                  psSGXFeatures->ui32CoreRevSW);
1368                         PVR_DPF(PVR_DBG_MESSAGE, "SGXGetMiscInfoKM: "
1369                                         "DDK version 0x%lx, DDK build 0x%lx\n",
1370                                  psSGXFeatures->ui32DDKVersion,
1371                                  psSGXFeatures->ui32DDKBuild);
1372
1373                         return PVRSRV_OK;
1374                 }
1375
1376         case SGX_MISC_INFO_REQUEST_DRIVER_SGXREV:
1377                 {
1378                         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo =
1379                             psDevInfo->psKernelSGXMiscMemInfo;
1380                         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1381
1382                         psSGXFeatures = &((struct PVRSRV_SGX_MISCINFO_INFO *)(
1383                                         psMemInfo->pvLinAddrKM))->sSGXFeatures;
1384
1385                         OSMemSet(psMemInfo->pvLinAddrKM, 0,
1386                                  sizeof(struct PVRSRV_SGX_MISCINFO_INFO));
1387
1388                         psSGXFeatures->ui32DDKVersion =
1389                             (PVRVERSION_MAJ << 16) |
1390                             (PVRVERSION_MIN << 8) | PVRVERSION_BRANCH;
1391                         psSGXFeatures->ui32DDKBuild = PVRVERSION_BUILD;
1392
1393                         psMiscInfo->uData.sSGXFeatures = *psSGXFeatures;
1394                         return PVRSRV_OK;
1395                 }
1396
1397         case SGX_MISC_INFO_REQUEST_SET_HWPERF_STATUS:
1398                 {
1399                         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1400                             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1401                         unsigned ui32MatchingFlags;
1402
1403                         if ((psMiscInfo->uData.ui32NewHWPerfStatus &
1404                              ~(PVRSRV_SGX_HWPERF_GRAPHICS_ON |
1405                                PVRSRV_SGX_HWPERF_MK_EXECUTION_ON)) != 0) {
1406                                 return PVRSRV_ERROR_INVALID_PARAMS;
1407                         }
1408
1409                         pvr_dev_lock();
1410                         ui32MatchingFlags = readl(&psDevInfo->
1411                                                  psSGXHostCtl->ui32HWPerfFlags);
1412                         ui32MatchingFlags &=
1413                                 psMiscInfo->uData.ui32NewHWPerfStatus;
1414                         if ((ui32MatchingFlags & PVRSRV_SGX_HWPERF_GRAPHICS_ON)
1415                             == 0UL) {
1416                                 psHWPerfCB->ui32OrdinalGRAPHICS = 0xffffffff;
1417                         }
1418                         if ((ui32MatchingFlags &
1419                              PVRSRV_SGX_HWPERF_MK_EXECUTION_ON) == 0UL) {
1420                                 psHWPerfCB->ui32OrdinalMK_EXECUTION =
1421                                     0xffffffffUL;
1422                         }
1423
1424
1425                         writel(psMiscInfo->uData.ui32NewHWPerfStatus,
1426                                 &psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1427                         pvr_dev_unlock();
1428 #if defined(PDUMP)
1429                         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
1430                                               "SGX ukernel HWPerf status %u\n",
1431                                               readl(&psDevInfo->psSGXHostCtl->
1432                                                               ui32HWPerfFlags));
1433                         PDUMPMEM(NULL, psDevInfo->psKernelSGXHostCtlMemInfo,
1434                                  offsetof(struct SGXMKIF_HOST_CTL,
1435                                           ui32HWPerfFlags),
1436                                  sizeof(psDevInfo->psSGXHostCtl->
1437                                         ui32HWPerfFlags),
1438                                  PDUMP_FLAGS_CONTINUOUS,
1439                                  MAKEUNIQUETAG(psDevInfo->
1440                                                psKernelSGXHostCtlMemInfo));
1441 #endif
1442
1443                         return PVRSRV_OK;
1444                 }
1445         case SGX_MISC_INFO_REQUEST_HWPERF_CB_ON:
1446                 {
1447
1448                         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1449                             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1450                         u32 l;
1451
1452                         psHWPerfCB->ui32OrdinalGRAPHICS = 0xffffffffUL;
1453
1454                         pvr_dev_lock();;
1455                         l = readl(&psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1456                         l |= PVRSRV_SGX_HWPERF_GRAPHICS_ON;
1457                         writel(l, &psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1458                         pvr_dev_unlock();
1459
1460                         return PVRSRV_OK;
1461                 }
1462         case SGX_MISC_INFO_REQUEST_HWPERF_CB_OFF:
1463                 {
1464                         pvr_dev_lock();
1465                         writel(0, &psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1466                         pvr_dev_unlock();
1467
1468                         return PVRSRV_OK;
1469                 }
1470         case SGX_MISC_INFO_REQUEST_HWPERF_RETRIEVE_CB:
1471                 {
1472                         struct SGX_MISC_INFO_HWPERF_RETRIEVE_CB *psRetrieve =
1473                             &psMiscInfo->uData.sRetrieveCB;
1474                         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1475                             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1476                         unsigned i;
1477
1478                         for (i = 0;
1479                              psHWPerfCB->ui32Woff != psHWPerfCB->ui32Roff
1480                              && i < psRetrieve->ui32ArraySize; i++) {
1481                                 struct SGXMKIF_HWPERF_CB_ENTRY *psData =
1482                                     &psHWPerfCB->psHWPerfCBData[psHWPerfCB->
1483                                                                 ui32Roff];
1484
1485                                 psRetrieve->psHWPerfData[i].ui32FrameNo =
1486                                     psData->ui32FrameNo;
1487                                 psRetrieve->psHWPerfData[i].ui32Type =
1488                                     (psData->ui32Type &
1489                                      PVRSRV_SGX_HWPERF_TYPE_OP_MASK);
1490                                 psRetrieve->psHWPerfData[i].ui32StartTime =
1491                                     psData->ui32Time;
1492                                 psRetrieve->psHWPerfData[i].ui32StartTimeWraps =
1493                                     psData->ui32TimeWraps;
1494                                 psRetrieve->psHWPerfData[i].ui32EndTime =
1495                                     psData->ui32Time;
1496                                 psRetrieve->psHWPerfData[i].ui32EndTimeWraps =
1497                                     psData->ui32TimeWraps;
1498                                 psRetrieve->psHWPerfData[i].ui32ClockSpeed =
1499                                     psDevInfo->ui32CoreClockSpeed;
1500                                 psRetrieve->psHWPerfData[i].ui32TimeMax =
1501                                     psDevInfo->ui32uKernelTimerClock;
1502                                 psHWPerfCB->ui32Roff =
1503                                     (psHWPerfCB->ui32Roff + 1) &
1504                                     (SGXMKIF_HWPERF_CB_SIZE - 1);
1505                         }
1506                         psRetrieve->ui32DataCount = i;
1507                         psRetrieve->ui32Time = OSClockus();
1508                         return PVRSRV_OK;
1509                 }
1510         default:
1511                 {
1512                         return PVRSRV_ERROR_INVALID_PARAMS;
1513                 }
1514         }
1515 }
1516
1517 enum PVRSRV_ERROR SGXReadDiffCountersKM(void *hDevHandle, u32 ui32Reg,
1518                                    u32 *pui32Old, IMG_BOOL bNew, u32 ui32New,
1519                                    u32 ui32NewReset, u32 ui32CountersReg,
1520                                    u32 *pui32Time, IMG_BOOL *pbActive,
1521                                    struct PVRSRV_SGXDEV_DIFF_INFO *psDiffs)
1522 {
1523         struct SYS_DATA *psSysData;
1524         struct PVRSRV_POWER_DEV *psPowerDevice;
1525         IMG_BOOL bPowered = IMG_FALSE;
1526         struct PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
1527         struct PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1528
1529         if (bNew)
1530                 psDevInfo->ui32HWGroupRequested = ui32New;
1531         psDevInfo->ui32HWReset |= ui32NewReset;
1532
1533         if (SysAcquireData(&psSysData) != PVRSRV_OK)
1534                 return PVRSRV_ERROR_GENERIC;
1535
1536         psPowerDevice = psSysData->psPowerDeviceList;
1537         while (psPowerDevice) {
1538                 if (psPowerDevice->ui32DeviceIndex ==
1539                     psDeviceNode->sDevId.ui32DeviceIndex) {
1540                         bPowered =
1541                             (IMG_BOOL)(psPowerDevice->eCurrentPowerState ==
1542                                         PVRSRV_POWER_STATE_D0);
1543                         break;
1544                 }
1545
1546                 psPowerDevice = psPowerDevice->psNext;
1547         }
1548
1549         *pbActive = bPowered;
1550
1551         pvr_dev_lock();
1552
1553         {
1554                 struct PVRSRV_SGXDEV_DIFF_INFO sNew,
1555                                                *psPrev = &psDevInfo->sDiffInfo;
1556                 u32 i;
1557
1558                 sNew.ui32Time[0] = OSClockus();
1559                 *pui32Time = sNew.ui32Time[0];
1560                 if (sNew.ui32Time[0] != psPrev->ui32Time[0] && bPowered) {
1561
1562                         *pui32Old =
1563                             OSReadHWReg(psDevInfo->pvRegsBaseKM, ui32Reg);
1564
1565                         for (i = 0; i < PVRSRV_SGX_DIFF_NUM_COUNTERS; ++i) {
1566                                 sNew.aui32Counters[i] =
1567                                     OSReadHWReg(psDevInfo->pvRegsBaseKM,
1568                                                 ui32CountersReg + (i * 4));
1569                         }
1570
1571                         if (psDevInfo->ui32HWGroupRequested != *pui32Old) {
1572                                 if (psDevInfo->ui32HWReset != 0) {
1573                                         OSWriteHWReg(psDevInfo->pvRegsBaseKM,
1574                                                      ui32Reg,
1575                                                      psDevInfo->
1576                                                      ui32HWGroupRequested |
1577                                                      psDevInfo->ui32HWReset);
1578                                         psDevInfo->ui32HWReset = 0;
1579                                 }
1580                                 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Reg,
1581                                              psDevInfo->ui32HWGroupRequested);
1582                         }
1583
1584                         sNew.ui32Marker[0] = psDevInfo->ui32KickTACounter;
1585                         sNew.ui32Marker[1] = psDevInfo->ui32KickTARenderCounter;
1586
1587                         sNew.ui32Time[1] = readl(
1588                                 &psDevInfo->psSGXHostCtl->ui32TimeWraps);
1589
1590                         for (i = 0; i < PVRSRV_SGX_DIFF_NUM_COUNTERS; ++i) {
1591                                 psDiffs->aui32Counters[i] =
1592                                     sNew.aui32Counters[i] -
1593                                     psPrev->aui32Counters[i];
1594                         }
1595
1596                         psDiffs->ui32Marker[0] =
1597                             sNew.ui32Marker[0] - psPrev->ui32Marker[0];
1598                         psDiffs->ui32Marker[1] =
1599                             sNew.ui32Marker[1] - psPrev->ui32Marker[1];
1600
1601                         psDiffs->ui32Time[0] =
1602                             sNew.ui32Time[0] - psPrev->ui32Time[0];
1603                         psDiffs->ui32Time[1] =
1604                             sNew.ui32Time[1] - psPrev->ui32Time[1];
1605
1606                         *psPrev = sNew;
1607                 } else {
1608                         for (i = 0; i < PVRSRV_SGX_DIFF_NUM_COUNTERS; ++i)
1609                                 psDiffs->aui32Counters[i] = 0;
1610
1611                         psDiffs->ui32Marker[0] = 0;
1612                         psDiffs->ui32Marker[1] = 0;
1613
1614                         psDiffs->ui32Time[0] = 0;
1615                         psDiffs->ui32Time[1] = 0;
1616                 }
1617         }
1618
1619         SGXTestActivePowerEvent(psDeviceNode);
1620
1621         pvr_dev_unlock();
1622
1623         return PVRSRV_OK;
1624 }
1625
1626 enum PVRSRV_ERROR SGXReadHWPerfCBKM(void *hDevHandle, u32 ui32ArraySize,
1627                         struct PVRSRV_SGX_HWPERF_CB_ENTRY *psClientHWPerfEntry,
1628                         u32 *pui32DataCount, u32 *pui32ClockSpeed,
1629                         u32 *pui32HostTimeStamp)
1630 {
1631         enum PVRSRV_ERROR eError = PVRSRV_OK;
1632         struct PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
1633         struct PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1634         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1635             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1636         unsigned i;
1637
1638         for (i = 0;
1639              psHWPerfCB->ui32Woff != psHWPerfCB->ui32Roff && i < ui32ArraySize;
1640              i++) {
1641                 struct SGXMKIF_HWPERF_CB_ENTRY *psMKPerfEntry =
1642                     &psHWPerfCB->psHWPerfCBData[psHWPerfCB->ui32Roff];
1643
1644                 psClientHWPerfEntry[i].ui32FrameNo = psMKPerfEntry->ui32FrameNo;
1645                 psClientHWPerfEntry[i].ui32Type = psMKPerfEntry->ui32Type;
1646                 psClientHWPerfEntry[i].ui32Ordinal = psMKPerfEntry->ui32Ordinal;
1647                 psClientHWPerfEntry[i].ui32Clocksx16 =
1648                     SGXConvertTimeStamp(psDevInfo, psMKPerfEntry->ui32TimeWraps,
1649                                         psMKPerfEntry->ui32Time);
1650                 OSMemCopy(&psClientHWPerfEntry[i].ui32Counters[0],
1651                           &psMKPerfEntry->ui32Counters[0],
1652                           sizeof(psMKPerfEntry->ui32Counters));
1653
1654                 psHWPerfCB->ui32Roff =
1655                     (psHWPerfCB->ui32Roff + 1) & (SGXMKIF_HWPERF_CB_SIZE - 1);
1656         }
1657
1658         *pui32DataCount = i;
1659         *pui32ClockSpeed = psDevInfo->ui32CoreClockSpeed;
1660         *pui32HostTimeStamp = OSClockus();
1661
1662         return eError;
1663 }