pvr/sgxinit.c

   1 /**********************************************************************
   2  *
   3  * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful but, except
  10  * as otherwise stated in writing, without any warranty; without even the
  11  * implied warranty of merchantability or fitness for a particular purpose.
  12  * See the GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * Imagination Technologies Ltd. <gpl-support@imgtec.com>
  23  * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
  24  *
  25  ******************************************************************************/
  26
  27 #include <stddef.h>
  28
  29 #include <linux/workqueue.h>
  30 #include <linux/io.h>
  31 #include <linux/slab.h>
  32 #include <linux/sched.h>
  33
  34 #include "sgxdefs.h"
  35 #include "sgxmmu.h"
  36 #include "services_headers.h"
  37 #include "buffer_manager.h"
  38 #include "sgxapi_km.h"
  39 #include "sgxinfo.h"
  40 #include "sgxinfokm.h"
  41 #include "sgxconfig.h"
  42 #include "sysconfig.h"
  43 #include "pvr_bridge_km.h"
  44 #include "sgx_bridge_km.h"
  45 #include "resman.h"
  46
  47 #include "pdump_km.h"
  48 #include "ra.h"
  49 #include "mmu.h"
  50 #include "handle.h"
  51 #include "perproc.h"
  52
  53 #include "sgxutils.h"
  54 #include "pvrversion.h"
  55 #include "sgx_options.h"
  56
  57 static IMG_BOOL SGX_ISRHandler(void *pvData);
  58
  59 static u32 gui32EventStatusServicesByISR;
  60
  61 static enum PVRSRV_ERROR SGXGetBuildInfoKM(struct PVRSRV_SGXDEV_INFO *psDevInfo,
  62                                     struct PVRSRV_DEVICE_NODE *psDeviceNode);
  63
  64 static void SGXCommandComplete(struct PVRSRV_DEVICE_NODE *psDeviceNode)
  65 {
  66         BUG_ON(in_irq());
  67
  68         SGXScheduleProcessQueuesKM(psDeviceNode);
  69 }
  70
  71 static u32 DeinitDevInfo(struct PVRSRV_SGXDEV_INFO *psDevInfo)
  72 {
  73         if (psDevInfo->psKernelCCBInfo != NULL)
  74                 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
  75                           sizeof(struct PVRSRV_SGX_CCB_INFO),
  76                           psDevInfo->psKernelCCBInfo, NULL);
  77
  78         return PVRSRV_OK;
  79 }
  80
  81 static enum PVRSRV_ERROR InitDevInfo(struct PVRSRV_PER_PROCESS_DATA *psPerProc,
  82                                 struct PVRSRV_DEVICE_NODE *psDeviceNode,
  83                                 struct SGX_BRIDGE_INIT_INFO *psInitInfo)
  84 {
  85         struct PVRSRV_SGXDEV_INFO *psDevInfo =
  86             (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
  87         enum PVRSRV_ERROR eError;
  88
  89         struct PVRSRV_SGX_CCB_INFO *psKernelCCBInfo = NULL;
  90
  91         PVR_UNREFERENCED_PARAMETER(psPerProc);
  92         psDevInfo->sScripts = psInitInfo->sScripts;
  93
  94         psDevInfo->psKernelCCBMemInfo =
  95             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelCCBMemInfo;
  96         psDevInfo->psKernelCCB =
  97             (struct PVRSRV_SGX_KERNEL_CCB *)psDevInfo->psKernelCCBMemInfo->
  98                                                     pvLinAddrKM;
  99
 100         psDevInfo->psKernelCCBCtlMemInfo =
 101             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelCCBCtlMemInfo;
 102         psDevInfo->psKernelCCBCtl =
 103             (struct PVRSRV_SGX_CCB_CTL *)psDevInfo->psKernelCCBCtlMemInfo->
 104                                                     pvLinAddrKM;
 105
 106         psDevInfo->psKernelCCBEventKickerMemInfo =
 107             (struct PVRSRV_KERNEL_MEM_INFO *)
 108                             psInitInfo->hKernelCCBEventKickerMemInfo;
 109         psDevInfo->pui32KernelCCBEventKicker =
 110             (u32 *)psDevInfo->psKernelCCBEventKickerMemInfo->pvLinAddrKM;
 111
 112         psDevInfo->psKernelSGXHostCtlMemInfo =
 113             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->
 114                                                     hKernelSGXHostCtlMemInfo;
 115         psDevInfo->psSGXHostCtl = (struct SGXMKIF_HOST_CTL __force __iomem *)
 116                 psDevInfo->psKernelSGXHostCtlMemInfo->pvLinAddrKM;
 117
 118         psDevInfo->psKernelSGXTA3DCtlMemInfo =
 119             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->
 120                                                     hKernelSGXTA3DCtlMemInfo;
 121
 122         psDevInfo->psKernelSGXMiscMemInfo =
 123             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXMiscMemInfo;
 124
 125         psDevInfo->psKernelHWPerfCBMemInfo =
 126             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelHWPerfCBMemInfo;
 127 #ifdef PVRSRV_USSE_EDM_STATUS_DEBUG
 128         psDevInfo->psKernelEDMStatusBufferMemInfo =
 129             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->
 130                                                   hKernelEDMStatusBufferMemInfo;
 131 #endif
 132
 133         eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
 134                             sizeof(struct PVRSRV_SGX_CCB_INFO),
 135                             (void **)&psKernelCCBInfo, NULL);
 136         if (eError != PVRSRV_OK) {
 137                 PVR_DPF(PVR_DBG_ERROR, "InitDevInfo: Failed to alloc memory");
 138                 goto failed_allockernelccb;
 139         }
 140
 141         OSMemSet(psKernelCCBInfo, 0, sizeof(struct PVRSRV_SGX_CCB_INFO));
 142         psKernelCCBInfo->psCCBMemInfo = psDevInfo->psKernelCCBMemInfo;
 143         psKernelCCBInfo->psCCBCtlMemInfo = psDevInfo->psKernelCCBCtlMemInfo;
 144         psKernelCCBInfo->psCommands = psDevInfo->psKernelCCB->asCommands;
 145         psKernelCCBInfo->pui32WriteOffset =
 146                                 &psDevInfo->psKernelCCBCtl->ui32WriteOffset;
 147         psKernelCCBInfo->pui32ReadOffset =
 148                                 &psDevInfo->psKernelCCBCtl->ui32ReadOffset;
 149         psDevInfo->psKernelCCBInfo = psKernelCCBInfo;
 150
 151         psDevInfo->ui32HostKickAddress = psInitInfo->ui32HostKickAddress;
 152
 153         psDevInfo->ui32GetMiscInfoAddress = psInitInfo->ui32GetMiscInfoAddress;
 154
 155         psDevInfo->bForcePTOff = IMG_FALSE;
 156
 157         psDevInfo->ui32CacheControl = psInitInfo->ui32CacheControl;
 158
 159         psDevInfo->ui32EDMTaskReg0 = psInitInfo->ui32EDMTaskReg0;
 160         psDevInfo->ui32EDMTaskReg1 = psInitInfo->ui32EDMTaskReg1;
 161         psDevInfo->ui32ClkGateStatusReg = psInitInfo->ui32ClkGateStatusReg;
 162         psDevInfo->ui32ClkGateStatusMask = psInitInfo->ui32ClkGateStatusMask;
 163
 164         OSMemCopy(&psDevInfo->asSGXDevData, &psInitInfo->asInitDevData,
 165                   sizeof(psDevInfo->asSGXDevData));
 166
 167         return PVRSRV_OK;
 168
 169 failed_allockernelccb:
 170         DeinitDevInfo(psDevInfo);
 171
 172         return eError;
 173 }
 174
 175 static enum PVRSRV_ERROR SGXRunScript(struct PVRSRV_SGXDEV_INFO *psDevInfo,
 176                                  union SGX_INIT_COMMAND *psScript,
 177                                  u32 ui32NumInitCommands)
 178 {
 179         u32 ui32PC;
 180         union SGX_INIT_COMMAND *psComm;
 181
 182         for (ui32PC = 0, psComm = psScript;
 183              ui32PC < ui32NumInitCommands; ui32PC++, psComm++) {
 184                 switch (psComm->eOp) {
 185                 case SGX_INIT_OP_WRITE_HW_REG:
 186                         {
 187                                 OSWriteHWReg(psDevInfo->pvRegsBaseKM,
 188                                              psComm->sWriteHWReg.ui32Offset,
 189                                              psComm->sWriteHWReg.ui32Value);
 190                                 PDUMPREG(psComm->sWriteHWReg.ui32Offset,
 191                                          psComm->sWriteHWReg.ui32Value);
 192                                 break;
 193                         }
 194 #if defined(PDUMP)
 195                 case SGX_INIT_OP_PDUMP_HW_REG:
 196                         {
 197                                 PDUMPREG(psComm->sPDumpHWReg.ui32Offset,
 198                                          psComm->sPDumpHWReg.ui32Value);
 199                                 break;
 200                         }
 201 #endif
 202                 case SGX_INIT_OP_HALT:
 203                         {
 204                                 return PVRSRV_OK;
 205                         }
 206                 case SGX_INIT_OP_ILLEGAL:
 207
 208                 default:
 209                         {
 210                                 PVR_DPF(PVR_DBG_ERROR,
 211                                      "SGXRunScript: PC %d: Illegal command: %d",
 212                                       ui32PC, psComm->eOp);
 213                                 return PVRSRV_ERROR_GENERIC;
 214                         }
 215                 }
 216
 217         }
 218
 219         return PVRSRV_ERROR_GENERIC;
 220 }
 221
 222 enum PVRSRV_ERROR SGXInitialise(struct PVRSRV_SGXDEV_INFO *psDevInfo,
 223                                   IMG_BOOL bHardwareRecovery)
 224 {
 225         enum PVRSRV_ERROR eError;
 226
 227         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 228                               "SGX initialisation script part 1\n");
 229         eError =
 230             SGXRunScript(psDevInfo, psDevInfo->sScripts.asInitCommandsPart1,
 231                          SGX_MAX_INIT_COMMANDS);
 232         if (eError != PVRSRV_OK) {
 233                 PVR_DPF(PVR_DBG_ERROR,
 234                          "SGXInitialise: SGXRunScript (part 1) failed (%d)",
 235                          eError);
 236                 return PVRSRV_ERROR_GENERIC;
 237         }
 238         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 239                               "End of SGX initialisation script part 1\n");
 240
 241         SGXReset(psDevInfo, PDUMP_FLAGS_CONTINUOUS);
 242
 243
 244
 245         *psDevInfo->pui32KernelCCBEventKicker = 0;
 246 #if defined(PDUMP)
 247         PDUMPMEM(NULL, psDevInfo->psKernelCCBEventKickerMemInfo, 0,
 248                  sizeof(*psDevInfo->pui32KernelCCBEventKicker),
 249                  PDUMP_FLAGS_CONTINUOUS,
 250                  MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
 251 #endif
 252
 253         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 254                               "SGX initialisation script part 2\n");
 255         eError =
 256             SGXRunScript(psDevInfo, psDevInfo->sScripts.asInitCommandsPart2,
 257                          SGX_MAX_INIT_COMMANDS);
 258         if (eError != PVRSRV_OK) {
 259                 PVR_DPF(PVR_DBG_ERROR,
 260                          "SGXInitialise: SGXRunScript (part 2) failed (%d)",
 261                          eError);
 262                 return PVRSRV_ERROR_GENERIC;
 263         }
 264         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 265                               "End of SGX initialisation script part 2\n");
 266
 267         SGXStartTimer(psDevInfo, (IMG_BOOL)!bHardwareRecovery);
 268
 269         if (bHardwareRecovery) {
 270                 struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 271                     psDevInfo->psSGXHostCtl;
 272
 273                 if (PollForValueKM(&psSGXHostCtl->ui32InterruptClearFlags, 0,
 274                      PVRSRV_USSE_EDM_INTERRUPT_HWR,
 275                      MAX_HW_TIME_US / WAIT_TRY_COUNT, 1000) != PVRSRV_OK) {
 276                         PVR_DPF(PVR_DBG_ERROR, "SGXInitialise: "
 277                                         "Wait for uKernel HW Recovery failed");
 278                         PVR_DBG_BREAK;
 279                         return PVRSRV_ERROR_RETRY;
 280                 }
 281         }
 282
 283         PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset ==
 284                    psDevInfo->psKernelCCBCtl->ui32WriteOffset);
 285
 286         return PVRSRV_OK;
 287 }
 288
 289 enum PVRSRV_ERROR SGXDeinitialise(void *hDevCookie)
 290 {
 291         struct PVRSRV_SGXDEV_INFO *psDevInfo = (struct PVRSRV_SGXDEV_INFO *)
 292                                                                    hDevCookie;
 293         enum PVRSRV_ERROR eError;
 294
 295         if (psDevInfo->pvRegsBaseKM == NULL)
 296                 return PVRSRV_OK;
 297
 298         eError = SGXRunScript(psDevInfo, psDevInfo->sScripts.asDeinitCommands,
 299                          SGX_MAX_DEINIT_COMMANDS);
 300         if (eError != PVRSRV_OK) {
 301                 PVR_DPF(PVR_DBG_ERROR,
 302                          "SGXDeinitialise: SGXRunScript failed (%d)", eError);
 303                 return PVRSRV_ERROR_GENERIC;
 304         }
 305
 306         return PVRSRV_OK;
 307 }
 308
 309 static enum PVRSRV_ERROR DevInitSGXPart1(void *pvDeviceNode)
 310 {
 311         struct PVRSRV_SGXDEV_INFO *psDevInfo;
 312         void *hKernelDevMemContext;
 313         struct IMG_DEV_PHYADDR sPDDevPAddr;
 314         u32 i;
 315         struct PVRSRV_DEVICE_NODE *psDeviceNode = (struct PVRSRV_DEVICE_NODE *)
 316                                                                    pvDeviceNode;
 317         struct DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap =
 318             psDeviceNode->sDevMemoryInfo.psDeviceMemoryHeap;
 319         enum PVRSRV_ERROR eError;
 320
 321         PDUMPCOMMENT("SGX Initialisation Part 1");
 322
 323         PDUMPCOMMENT("SGX Core Version Information: %s",
 324                      SGX_CORE_FRIENDLY_NAME);
 325         PDUMPCOMMENT("SGX Core Revision Information: multi rev support");
 326
 327         if (OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 328                        sizeof(struct PVRSRV_SGXDEV_INFO),
 329                        (void **)&psDevInfo, NULL) != PVRSRV_OK) {
 330                 PVR_DPF(PVR_DBG_ERROR,
 331                         "DevInitSGXPart1 : Failed to alloc memory for DevInfo");
 332                 return PVRSRV_ERROR_OUT_OF_MEMORY;
 333         }
 334         OSMemSet(psDevInfo, 0, sizeof(struct PVRSRV_SGXDEV_INFO));
 335
 336         psDevInfo->eDeviceType = DEV_DEVICE_TYPE;
 337         psDevInfo->eDeviceClass = DEV_DEVICE_CLASS;
 338
 339         psDeviceNode->pvDevice = (void *) psDevInfo;
 340
 341         psDevInfo->pvDeviceMemoryHeap = (void *) psDeviceMemoryHeap;
 342
 343         hKernelDevMemContext = BM_CreateContext(psDeviceNode, &sPDDevPAddr,
 344                                                 NULL, NULL);
 345
 346         psDevInfo->sKernelPDDevPAddr = sPDDevPAddr;
 347
 348         for (i = 0; i < psDeviceNode->sDevMemoryInfo.ui32HeapCount; i++) {
 349                 void *hDevMemHeap;
 350
 351                 switch (psDeviceMemoryHeap[i].DevMemHeapType) {
 352                 case DEVICE_MEMORY_HEAP_KERNEL:
 353                 case DEVICE_MEMORY_HEAP_SHARED:
 354                 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
 355                         {
 356                                 hDevMemHeap =
 357                                     BM_CreateHeap(hKernelDevMemContext,
 358                                                   &psDeviceMemoryHeap[i]);
 359
 360                                 psDeviceMemoryHeap[i].hDevMemHeap = hDevMemHeap;
 361                                 break;
 362                         }
 363                 }
 364         }
 365
 366         eError = MMU_BIFResetPDAlloc(psDevInfo);
 367         if (eError != PVRSRV_OK) {
 368                 PVR_DPF(PVR_DBG_ERROR,
 369                          "DevInitSGX : Failed to alloc memory for BIF reset");
 370                 return PVRSRV_ERROR_GENERIC;
 371         }
 372
 373         return PVRSRV_OK;
 374 }
 375
 376 enum PVRSRV_ERROR SGXGetInfoForSrvinitKM(void *hDevHandle,
 377                                 struct SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo)
 378 {
 379         struct PVRSRV_DEVICE_NODE *psDeviceNode;
 380         struct PVRSRV_SGXDEV_INFO *psDevInfo;
 381         enum PVRSRV_ERROR eError;
 382
 383         PDUMPCOMMENT("SGXGetInfoForSrvinit");
 384
 385         psDeviceNode = (struct PVRSRV_DEVICE_NODE *)hDevHandle;
 386         psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 387
 388         psInitInfo->sPDDevPAddr = psDevInfo->sKernelPDDevPAddr;
 389
 390         eError =
 391             PVRSRVGetDeviceMemHeapsKM(hDevHandle, &psInitInfo->asHeapInfo[0]);
 392         if (eError != PVRSRV_OK) {
 393                 PVR_DPF(PVR_DBG_ERROR, "SGXGetInfoForSrvinit: "
 394                                 "PVRSRVGetDeviceMemHeapsKM failed (%d)",
 395                          eError);
 396                 return PVRSRV_ERROR_GENERIC;
 397         }
 398
 399         return eError;
 400 }
 401
 402 enum PVRSRV_ERROR DevInitSGXPart2KM(struct PVRSRV_PER_PROCESS_DATA *psPerProc,
 403                                    void *hDevHandle,
 404                                    struct SGX_BRIDGE_INIT_INFO *psInitInfo)
 405 {
 406         struct PVRSRV_DEVICE_NODE *psDeviceNode;
 407         struct PVRSRV_SGXDEV_INFO *psDevInfo;
 408         enum PVRSRV_ERROR eError;
 409         struct SGX_DEVICE_MAP *psSGXDeviceMap;
 410         enum PVR_POWER_STATE eDefaultPowerState;
 411         u32 l;
 412
 413         PDUMPCOMMENT("SGX Initialisation Part 2");
 414
 415         psDeviceNode = (struct PVRSRV_DEVICE_NODE *)hDevHandle;
 416         psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 417
 418         eError = InitDevInfo(psPerProc, psDeviceNode, psInitInfo);
 419         if (eError != PVRSRV_OK) {
 420                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM: "
 421                                         "Failed to load EDM program");
 422                 goto failed_init_dev_info;
 423         }
 424
 425
 426         eError = SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
 427                                        (void **) &psSGXDeviceMap);
 428         if (eError != PVRSRV_OK) {
 429                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM: "
 430                                         "Failed to get device memory map!");
 431                 return PVRSRV_ERROR_INIT_FAILURE;
 432         }
 433
 434         if (psSGXDeviceMap->pvRegsCpuVBase) {
 435                 psDevInfo->pvRegsBaseKM = psSGXDeviceMap->pvRegsCpuVBase;
 436         } else {
 437                 psDevInfo->pvRegsBaseKM =
 438                     OSMapPhysToLin(psSGXDeviceMap->sRegsCpuPBase,
 439                                    psSGXDeviceMap->ui32RegsSize,
 440                                    PVRSRV_HAP_KERNEL_ONLY | PVRSRV_HAP_UNCACHED,
 441                                    NULL);
 442                 if (!psDevInfo->pvRegsBaseKM) {
 443                         PVR_DPF(PVR_DBG_ERROR,
 444                                  "DevInitSGXPart2KM: Failed to map in regs\n");
 445                         return PVRSRV_ERROR_BAD_MAPPING;
 446                 }
 447         }
 448         psDevInfo->ui32RegSize = psSGXDeviceMap->ui32RegsSize;
 449         psDevInfo->sRegsPhysBase = psSGXDeviceMap->sRegsSysPBase;
 450
 451         psDeviceNode->pvISRData = psDeviceNode;
 452
 453         PVR_ASSERT(psDeviceNode->pfnDeviceISR == SGX_ISRHandler);
 454
 455         l = readl(&psDevInfo->psSGXHostCtl->ui32PowerStatus);
 456         l |= PVRSRV_USSE_EDM_POWMAN_NO_WORK;
 457         writel(l, &psDevInfo->psSGXHostCtl->ui32PowerStatus);
 458         eDefaultPowerState = PVRSRV_POWER_STATE_D3;
 459
 460         eError = PVRSRVRegisterPowerDevice(psDeviceNode->sDevId.ui32DeviceIndex,
 461                                            SGXPrePowerStateExt,
 462                                            SGXPostPowerStateExt,
 463                                            SGXPreClockSpeedChange,
 464                                            SGXPostClockSpeedChange,
 465                                            (void *) psDeviceNode,
 466                                            PVRSRV_POWER_STATE_D3,
 467                                            eDefaultPowerState);
 468         if (eError != PVRSRV_OK) {
 469                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM: "
 470                                 "failed to register device with power manager");
 471                 return eError;
 472         }
 473
 474         OSMemSet(psDevInfo->psKernelCCB, 0,
 475                  sizeof(struct PVRSRV_SGX_KERNEL_CCB));
 476         OSMemSet(psDevInfo->psKernelCCBCtl, 0,
 477                  sizeof(struct PVRSRV_SGX_CCB_CTL));
 478         OSMemSet(psDevInfo->pui32KernelCCBEventKicker, 0,
 479                  sizeof(*psDevInfo->pui32KernelCCBEventKicker));
 480         PDUMPCOMMENT("Initialise Kernel CCB");
 481         PDUMPMEM(NULL, psDevInfo->psKernelCCBMemInfo, 0,
 482                  sizeof(struct PVRSRV_SGX_KERNEL_CCB), PDUMP_FLAGS_CONTINUOUS,
 483                  MAKEUNIQUETAG(psDevInfo->psKernelCCBMemInfo));
 484         PDUMPCOMMENT("Initialise Kernel CCB Control");
 485         PDUMPMEM(NULL, psDevInfo->psKernelCCBCtlMemInfo, 0,
 486                  sizeof(struct PVRSRV_SGX_CCB_CTL), PDUMP_FLAGS_CONTINUOUS,
 487                  MAKEUNIQUETAG(psDevInfo->psKernelCCBCtlMemInfo));
 488         PDUMPCOMMENT("Initialise Kernel CCB Event Kicker");
 489         PDUMPMEM(NULL, psDevInfo->psKernelCCBEventKickerMemInfo, 0,
 490                  sizeof(*psDevInfo->pui32KernelCCBEventKicker),
 491                  PDUMP_FLAGS_CONTINUOUS,
 492                  MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
 493
 494         psDevInfo->hTimer = SGXOSTimerInit(psDeviceNode);
 495         if (!psDevInfo->hTimer)
 496                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM : "
 497                         "Failed to initialize HW recovery timer");
 498
 499         return PVRSRV_OK;
 500
 501 failed_init_dev_info:
 502         return eError;
 503 }
 504
 505 static enum PVRSRV_ERROR DevDeInitSGX(void *pvDeviceNode)
 506 {
 507         struct PVRSRV_DEVICE_NODE *psDeviceNode =
 508                 (struct PVRSRV_DEVICE_NODE *)pvDeviceNode;
 509         struct PVRSRV_SGXDEV_INFO *psDevInfo =
 510                 (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 511         enum PVRSRV_ERROR eError;
 512         u32 ui32Heap;
 513         struct DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
 514         struct SGX_DEVICE_MAP *psSGXDeviceMap;
 515
 516         if (!psDevInfo) {
 517                 PVR_DPF(PVR_DBG_ERROR, "DevDeInitSGX: Null DevInfo");
 518                 return PVRSRV_OK;
 519         }
 520         if (psDevInfo->hTimer) {
 521                 SGXOSTimerCancel(psDevInfo->hTimer);
 522                 SGXOSTimerDeInit(psDevInfo->hTimer);
 523                 psDevInfo->hTimer = NULL;
 524         }
 525
 526         MMU_BIFResetPDFree(psDevInfo);
 527
 528         DeinitDevInfo(psDevInfo);
 529
 530
 531         psDeviceMemoryHeap =
 532             (struct DEVICE_MEMORY_HEAP_INFO *)psDevInfo->pvDeviceMemoryHeap;
 533         for (ui32Heap = 0;
 534              ui32Heap < psDeviceNode->sDevMemoryInfo.ui32HeapCount;
 535              ui32Heap++) {
 536                 switch (psDeviceMemoryHeap[ui32Heap].DevMemHeapType) {
 537                 case DEVICE_MEMORY_HEAP_KERNEL:
 538                 case DEVICE_MEMORY_HEAP_SHARED:
 539                 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
 540                         {
 541                                 if (psDeviceMemoryHeap[ui32Heap].hDevMemHeap !=
 542                                     NULL)
 543                                         BM_DestroyHeap(psDeviceMemoryHeap
 544                                                        [ui32Heap].hDevMemHeap);
 545                                 break;
 546                         }
 547                 }
 548         }
 549
 550         if (!pvr_put_ctx(psDeviceNode->sDevMemoryInfo.pBMKernelContext))
 551                 pr_err("%s: kernel context still in use, can't free it",
 552                         __func__);
 553
 554         eError = PVRSRVRemovePowerDevice(
 555                                 ((struct PVRSRV_DEVICE_NODE *)pvDeviceNode)->
 556                                   sDevId.ui32DeviceIndex);
 557         if (eError != PVRSRV_OK)
 558                 return eError;
 559
 560         eError = SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
 561                                        (void **)&psSGXDeviceMap);
 562         if (eError != PVRSRV_OK) {
 563                 PVR_DPF(PVR_DBG_ERROR,
 564                          "DevDeInitSGX: Failed to get device memory map!");
 565                 return eError;
 566         }
 567
 568         if (!psSGXDeviceMap->pvRegsCpuVBase)
 569                 if (psDevInfo->pvRegsBaseKM != NULL)
 570                         OSUnMapPhysToLin(psDevInfo->pvRegsBaseKM,
 571                                          psDevInfo->ui32RegSize,
 572                                          PVRSRV_HAP_KERNEL_ONLY |
 573                                                  PVRSRV_HAP_UNCACHED,
 574                                          NULL);
 575
 576         OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 577                   sizeof(struct PVRSRV_SGXDEV_INFO), psDevInfo, NULL);
 578
 579         psDeviceNode->pvDevice = NULL;
 580
 581         if (psDeviceMemoryHeap != NULL)
 582                 OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 583                           sizeof(struct DEVICE_MEMORY_HEAP_INFO) *
 584                           psDeviceNode->sDevMemoryInfo.ui32HeapCount,
 585                           psDeviceMemoryHeap, NULL);
 586
 587         return PVRSRV_OK;
 588 }
 589
 590 #ifdef PVRSRV_USSE_EDM_STATUS_DEBUG
 591
 592 #define SGXMK_TRACE_BUFFER_SIZE         512
 593
 594 static void dump_edm(struct PVRSRV_SGXDEV_INFO *psDevInfo)
 595 {
 596         u32 *trace_buffer =
 597                 psDevInfo->psKernelEDMStatusBufferMemInfo->pvLinAddrKM;
 598         u32 last_code, write_offset;
 599         int i;
 600
 601         last_code = *trace_buffer;
 602         trace_buffer++;
 603         write_offset = *trace_buffer;
 604
 605         pr_err("Last SGX microkernel status code: 0x%x\n", last_code);
 606
 607         trace_buffer++;
 608         /* Dump the status values */
 609
 610         for (i = 0; i < SGXMK_TRACE_BUFFER_SIZE; i++) {
 611                 u32     *buf;
 612                 buf = trace_buffer + (((write_offset + i) %
 613                                         SGXMK_TRACE_BUFFER_SIZE) * 4);
 614                 pr_err("(MKT%u) %8.8X %8.8X %8.8X %8.8X\n", i,
 615                                 buf[2], buf[3], buf[1], buf[0]);
 616         }
 617 }
 618 #else
 619 static void dump_edm(struct PVRSRV_SGXDEV_INFO *psDevInfo) {}
 620 #endif
 621
 622 static void dump_process_info(struct PVRSRV_DEVICE_NODE *dev)
 623 {
 624         struct PVRSRV_SGXDEV_INFO *dev_info = dev->pvDevice;
 625         u32 page_dir = readl(dev_info->pvRegsBaseKM +
 626                                 EUR_CR_BIF_DIR_LIST_BASE0);
 627         struct BM_CONTEXT *bm_ctx;
 628         struct RESMAN_CONTEXT *res_ctx = NULL;
 629
 630         bm_ctx = bm_find_context(dev->sDevMemoryInfo.pBMContext, page_dir);
 631         if (bm_ctx)
 632                 res_ctx = pvr_get_resman_ctx(bm_ctx);
 633
 634         if (res_ctx) {
 635                 struct task_struct *tsk;
 636                 struct PVRSRV_PER_PROCESS_DATA *proc;
 637                 int pid;
 638
 639                 proc = pvr_get_proc_by_ctx(res_ctx);
 640                 pid = proc->ui32PID;
 641                 rcu_read_lock();
 642                 tsk = pid_task(find_vpid(pid), PIDTYPE_PID);
 643                 pr_err("PID = %d, process name = %s\n", pid, tsk->comm);
 644                 rcu_read_unlock();
 645         }
 646 }
 647
 648 static void dump_sgx_registers(struct PVRSRV_SGXDEV_INFO *psDevInfo)
 649 {
 650         pr_err("EVENT_STATUS =     0x%08X\n"
 651                 "EVENT_STATUS2 =    0x%08X\n"
 652                 "BIF_CTRL =         0x%08X\n"
 653                 "BIF_INT_STAT =     0x%08X\n"
 654                 "BIF_MEM_REQ_STAT = 0x%08X\n"
 655                 "BIF_FAULT  =       0x%08X\n"
 656                 "CLKGATECTL =       0x%08X\n",
 657                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_EVENT_STATUS),
 658                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_EVENT_STATUS2),
 659                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_CTRL),
 660                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_INT_STAT),
 661                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
 662                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_FAULT),
 663                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_CLKGATECTL));
 664 }
 665
 666 /* Should be called with pvr_lock held */
 667 void HWRecoveryResetSGX(struct PVRSRV_DEVICE_NODE *psDeviceNode)
 668 {
 669         enum PVRSRV_ERROR eError;
 670         struct PVRSRV_SGXDEV_INFO *psDevInfo =
 671             (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 672         struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 673                                         psDevInfo->psSGXHostCtl;
 674         u32 l;
 675         int max_retries = 10;
 676
 677         BUG_ON(!pvr_is_locked());
 678
 679         l = readl(&psSGXHostCtl->ui32InterruptClearFlags);
 680         l |= PVRSRV_USSE_EDM_INTERRUPT_HWR;
 681         writel(l, &psSGXHostCtl->ui32InterruptClearFlags);
 682
 683         pr_err("%s: SGX Hardware Recovery triggered\n", __func__);
 684
 685         dump_process_info(psDeviceNode);
 686         dump_sgx_registers(psDevInfo);
 687         dump_edm(psDevInfo);
 688
 689         PDUMPSUSPEND();
 690
 691         do {
 692                 eError = SGXInitialise(psDevInfo, IMG_TRUE);
 693                 if (eError != PVRSRV_ERROR_RETRY)
 694                         break;
 695         } while (max_retries--);
 696
 697         if (eError != PVRSRV_OK) {
 698                 pr_err("%s: recovery failed (%d). Disabling the driver",
 699                         __func__, eError);
 700                 pvr_disable();
 701
 702                 PDUMPRESUME();
 703
 704                 return;
 705         }
 706
 707         PDUMPRESUME();
 708
 709         SGXScheduleProcessQueuesKM(psDeviceNode);
 710
 711         PVRSRVProcessQueues(IMG_TRUE);
 712 }
 713
 714 static unsigned long sgx_reset_forced;
 715
 716 static void SGXOSTimer(struct work_struct *work)
 717 {
 718         struct timer_work_data *data = container_of(work,
 719                                                     struct timer_work_data,
 720                                                     work.work);
 721         struct PVRSRV_DEVICE_NODE *psDeviceNode = data->psDeviceNode;
 722         struct PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
 723         static u32 ui32EDMTasks;
 724         static u32 ui32LockupCounter;
 725         static u32 ui32NumResets;
 726         u32 ui32CurrentEDMTasks;
 727         IMG_BOOL bLockup = IMG_FALSE;
 728         IMG_BOOL bPoweredDown;
 729
 730         pvr_lock();
 731
 732         if (!data->armed || pvr_is_disabled()) {
 733                 pvr_unlock();
 734                 return;
 735         }
 736
 737         psDevInfo->ui32TimeStamp++;
 738
 739 #if defined(NO_HARDWARE)
 740         bPoweredDown = IMG_TRUE;
 741 #else
 742         bPoweredDown = (IMG_BOOL) !SGXIsDevicePowered(psDeviceNode);
 743 #endif
 744
 745         if (bPoweredDown) {
 746                 ui32LockupCounter = 0;
 747         } else {
 748                 ui32CurrentEDMTasks = OSReadHWReg(psDevInfo->pvRegsBaseKM,
 749                                                 psDevInfo->ui32EDMTaskReg0);
 750                 if (psDevInfo->ui32EDMTaskReg1 != 0)
 751                         ui32CurrentEDMTasks ^=
 752                             OSReadHWReg(psDevInfo->pvRegsBaseKM,
 753                                         psDevInfo->ui32EDMTaskReg1);
 754                 if ((ui32CurrentEDMTasks == ui32EDMTasks) &&
 755                     (psDevInfo->ui32NumResets == ui32NumResets)) {
 756                         ui32LockupCounter++;
 757                         if (ui32LockupCounter == 3) {
 758                                 ui32LockupCounter = 0;
 759                                 PVR_DPF(PVR_DBG_ERROR, "SGXOSTimer() "
 760                                         "detected SGX lockup (0x%x tasks)",
 761                                          ui32EDMTasks);
 762
 763                                 bLockup = IMG_TRUE;
 764                         }
 765                 } else {
 766                         ui32LockupCounter = 0;
 767                         ui32EDMTasks = ui32CurrentEDMTasks;
 768                         ui32NumResets = psDevInfo->ui32NumResets;
 769                 }
 770         }
 771
 772         bLockup |= cmpxchg(&sgx_reset_forced, 1, 0);
 773
 774         if (bLockup) {
 775                 struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 776                                                 psDevInfo->psSGXHostCtl;
 777                 u32 l;
 778
 779                 l = readl(&psSGXHostCtl->ui32HostDetectedLockups);
 780                 l++;
 781                 writel(l, &psSGXHostCtl->ui32HostDetectedLockups);
 782
 783                 HWRecoveryResetSGX(psDeviceNode);
 784         }
 785
 786         queue_delayed_work(data->work_queue, &data->work,
 787                            msecs_to_jiffies(data->interval));
 788
 789         pvr_unlock();
 790 }
 791
 792 struct timer_work_data *
 793 SGXOSTimerInit(struct PVRSRV_DEVICE_NODE *psDeviceNode)
 794 {
 795         struct timer_work_data *data;
 796
 797         data = kzalloc(sizeof(struct timer_work_data), GFP_KERNEL);
 798         if (!data)
 799                 return NULL;
 800
 801         data->work_queue = create_workqueue("SGXOSTimer");
 802         if (!data->work_queue) {
 803                 kfree(data);
 804                 return NULL;
 805         }
 806
 807         data->interval = 150;
 808         data->psDeviceNode = psDeviceNode;
 809         INIT_DELAYED_WORK(&data->work, SGXOSTimer);
 810
 811         return data;
 812 }
 813
 814 void SGXOSTimerDeInit(struct timer_work_data *data)
 815 {
 816         data->armed = false;
 817         destroy_workqueue(data->work_queue);
 818         kfree(data);
 819 }
 820
 821 enum PVRSRV_ERROR SGXOSTimerEnable(struct timer_work_data *data)
 822 {
 823         if (!data)
 824                 return PVRSRV_ERROR_GENERIC;
 825
 826         if (queue_delayed_work(data->work_queue, &data->work,
 827                                msecs_to_jiffies(data->interval))) {
 828                 data->armed = true;
 829                 return PVRSRV_OK;
 830         }
 831
 832         return PVRSRV_ERROR_GENERIC;
 833 }
 834
 835 enum PVRSRV_ERROR SGXOSTimerCancel(struct timer_work_data *data)
 836 {
 837         if (!data)
 838                 return PVRSRV_ERROR_GENERIC;
 839
 840         data->armed = false;
 841         cancel_delayed_work(&data->work);
 842
 843         return PVRSRV_OK;
 844 }
 845
 846 int sgx_force_reset(void)
 847 {
 848         return !cmpxchg(&sgx_reset_forced, 0, 1);
 849 }
 850
 851 static IMG_BOOL SGX_ISRHandler(void *pvData)
 852 {
 853         IMG_BOOL bInterruptProcessed = IMG_FALSE;
 854
 855         {
 856                 u32 ui32EventStatus, ui32EventEnable;
 857                 u32 ui32EventClear = 0;
 858                 struct PVRSRV_DEVICE_NODE *psDeviceNode;
 859                 struct PVRSRV_SGXDEV_INFO *psDevInfo;
 860
 861                 if (pvData == NULL) {
 862                         PVR_DPF(PVR_DBG_ERROR,
 863                                  "SGX_ISRHandler: Invalid params\n");
 864                         return bInterruptProcessed;
 865                 }
 866
 867                 psDeviceNode = (struct PVRSRV_DEVICE_NODE *)pvData;
 868                 psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 869
 870                 ui32EventStatus =
 871                     OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
 872                 ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM,
 873                                                 EUR_CR_EVENT_HOST_ENABLE);
 874
 875                 gui32EventStatusServicesByISR = ui32EventStatus;
 876
 877                 ui32EventStatus &= ui32EventEnable;
 878
 879                 if (ui32EventStatus & EUR_CR_EVENT_STATUS_SW_EVENT_MASK)
 880                         ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK;
 881
 882                 if (ui32EventClear) {
 883                         bInterruptProcessed = IMG_TRUE;
 884
 885                         ui32EventClear |=
 886                             EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK;
 887
 888                         OSWriteHWReg(psDevInfo->pvRegsBaseKM,
 889                                      EUR_CR_EVENT_HOST_CLEAR, ui32EventClear);
 890                 }
 891         }
 892
 893         return bInterruptProcessed;
 894 }
 895
 896 static void SGX_MISRHandler(void *pvData)
 897 {
 898         struct PVRSRV_DEVICE_NODE *psDeviceNode =
 899                         (struct PVRSRV_DEVICE_NODE *)pvData;
 900         struct PVRSRV_SGXDEV_INFO *psDevInfo =
 901                         (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 902         struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 903                         psDevInfo->psSGXHostCtl;
 904         u32 l1, l2;
 905         int dev_idx;
 906         enum PVRSRV_ERROR err;
 907
 908         dev_idx = psDeviceNode->sDevId.ui32DeviceIndex;
 909         err = PVRSRVSetDevicePowerStateKM(dev_idx, PVRSRV_POWER_STATE_D0);
 910         BUG_ON(err != PVRSRV_OK);
 911
 912         l1 = readl(&psSGXHostCtl->ui32InterruptFlags);
 913         l2 = readl(&psSGXHostCtl->ui32InterruptClearFlags);
 914         if ((l1 & PVRSRV_USSE_EDM_INTERRUPT_HWR) &&
 915             !(l2 & PVRSRV_USSE_EDM_INTERRUPT_HWR))
 916                 HWRecoveryResetSGX(psDeviceNode);
 917
 918         if (psDeviceNode->bReProcessDeviceCommandComplete)
 919                 SGXScheduleProcessQueuesKM(psDeviceNode);
 920
 921         SGXTestActivePowerEvent(psDeviceNode);
 922 }
 923
 924 enum PVRSRV_ERROR SGXRegisterDevice(struct PVRSRV_DEVICE_NODE *psDeviceNode)
 925 {
 926         struct DEVICE_MEMORY_INFO *psDevMemoryInfo;
 927         struct DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
 928
 929         psDeviceNode->sDevId.eDeviceType = DEV_DEVICE_TYPE;
 930         psDeviceNode->sDevId.eDeviceClass = DEV_DEVICE_CLASS;
 931
 932         psDeviceNode->pfnInitDevice = DevInitSGXPart1;
 933         psDeviceNode->pfnDeInitDevice = DevDeInitSGX;
 934
 935         psDeviceNode->pfnInitDeviceCompatCheck = SGXDevInitCompatCheck;
 936
 937         psDeviceNode->pfnMMUInitialise = MMU_Initialise;
 938         psDeviceNode->pfnMMUFinalise = MMU_Finalise;
 939         psDeviceNode->pfnMMUInsertHeap = MMU_InsertHeap;
 940         psDeviceNode->pfnMMUCreate = MMU_Create;
 941         psDeviceNode->pfnMMUDelete = MMU_Delete;
 942         psDeviceNode->pfnMMUAlloc = MMU_Alloc;
 943         psDeviceNode->pfnMMUFree = MMU_Free;
 944         psDeviceNode->pfnMMUMapPages = MMU_MapPages;
 945         psDeviceNode->pfnMMUMapShadow = MMU_MapShadow;
 946         psDeviceNode->pfnMMUUnmapPages = MMU_UnmapPages;
 947         psDeviceNode->pfnMMUMapScatter = MMU_MapScatter;
 948         psDeviceNode->pfnMMUGetPhysPageAddr = MMU_GetPhysPageAddr;
 949         psDeviceNode->pfnMMUGetPDDevPAddr = MMU_GetPDDevPAddr;
 950
 951         psDeviceNode->pfnDeviceISR = SGX_ISRHandler;
 952         psDeviceNode->pfnDeviceMISR = SGX_MISRHandler;
 953
 954         psDeviceNode->pfnDeviceCommandComplete = SGXCommandComplete;
 955
 956         psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo;
 957
 958         psDevMemoryInfo->ui32AddressSpaceSizeLog2 =
 959             SGX_FEATURE_ADDRESS_SPACE_SIZE;
 960
 961         psDevMemoryInfo->ui32Flags = 0;
 962         psDevMemoryInfo->ui32HeapCount = SGX_MAX_HEAP_ID;
 963         psDevMemoryInfo->ui32SyncHeapID = SGX_SYNCINFO_HEAP_ID;
 964
 965         psDevMemoryInfo->ui32MappingHeapID = SGX_GENERAL_HEAP_ID;
 966
 967         if (OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
 968                        sizeof(struct DEVICE_MEMORY_HEAP_INFO) *
 969                        psDevMemoryInfo->ui32HeapCount,
 970                        (void **) &psDevMemoryInfo->psDeviceMemoryHeap,
 971                        NULL) != PVRSRV_OK) {
 972                 PVR_DPF(PVR_DBG_ERROR, "SGXRegisterDevice : "
 973                                 "Failed to alloc memory for "
 974                                 "struct DEVICE_MEMORY_HEAP_INFO");
 975                 return PVRSRV_ERROR_OUT_OF_MEMORY;
 976         }
 977         OSMemSet(psDevMemoryInfo->psDeviceMemoryHeap, 0,
 978                  sizeof(struct DEVICE_MEMORY_HEAP_INFO) *
 979                  psDevMemoryInfo->ui32HeapCount);
 980
 981         psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap;
 982
 983         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32HeapID =
 984             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_GENERAL_HEAP_ID);
 985         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].sDevVAddrBase.uiAddr =
 986             SGX_GENERAL_HEAP_BASE;
 987         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32HeapSize =
 988             SGX_GENERAL_HEAP_SIZE;
 989         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32Attribs =
 990             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
 991             PVRSRV_HAP_SINGLE_PROCESS;
 992         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].pszName = "General";
 993         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].pszBSName = "General BS";
 994         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].DevMemHeapType =
 995             DEVICE_MEMORY_HEAP_PERCONTEXT;
 996
 997         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32DataPageSize =
 998             SGX_MMU_PAGE_SIZE;
 999
1000         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32HeapID =
1001             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID);
1002         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].sDevVAddrBase.uiAddr =
1003             SGX_TADATA_HEAP_BASE;
1004         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32HeapSize =
1005             SGX_TADATA_HEAP_SIZE;
1006         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32Attribs =
1007             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION
1008             | PVRSRV_HAP_MULTI_PROCESS;
1009         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].pszName = "TA Data";
1010         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].pszBSName = "TA Data BS";
1011         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].DevMemHeapType =
1012             DEVICE_MEMORY_HEAP_PERCONTEXT;
1013
1014         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32DataPageSize =
1015             SGX_MMU_PAGE_SIZE;
1016
1017         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32HeapID =
1018             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_CODE_HEAP_ID);
1019         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].sDevVAddrBase.uiAddr =
1020             SGX_KERNEL_CODE_HEAP_BASE;
1021         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32HeapSize =
1022             SGX_KERNEL_CODE_HEAP_SIZE;
1023         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32Attribs =
1024             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1025             PVRSRV_HAP_MULTI_PROCESS;
1026         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].pszName = "Kernel Code";
1027         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].pszBSName =
1028             "Kernel Code BS";
1029         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].DevMemHeapType =
1030             DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1031
1032         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32DataPageSize =
1033             SGX_MMU_PAGE_SIZE;
1034
1035         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32HeapID =
1036             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_DATA_HEAP_ID);
1037         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].sDevVAddrBase.uiAddr =
1038             SGX_KERNEL_DATA_HEAP_BASE;
1039         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32HeapSize =
1040             SGX_KERNEL_DATA_HEAP_SIZE;
1041         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32Attribs =
1042             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1043             PVRSRV_HAP_MULTI_PROCESS;
1044         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].pszName = "KernelData";
1045         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].pszBSName = "KernelData BS";
1046         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].DevMemHeapType =
1047             DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1048
1049         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32DataPageSize =
1050             SGX_MMU_PAGE_SIZE;
1051
1052         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32HeapID =
1053             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_PIXELSHADER_HEAP_ID);
1054         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].sDevVAddrBase.uiAddr =
1055             SGX_PIXELSHADER_HEAP_BASE;
1056         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32HeapSize =
1057             SGX_PIXELSHADER_HEAP_SIZE;
1058         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32Attribs =
1059             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1060             PVRSRV_HAP_SINGLE_PROCESS;
1061         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].pszName = "PixelShaderUSSE";
1062         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].pszBSName =
1063             "PixelShaderUSSE BS";
1064         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].DevMemHeapType =
1065             DEVICE_MEMORY_HEAP_PERCONTEXT;
1066
1067         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32DataPageSize =
1068             SGX_MMU_PAGE_SIZE;
1069
1070         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32HeapID =
1071             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_VERTEXSHADER_HEAP_ID);
1072         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].sDevVAddrBase.uiAddr =
1073             SGX_VERTEXSHADER_HEAP_BASE;
1074         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32HeapSize =
1075             SGX_VERTEXSHADER_HEAP_SIZE;
1076         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32Attribs =
1077             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1078             PVRSRV_HAP_SINGLE_PROCESS;
1079         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].pszName =
1080             "VertexShaderUSSE";
1081         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].pszBSName =
1082             "VertexShaderUSSE BS";
1083         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].DevMemHeapType =
1084             DEVICE_MEMORY_HEAP_PERCONTEXT;
1085
1086         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32DataPageSize =
1087             SGX_MMU_PAGE_SIZE;
1088
1089         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32HeapID =
1090             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_PDSPIXEL_CODEDATA_HEAP_ID);
1091         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].sDevVAddrBase.uiAddr =
1092             SGX_PDSPIXEL_CODEDATA_HEAP_BASE;
1093         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32HeapSize =
1094             SGX_PDSPIXEL_CODEDATA_HEAP_SIZE;
1095         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32Attribs =
1096             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1097             PVRSRV_HAP_SINGLE_PROCESS;
1098         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].pszName =
1099             "PDSPixelCodeData";
1100         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].pszBSName =
1101             "PDSPixelCodeData BS";
1102         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].DevMemHeapType =
1103             DEVICE_MEMORY_HEAP_PERCONTEXT;
1104
1105         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32DataPageSize =
1106             SGX_MMU_PAGE_SIZE;
1107
1108         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32HeapID =
1109             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_PDSVERTEX_CODEDATA_HEAP_ID);
1110         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].sDevVAddrBase.
1111             uiAddr = SGX_PDSVERTEX_CODEDATA_HEAP_BASE;
1112         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32HeapSize =
1113             SGX_PDSVERTEX_CODEDATA_HEAP_SIZE;
1114         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32Attribs =
1115             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1116             PVRSRV_HAP_SINGLE_PROCESS;
1117         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].pszName =
1118             "PDSVertexCodeData";
1119         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].pszBSName =
1120             "PDSVertexCodeData BS";
1121         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].DevMemHeapType =
1122             DEVICE_MEMORY_HEAP_PERCONTEXT;
1123
1124         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32DataPageSize =
1125             SGX_MMU_PAGE_SIZE;
1126
1127         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32HeapID =
1128             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_SYNCINFO_HEAP_ID);
1129         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].sDevVAddrBase.uiAddr =
1130             SGX_SYNCINFO_HEAP_BASE;
1131         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32HeapSize =
1132             SGX_SYNCINFO_HEAP_SIZE;
1133
1134         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32Attribs =
1135             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1136             PVRSRV_HAP_MULTI_PROCESS;
1137         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].pszName = "CacheCoherent";
1138         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].pszBSName = "CacheCoherent BS";
1139
1140         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].DevMemHeapType =
1141             DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1142
1143         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32DataPageSize =
1144             SGX_MMU_PAGE_SIZE;
1145
1146         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32HeapID =
1147             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_3DPARAMETERS_HEAP_ID);
1148         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].sDevVAddrBase.uiAddr =
1149             SGX_3DPARAMETERS_HEAP_BASE;
1150         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32HeapSize =
1151             SGX_3DPARAMETERS_HEAP_SIZE;
1152         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].pszName = "3DParameters";
1153         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].pszBSName =
1154             "3DParameters BS";
1155         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32Attribs =
1156             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1157             PVRSRV_HAP_SINGLE_PROCESS;
1158         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].DevMemHeapType =
1159             DEVICE_MEMORY_HEAP_PERCONTEXT;
1160
1161         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32DataPageSize =
1162             SGX_MMU_PAGE_SIZE;
1163
1164         return PVRSRV_OK;
1165 }
1166
1167 enum PVRSRV_ERROR SGXGetClientInfoKM(void *hDevCookie,
1168                                          struct SGX_CLIENT_INFO *psClientInfo)
1169 {
1170         struct PVRSRV_SGXDEV_INFO *psDevInfo =
1171             (struct PVRSRV_SGXDEV_INFO *)
1172                         ((struct PVRSRV_DEVICE_NODE *)hDevCookie)->pvDevice;
1173
1174         psDevInfo->ui32ClientRefCount++;
1175 #ifdef PDUMP
1176         if (psDevInfo->ui32ClientRefCount == 1)
1177                 psDevInfo->psKernelCCBInfo->ui32CCBDumpWOff = 0;
1178 #endif
1179         psClientInfo->ui32ProcessID = OSGetCurrentProcessIDKM();
1180
1181         OSMemCopy(&psClientInfo->asDevData, &psDevInfo->asSGXDevData,
1182                   sizeof(psClientInfo->asDevData));
1183
1184         return PVRSRV_OK;
1185 }
1186
1187 enum PVRSRV_ERROR SGXDevInitCompatCheck(struct PVRSRV_DEVICE_NODE *psDeviceNode)
1188 {
1189         struct PVRSRV_SGXDEV_INFO *psDevInfo;
1190         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo;
1191         enum PVRSRV_ERROR eError;
1192 #if !defined(NO_HARDWARE)
1193         u32 ui32BuildOptions, ui32BuildOptionsMismatch;
1194         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1195 #endif
1196
1197         if (psDeviceNode->sDevId.eDeviceType != PVRSRV_DEVICE_TYPE_SGX) {
1198                 PVR_DPF(PVR_DBG_ERROR,
1199                          "SGXDevInitCompatCheck: Device not of type SGX");
1200                 eError = PVRSRV_ERROR_INVALID_PARAMS;
1201                 goto exit;
1202         }
1203         psDevInfo = psDeviceNode->pvDevice;
1204         psMemInfo = psDevInfo->psKernelSGXMiscMemInfo;
1205
1206 #if !defined(NO_HARDWARE)
1207
1208         eError = SGXGetBuildInfoKM(psDevInfo, psDeviceNode);
1209         if (eError != PVRSRV_OK) {
1210                 PVR_DPF(PVR_DBG_ERROR, "SGXDevInitCompatCheck: "
1211                                 "Unable to validate device DDK version");
1212                 goto exit;
1213         }
1214         psSGXFeatures =
1215             &((struct PVRSRV_SGX_MISCINFO_INFO *)(psMemInfo->pvLinAddrKM))->
1216                                                             sSGXFeatures;
1217         if ((psSGXFeatures->ui32DDKVersion !=
1218              ((PVRVERSION_MAJ << 16) | (PVRVERSION_MIN << 8) |
1219               PVRVERSION_BRANCH)) ||
1220              (psSGXFeatures->ui32DDKBuild != PVRVERSION_BUILD)) {
1221                 PVR_DPF(PVR_DBG_ERROR, "SGXDevInitCompatCheck: "
1222                         "Incompatible driver DDK revision (%ld)"
1223                         "/device DDK revision (%ld).",
1224                          PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild);
1225                 eError = PVRSRV_ERROR_DDK_VERSION_MISMATCH;
1226                 goto exit;
1227         } else {
1228                 PVR_DPF(PVR_DBG_WARNING, "(Success) SGXInit: "
1229                                 "driver DDK (%ld) and device DDK (%ld) match",
1230                          PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild);
1231         }
1232
1233         ui32BuildOptions = psSGXFeatures->ui32BuildOptions;
1234         if (ui32BuildOptions != (SGX_BUILD_OPTIONS)) {
1235                 ui32BuildOptionsMismatch =
1236                     ui32BuildOptions ^ (SGX_BUILD_OPTIONS);
1237                 if (((SGX_BUILD_OPTIONS) & ui32BuildOptionsMismatch) != 0)
1238                         PVR_DPF(PVR_DBG_ERROR, "SGXInit: "
1239                                 "Mismatch in driver and microkernel build "
1240                                 "options; extra options present in driver: "
1241                                 "(0x%lx)",
1242                                  (SGX_BUILD_OPTIONS) &
1243                                  ui32BuildOptionsMismatch);
1244
1245                 if ((ui32BuildOptions & ui32BuildOptionsMismatch) != 0)
1246                         PVR_DPF(PVR_DBG_ERROR, "SGXInit: "
1247                                 "Mismatch in driver and microkernel build "
1248                                 "options; extra options present in "
1249                                 "microkernel: (0x%lx)",
1250                                  ui32BuildOptions & ui32BuildOptionsMismatch);
1251                 eError = PVRSRV_ERROR_BUILD_MISMATCH;
1252                 goto exit;
1253         } else {
1254                 PVR_DPF(PVR_DBG_WARNING, "(Success) SGXInit: "
1255                                 "Driver and microkernel build options match.");
1256         }
1257
1258 #endif
1259         eError = PVRSRV_OK;
1260 exit:
1261         return eError;
1262 }
1263
1264 static
1265 enum PVRSRV_ERROR SGXGetBuildInfoKM(struct PVRSRV_SGXDEV_INFO *psDevInfo,
1266                                     struct PVRSRV_DEVICE_NODE *psDeviceNode)
1267 {
1268         enum PVRSRV_ERROR eError;
1269         struct SGXMKIF_COMMAND sCommandData;
1270         struct PVRSRV_SGX_MISCINFO_INFO *psSGXMiscInfoInt;
1271         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1272
1273         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo =
1274             psDevInfo->psKernelSGXMiscMemInfo;
1275
1276         if (!psMemInfo->pvLinAddrKM) {
1277                 PVR_DPF(PVR_DBG_ERROR, "SGXGetMiscInfoKM: Invalid address.");
1278                 return PVRSRV_ERROR_INVALID_PARAMS;
1279         }
1280         psSGXMiscInfoInt = psMemInfo->pvLinAddrKM;
1281         psSGXMiscInfoInt->ui32MiscInfoFlags &= ~PVRSRV_USSE_MISCINFO_READY;
1282         psSGXFeatures = &psSGXMiscInfoInt->sSGXFeatures;
1283
1284         OSMemSet(psMemInfo->pvLinAddrKM, 0,
1285                  sizeof(struct PVRSRV_SGX_MISCINFO_INFO));
1286
1287         sCommandData.ui32Data[1] = psMemInfo->sDevVAddr.uiAddr;
1288
1289         OSMemSet(psSGXFeatures, 0, sizeof(*psSGXFeatures));
1290
1291         mb();
1292
1293         eError = SGXScheduleCCBCommandKM(psDeviceNode,
1294                                          SGXMKIF_COMMAND_REQUEST_SGXMISCINFO,
1295                                          &sCommandData, KERNEL_ID, 0);
1296
1297         if (eError != PVRSRV_OK) {
1298                 PVR_DPF(PVR_DBG_ERROR,
1299                          "SGXGetMiscInfoKM: SGXScheduleCCBCommandKM failed.");
1300                 return eError;
1301         }
1302
1303 #if !defined(NO_HARDWARE)
1304         {
1305                 IMG_BOOL bTimeout = IMG_TRUE;
1306
1307                 LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US) {
1308                         if ((psSGXMiscInfoInt->
1309                              ui32MiscInfoFlags & PVRSRV_USSE_MISCINFO_READY) !=
1310                             0) {
1311                                 bTimeout = IMG_FALSE;
1312                                 break;
1313                         }
1314                 }
1315                 END_LOOP_UNTIL_TIMEOUT();
1316
1317                 if (bTimeout)
1318                         return PVRSRV_ERROR_TIMEOUT;
1319         }
1320 #endif
1321
1322         return PVRSRV_OK;
1323 }
1324
1325 enum PVRSRV_ERROR SGXGetMiscInfoKM(struct PVRSRV_SGXDEV_INFO *psDevInfo,
1326                                        struct SGX_MISC_INFO *psMiscInfo,
1327                                        struct PVRSRV_DEVICE_NODE *psDeviceNode)
1328 {
1329         switch (psMiscInfo->eRequest) {
1330         case SGX_MISC_INFO_REQUEST_CLOCKSPEED:
1331                 {
1332                         psMiscInfo->uData.ui32SGXClockSpeed =
1333                             psDevInfo->ui32CoreClockSpeed;
1334                         return PVRSRV_OK;
1335                 }
1336
1337         case SGX_MISC_INFO_REQUEST_SGXREV:
1338                 {
1339                         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1340                         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo =
1341                             psDevInfo->psKernelSGXMiscMemInfo;
1342
1343                         SGXGetBuildInfoKM(psDevInfo, psDeviceNode);
1344                         psSGXFeatures =
1345                             &((struct PVRSRV_SGX_MISCINFO_INFO *)(psMemInfo->
1346                                                   pvLinAddrKM))->sSGXFeatures;
1347
1348                         psMiscInfo->uData.sSGXFeatures = *psSGXFeatures;
1349
1350                         PVR_DPF(PVR_DBG_MESSAGE, "SGXGetMiscInfoKM: "
1351                                         "Core 0x%lx, sw ID 0x%lx, "
1352                                         "sw Rev 0x%lx\n",
1353                                  psSGXFeatures->ui32CoreRev,
1354                                  psSGXFeatures->ui32CoreIdSW,
1355                                  psSGXFeatures->ui32CoreRevSW);
1356                         PVR_DPF(PVR_DBG_MESSAGE, "SGXGetMiscInfoKM: "
1357                                         "DDK version 0x%lx, DDK build 0x%lx\n",
1358                                  psSGXFeatures->ui32DDKVersion,
1359                                  psSGXFeatures->ui32DDKBuild);
1360
1361                         return PVRSRV_OK;
1362                 }
1363
1364         case SGX_MISC_INFO_REQUEST_DRIVER_SGXREV:
1365                 {
1366                         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo =
1367                             psDevInfo->psKernelSGXMiscMemInfo;
1368                         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1369
1370                         psSGXFeatures = &((struct PVRSRV_SGX_MISCINFO_INFO *)(
1371                                         psMemInfo->pvLinAddrKM))->sSGXFeatures;
1372
1373                         OSMemSet(psMemInfo->pvLinAddrKM, 0,
1374                                  sizeof(struct PVRSRV_SGX_MISCINFO_INFO));
1375
1376                         psSGXFeatures->ui32DDKVersion =
1377                             (PVRVERSION_MAJ << 16) |
1378                             (PVRVERSION_MIN << 8) | PVRVERSION_BRANCH;
1379                         psSGXFeatures->ui32DDKBuild = PVRVERSION_BUILD;
1380
1381                         psMiscInfo->uData.sSGXFeatures = *psSGXFeatures;
1382                         return PVRSRV_OK;
1383                 }
1384
1385         case SGX_MISC_INFO_REQUEST_SET_HWPERF_STATUS:
1386                 {
1387                         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1388                             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1389                         unsigned ui32MatchingFlags;
1390
1391                         if ((psMiscInfo->uData.ui32NewHWPerfStatus &
1392                              ~(PVRSRV_SGX_HWPERF_GRAPHICS_ON |
1393                                PVRSRV_SGX_HWPERF_MK_EXECUTION_ON)) != 0) {
1394                                 return PVRSRV_ERROR_INVALID_PARAMS;
1395                         }
1396
1397                         ui32MatchingFlags = readl(&psDevInfo->
1398                                                  psSGXHostCtl->ui32HWPerfFlags);
1399                         ui32MatchingFlags &=
1400                                 psMiscInfo->uData.ui32NewHWPerfStatus;
1401                         if ((ui32MatchingFlags & PVRSRV_SGX_HWPERF_GRAPHICS_ON)
1402                             == 0UL) {
1403                                 psHWPerfCB->ui32OrdinalGRAPHICS = 0xffffffff;
1404                         }
1405                         if ((ui32MatchingFlags &
1406                              PVRSRV_SGX_HWPERF_MK_EXECUTION_ON) == 0UL) {
1407                                 psHWPerfCB->ui32OrdinalMK_EXECUTION =
1408                                     0xffffffffUL;
1409                         }
1410
1411
1412                         writel(psMiscInfo->uData.ui32NewHWPerfStatus,
1413                                 &psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1414 #if defined(PDUMP)
1415                         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
1416                                               "SGX ukernel HWPerf status %u\n",
1417                                               readl(&psDevInfo->psSGXHostCtl->
1418                                                               ui32HWPerfFlags));
1419                         PDUMPMEM(NULL, psDevInfo->psKernelSGXHostCtlMemInfo,
1420                                  offsetof(struct SGXMKIF_HOST_CTL,
1421                                           ui32HWPerfFlags),
1422                                  sizeof(psDevInfo->psSGXHostCtl->
1423                                         ui32HWPerfFlags),
1424                                  PDUMP_FLAGS_CONTINUOUS,
1425                                  MAKEUNIQUETAG(psDevInfo->
1426                                                psKernelSGXHostCtlMemInfo));
1427 #endif
1428
1429                         return PVRSRV_OK;
1430                 }
1431         case SGX_MISC_INFO_REQUEST_HWPERF_CB_ON:
1432                 {
1433
1434                         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1435                             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1436                         u32 l;
1437
1438                         psHWPerfCB->ui32OrdinalGRAPHICS = 0xffffffffUL;
1439
1440                         l = readl(&psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1441                         l |= PVRSRV_SGX_HWPERF_GRAPHICS_ON;
1442                         writel(l, &psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1443
1444                         return PVRSRV_OK;
1445                 }
1446         case SGX_MISC_INFO_REQUEST_HWPERF_CB_OFF:
1447                 {
1448                         writel(0, &psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1449
1450                         return PVRSRV_OK;
1451                 }
1452         case SGX_MISC_INFO_REQUEST_HWPERF_RETRIEVE_CB:
1453                 {
1454                         struct SGX_MISC_INFO_HWPERF_RETRIEVE_CB *psRetrieve =
1455                             &psMiscInfo->uData.sRetrieveCB;
1456                         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1457                             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1458                         unsigned i;
1459
1460                         for (i = 0;
1461                              psHWPerfCB->ui32Woff != psHWPerfCB->ui32Roff
1462                              && i < psRetrieve->ui32ArraySize; i++) {
1463                                 struct SGXMKIF_HWPERF_CB_ENTRY *psData =
1464                                     &psHWPerfCB->psHWPerfCBData[psHWPerfCB->
1465                                                                 ui32Roff];
1466
1467                                 psRetrieve->psHWPerfData[i].ui32FrameNo =
1468                                     psData->ui32FrameNo;
1469                                 psRetrieve->psHWPerfData[i].ui32Type =
1470                                     (psData->ui32Type &
1471                                      PVRSRV_SGX_HWPERF_TYPE_OP_MASK);
1472                                 psRetrieve->psHWPerfData[i].ui32StartTime =
1473                                     psData->ui32Time;
1474                                 psRetrieve->psHWPerfData[i].ui32StartTimeWraps =
1475                                     psData->ui32TimeWraps;
1476                                 psRetrieve->psHWPerfData[i].ui32EndTime =
1477                                     psData->ui32Time;
1478                                 psRetrieve->psHWPerfData[i].ui32EndTimeWraps =
1479                                     psData->ui32TimeWraps;
1480                                 psRetrieve->psHWPerfData[i].ui32ClockSpeed =
1481                                     psDevInfo->ui32CoreClockSpeed;
1482                                 psRetrieve->psHWPerfData[i].ui32TimeMax =
1483                                     psDevInfo->ui32uKernelTimerClock;
1484                                 psHWPerfCB->ui32Roff =
1485                                     (psHWPerfCB->ui32Roff + 1) &
1486                                     (SGXMKIF_HWPERF_CB_SIZE - 1);
1487                         }
1488                         psRetrieve->ui32DataCount = i;
1489                         psRetrieve->ui32Time = OSClockus();
1490                         return PVRSRV_OK;
1491                 }
1492         default:
1493                 {
1494                         return PVRSRV_ERROR_INVALID_PARAMS;
1495                 }
1496         }
1497 }
1498
1499 enum PVRSRV_ERROR SGXReadDiffCountersKM(void *hDevHandle, u32 ui32Reg,
1500                                    u32 *pui32Old, IMG_BOOL bNew, u32 ui32New,
1501                                    u32 ui32NewReset, u32 ui32CountersReg,
1502                                    u32 *pui32Time, IMG_BOOL *pbActive,
1503                                    struct PVRSRV_SGXDEV_DIFF_INFO *psDiffs)
1504 {
1505         struct SYS_DATA *psSysData;
1506         struct PVRSRV_POWER_DEV *psPowerDevice;
1507         IMG_BOOL bPowered = IMG_FALSE;
1508         struct PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
1509         struct PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1510
1511         if (bNew)
1512                 psDevInfo->ui32HWGroupRequested = ui32New;
1513         psDevInfo->ui32HWReset |= ui32NewReset;
1514
1515         SysAcquireData(&psSysData);
1516
1517         psPowerDevice = psSysData->psPowerDeviceList;
1518         while (psPowerDevice) {
1519                 if (psPowerDevice->ui32DeviceIndex ==
1520                     psDeviceNode->sDevId.ui32DeviceIndex) {
1521                         bPowered =
1522                             (IMG_BOOL)(psPowerDevice->eCurrentPowerState ==
1523                                         PVRSRV_POWER_STATE_D0);
1524                         break;
1525                 }
1526
1527                 psPowerDevice = psPowerDevice->psNext;
1528         }
1529
1530         *pbActive = bPowered;
1531
1532         {
1533                 struct PVRSRV_SGXDEV_DIFF_INFO sNew,
1534                                                *psPrev = &psDevInfo->sDiffInfo;
1535                 u32 i;
1536
1537                 sNew.ui32Time[0] = OSClockus();
1538                 *pui32Time = sNew.ui32Time[0];
1539                 if (sNew.ui32Time[0] != psPrev->ui32Time[0] && bPowered) {
1540
1541                         *pui32Old =
1542                             OSReadHWReg(psDevInfo->pvRegsBaseKM, ui32Reg);
1543
1544                         for (i = 0; i < PVRSRV_SGX_DIFF_NUM_COUNTERS; ++i) {
1545                                 sNew.aui32Counters[i] =
1546                                     OSReadHWReg(psDevInfo->pvRegsBaseKM,
1547                                                 ui32CountersReg + (i * 4));
1548                         }
1549
1550                         if (psDevInfo->ui32HWGroupRequested != *pui32Old) {
1551                                 if (psDevInfo->ui32HWReset != 0) {
1552                                         OSWriteHWReg(psDevInfo->pvRegsBaseKM,
1553                                                      ui32Reg,
1554                                                      psDevInfo->
1555                                                      ui32HWGroupRequested |
1556                                                      psDevInfo->ui32HWReset);
1557                                         psDevInfo->ui32HWReset = 0;
1558                                 }
1559                                 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Reg,
1560                                              psDevInfo->ui32HWGroupRequested);
1561                         }
1562
1563                         sNew.ui32Marker[0] = psDevInfo->ui32KickTACounter;
1564                         sNew.ui32Marker[1] = psDevInfo->ui32KickTARenderCounter;
1565
1566                         sNew.ui32Time[1] = readl(
1567                                 &psDevInfo->psSGXHostCtl->ui32TimeWraps);
1568
1569                         for (i = 0; i < PVRSRV_SGX_DIFF_NUM_COUNTERS; ++i) {
1570                                 psDiffs->aui32Counters[i] =
1571                                     sNew.aui32Counters[i] -
1572                                     psPrev->aui32Counters[i];
1573                         }
1574
1575                         psDiffs->ui32Marker[0] =
1576                             sNew.ui32Marker[0] - psPrev->ui32Marker[0];
1577                         psDiffs->ui32Marker[1] =
1578                             sNew.ui32Marker[1] - psPrev->ui32Marker[1];
1579
1580                         psDiffs->ui32Time[0] =
1581                             sNew.ui32Time[0] - psPrev->ui32Time[0];
1582                         psDiffs->ui32Time[1] =
1583                             sNew.ui32Time[1] - psPrev->ui32Time[1];
1584
1585                         *psPrev = sNew;
1586                 } else {
1587                         for (i = 0; i < PVRSRV_SGX_DIFF_NUM_COUNTERS; ++i)
1588                                 psDiffs->aui32Counters[i] = 0;
1589
1590                         psDiffs->ui32Marker[0] = 0;
1591                         psDiffs->ui32Marker[1] = 0;
1592
1593                         psDiffs->ui32Time[0] = 0;
1594                         psDiffs->ui32Time[1] = 0;
1595                 }
1596         }
1597
1598         SGXTestActivePowerEvent(psDeviceNode);
1599
1600         return PVRSRV_OK;
1601 }
1602
1603 enum PVRSRV_ERROR SGXReadHWPerfCBKM(void *hDevHandle, u32 ui32ArraySize,
1604                         struct PVRSRV_SGX_HWPERF_CB_ENTRY *psClientHWPerfEntry,
1605                         u32 *pui32DataCount, u32 *pui32ClockSpeed,
1606                         u32 *pui32HostTimeStamp)
1607 {
1608         enum PVRSRV_ERROR eError = PVRSRV_OK;
1609         struct PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
1610         struct PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1611         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1612             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1613         unsigned i;
1614
1615         for (i = 0;
1616              psHWPerfCB->ui32Woff != psHWPerfCB->ui32Roff && i < ui32ArraySize;
1617              i++) {
1618                 struct SGXMKIF_HWPERF_CB_ENTRY *psMKPerfEntry =
1619                     &psHWPerfCB->psHWPerfCBData[psHWPerfCB->ui32Roff];
1620
1621                 psClientHWPerfEntry[i].ui32FrameNo = psMKPerfEntry->ui32FrameNo;
1622                 psClientHWPerfEntry[i].ui32Type = psMKPerfEntry->ui32Type;
1623                 psClientHWPerfEntry[i].ui32Ordinal = psMKPerfEntry->ui32Ordinal;
1624                 psClientHWPerfEntry[i].ui32Clocksx16 =
1625                     SGXConvertTimeStamp(psDevInfo, psMKPerfEntry->ui32TimeWraps,
1626                                         psMKPerfEntry->ui32Time);
1627                 OSMemCopy(&psClientHWPerfEntry[i].ui32Counters[0],
1628                           &psMKPerfEntry->ui32Counters[0],
1629                           sizeof(psMKPerfEntry->ui32Counters));
1630
1631                 psHWPerfCB->ui32Roff =
1632                     (psHWPerfCB->ui32Roff + 1) & (SGXMKIF_HWPERF_CB_SIZE - 1);
1633         }
1634
1635         *pui32DataCount = i;
1636         *pui32ClockSpeed = psDevInfo->ui32CoreClockSpeed;
1637         *pui32HostTimeStamp = OSClockus();
1638
1639         return eError;
1640 }