pvr/sgxinit.c

   1 /**********************************************************************
   2  *
   3  * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful but, except
  10  * as otherwise stated in writing, without any warranty; without even the
  11  * implied warranty of merchantability or fitness for a particular purpose.
  12  * See the GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * Imagination Technologies Ltd. <gpl-support@imgtec.com>
  23  * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
  24  *
  25  ******************************************************************************/
  26
  27 #include <stddef.h>
  28
  29 #include <linux/workqueue.h>
  30 #include <linux/io.h>
  31 #include <linux/slab.h>
  32 #include <linux/sched.h>
  33 #include <linux/mm.h>
  34 #include <linux/vmalloc.h>
  35
  36 #include "sgxdefs.h"
  37 #include "sgxmmu.h"
  38 #include "services_headers.h"
  39 #include "buffer_manager.h"
  40 #include "sgxapi_km.h"
  41 #include "sgxinfo.h"
  42 #include "sgxinfokm.h"
  43 #include "sgxconfig.h"
  44 #include "sysconfig.h"
  45 #include "pvr_bridge_km.h"
  46 #include "sgx_bridge_km.h"
  47 #include "resman.h"
  48 #include "bridged_support.h"
  49
  50 #include "pvr_pdump.h"
  51 #include "ra.h"
  52 #include "mmu.h"
  53 #include "mm.h"
  54 #include "handle.h"
  55 #include "perproc.h"
  56
  57 #include "sgxutils.h"
  58 #include "pvrversion.h"
  59 #include "sgx_options.h"
  60
  61 #ifdef CONFIG_DEBUG_FS
  62 #include "pvr_debugfs.h"
  63 #endif
  64
  65 static IMG_BOOL SGX_ISRHandler(void *pvData);
  66
  67 static u32 gui32EventStatusServicesByISR;
  68
  69 static enum PVRSRV_ERROR SGXGetBuildInfoKM(struct PVRSRV_SGXDEV_INFO *psDevInfo,
  70                                     struct PVRSRV_DEVICE_NODE *psDeviceNode);
  71
  72 static void SGXCommandComplete(struct PVRSRV_DEVICE_NODE *psDeviceNode)
  73 {
  74         BUG_ON(in_irq());
  75
  76         SGXScheduleProcessQueuesKM(psDeviceNode);
  77 }
  78
  79 static u32 DeinitDevInfo(struct PVRSRV_SGXDEV_INFO *psDevInfo)
  80 {
  81         if (psDevInfo->psKernelCCBInfo != NULL)
  82                 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
  83                           sizeof(struct PVRSRV_SGX_CCB_INFO),
  84                           psDevInfo->psKernelCCBInfo, NULL);
  85
  86         return PVRSRV_OK;
  87 }
  88
  89 static enum PVRSRV_ERROR InitDevInfo(struct PVRSRV_PER_PROCESS_DATA *psPerProc,
  90                                 struct PVRSRV_DEVICE_NODE *psDeviceNode,
  91                                 struct SGX_BRIDGE_INIT_INFO *psInitInfo)
  92 {
  93         struct PVRSRV_SGXDEV_INFO *psDevInfo =
  94             (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
  95         enum PVRSRV_ERROR eError;
  96
  97         struct PVRSRV_SGX_CCB_INFO *psKernelCCBInfo = NULL;
  98
  99         PVR_UNREFERENCED_PARAMETER(psPerProc);
 100         psDevInfo->sScripts = psInitInfo->sScripts;
 101
 102         psDevInfo->psKernelCCBMemInfo =
 103             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelCCBMemInfo;
 104         psDevInfo->psKernelCCB =
 105             (struct PVRSRV_SGX_KERNEL_CCB *)psDevInfo->psKernelCCBMemInfo->
 106                                                     pvLinAddrKM;
 107
 108         psDevInfo->psKernelCCBCtlMemInfo =
 109             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelCCBCtlMemInfo;
 110         psDevInfo->psKernelCCBCtl =
 111             (struct PVRSRV_SGX_CCB_CTL *)psDevInfo->psKernelCCBCtlMemInfo->
 112                                                     pvLinAddrKM;
 113
 114         psDevInfo->psKernelCCBEventKickerMemInfo =
 115             (struct PVRSRV_KERNEL_MEM_INFO *)
 116                             psInitInfo->hKernelCCBEventKickerMemInfo;
 117         psDevInfo->pui32KernelCCBEventKicker =
 118             (u32 *)psDevInfo->psKernelCCBEventKickerMemInfo->pvLinAddrKM;
 119
 120         psDevInfo->psKernelSGXHostCtlMemInfo =
 121             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->
 122                                                     hKernelSGXHostCtlMemInfo;
 123         psDevInfo->psSGXHostCtl = (struct SGXMKIF_HOST_CTL __force __iomem *)
 124                 psDevInfo->psKernelSGXHostCtlMemInfo->pvLinAddrKM;
 125
 126         psDevInfo->psKernelSGXTA3DCtlMemInfo =
 127             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->
 128                                                     hKernelSGXTA3DCtlMemInfo;
 129
 130         psDevInfo->psKernelSGXMiscMemInfo =
 131             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXMiscMemInfo;
 132
 133         psDevInfo->psKernelHWPerfCBMemInfo =
 134             (struct PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelHWPerfCBMemInfo;
 135         psDevInfo->psKernelEDMStatusBufferMemInfo =
 136                                     psInitInfo->hKernelEDMStatusBufferMemInfo;
 137
 138         eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
 139                             sizeof(struct PVRSRV_SGX_CCB_INFO),
 140                             (void **)&psKernelCCBInfo, NULL);
 141         if (eError != PVRSRV_OK) {
 142                 PVR_DPF(PVR_DBG_ERROR, "InitDevInfo: Failed to alloc memory");
 143                 goto failed_allockernelccb;
 144         }
 145
 146         OSMemSet(psKernelCCBInfo, 0, sizeof(struct PVRSRV_SGX_CCB_INFO));
 147         psKernelCCBInfo->psCCBMemInfo = psDevInfo->psKernelCCBMemInfo;
 148         psKernelCCBInfo->psCCBCtlMemInfo = psDevInfo->psKernelCCBCtlMemInfo;
 149         psKernelCCBInfo->psCommands = psDevInfo->psKernelCCB->asCommands;
 150         psKernelCCBInfo->pui32WriteOffset =
 151                                 &psDevInfo->psKernelCCBCtl->ui32WriteOffset;
 152         psKernelCCBInfo->pui32ReadOffset =
 153                                 &psDevInfo->psKernelCCBCtl->ui32ReadOffset;
 154         psDevInfo->psKernelCCBInfo = psKernelCCBInfo;
 155
 156         psDevInfo->ui32HostKickAddress = psInitInfo->ui32HostKickAddress;
 157
 158         psDevInfo->ui32GetMiscInfoAddress = psInitInfo->ui32GetMiscInfoAddress;
 159
 160         psDevInfo->bForcePTOff = IMG_FALSE;
 161
 162         psDevInfo->ui32CacheControl = psInitInfo->ui32CacheControl;
 163
 164         psDevInfo->ui32EDMTaskReg0 = psInitInfo->ui32EDMTaskReg0;
 165         psDevInfo->ui32EDMTaskReg1 = psInitInfo->ui32EDMTaskReg1;
 166         psDevInfo->ui32ClkGateStatusReg = psInitInfo->ui32ClkGateStatusReg;
 167         psDevInfo->ui32ClkGateStatusMask = psInitInfo->ui32ClkGateStatusMask;
 168
 169         OSMemCopy(&psDevInfo->asSGXDevData, &psInitInfo->asInitDevData,
 170                   sizeof(psDevInfo->asSGXDevData));
 171
 172         psDevInfo->state_buf_ofs = psInitInfo->state_buf_ofs;
 173
 174         return PVRSRV_OK;
 175
 176 failed_allockernelccb:
 177         DeinitDevInfo(psDevInfo);
 178
 179         return eError;
 180 }
 181
 182 static enum PVRSRV_ERROR SGXRunScript(struct PVRSRV_SGXDEV_INFO *psDevInfo,
 183                                  union SGX_INIT_COMMAND *psScript,
 184                                  u32 ui32NumInitCommands)
 185 {
 186         u32 ui32PC;
 187         union SGX_INIT_COMMAND *psComm;
 188
 189         for (ui32PC = 0, psComm = psScript;
 190              ui32PC < ui32NumInitCommands; ui32PC++, psComm++) {
 191                 switch (psComm->eOp) {
 192                 case SGX_INIT_OP_WRITE_HW_REG:
 193                         {
 194                                 OSWriteHWReg(psDevInfo->pvRegsBaseKM,
 195                                              psComm->sWriteHWReg.ui32Offset,
 196                                              psComm->sWriteHWReg.ui32Value);
 197                                 PDUMPREG(psComm->sWriteHWReg.ui32Offset,
 198                                          psComm->sWriteHWReg.ui32Value);
 199                                 break;
 200                         }
 201 #if defined(PDUMP)
 202                 case SGX_INIT_OP_PDUMP_HW_REG:
 203                         {
 204                                 PDUMPREG(psComm->sPDumpHWReg.ui32Offset,
 205                                          psComm->sPDumpHWReg.ui32Value);
 206                                 break;
 207                         }
 208 #endif
 209                 case SGX_INIT_OP_HALT:
 210                         {
 211                                 return PVRSRV_OK;
 212                         }
 213                 case SGX_INIT_OP_ILLEGAL:
 214
 215                 default:
 216                         {
 217                                 PVR_DPF(PVR_DBG_ERROR,
 218                                      "SGXRunScript: PC %d: Illegal command: %d",
 219                                       ui32PC, psComm->eOp);
 220                                 return PVRSRV_ERROR_GENERIC;
 221                         }
 222                 }
 223
 224         }
 225
 226         return PVRSRV_ERROR_GENERIC;
 227 }
 228
 229 enum PVRSRV_ERROR SGXInitialise(struct PVRSRV_SGXDEV_INFO *psDevInfo,
 230                                   IMG_BOOL bHardwareRecovery)
 231 {
 232         enum PVRSRV_ERROR eError;
 233
 234         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 235                               "SGX initialisation script part 1\n");
 236         eError =
 237             SGXRunScript(psDevInfo, psDevInfo->sScripts.asInitCommandsPart1,
 238                          SGX_MAX_INIT_COMMANDS);
 239         if (eError != PVRSRV_OK) {
 240                 PVR_DPF(PVR_DBG_ERROR,
 241                          "SGXInitialise: SGXRunScript (part 1) failed (%d)",
 242                          eError);
 243                 return PVRSRV_ERROR_GENERIC;
 244         }
 245         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 246                               "End of SGX initialisation script part 1\n");
 247
 248         SGXReset(psDevInfo, PDUMP_FLAGS_CONTINUOUS);
 249
 250
 251
 252         *psDevInfo->pui32KernelCCBEventKicker = 0;
 253 #if defined(PDUMP)
 254         PDUMPMEM(NULL, psDevInfo->psKernelCCBEventKickerMemInfo, 0,
 255                  sizeof(*psDevInfo->pui32KernelCCBEventKicker),
 256                  PDUMP_FLAGS_CONTINUOUS,
 257                  MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
 258 #endif
 259
 260         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 261                               "SGX initialisation script part 2\n");
 262         eError =
 263             SGXRunScript(psDevInfo, psDevInfo->sScripts.asInitCommandsPart2,
 264                          SGX_MAX_INIT_COMMANDS);
 265         if (eError != PVRSRV_OK) {
 266                 PVR_DPF(PVR_DBG_ERROR,
 267                          "SGXInitialise: SGXRunScript (part 2) failed (%d)",
 268                          eError);
 269                 return PVRSRV_ERROR_GENERIC;
 270         }
 271         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
 272                               "End of SGX initialisation script part 2\n");
 273
 274         SGXStartTimer(psDevInfo, (IMG_BOOL)!bHardwareRecovery);
 275
 276         if (bHardwareRecovery) {
 277                 struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 278                     psDevInfo->psSGXHostCtl;
 279
 280                 if (PollForValueKM(&psSGXHostCtl->ui32InterruptClearFlags, 0,
 281                      PVRSRV_USSE_EDM_INTERRUPT_HWR,
 282                      MAX_HW_TIME_US / WAIT_TRY_COUNT, 1000) != PVRSRV_OK) {
 283                         PVR_DPF(PVR_DBG_ERROR, "SGXInitialise: "
 284                                         "Wait for uKernel HW Recovery failed");
 285                         PVR_DBG_BREAK;
 286                         return PVRSRV_ERROR_RETRY;
 287                 }
 288         }
 289
 290         PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset ==
 291                    psDevInfo->psKernelCCBCtl->ui32WriteOffset);
 292
 293         return PVRSRV_OK;
 294 }
 295
 296 enum PVRSRV_ERROR SGXDeinitialise(void *hDevCookie)
 297 {
 298         struct PVRSRV_SGXDEV_INFO *psDevInfo = (struct PVRSRV_SGXDEV_INFO *)
 299                                                                    hDevCookie;
 300         enum PVRSRV_ERROR eError;
 301
 302         if (psDevInfo->pvRegsBaseKM == NULL)
 303                 return PVRSRV_OK;
 304
 305         eError = SGXRunScript(psDevInfo, psDevInfo->sScripts.asDeinitCommands,
 306                          SGX_MAX_DEINIT_COMMANDS);
 307         if (eError != PVRSRV_OK) {
 308                 PVR_DPF(PVR_DBG_ERROR,
 309                          "SGXDeinitialise: SGXRunScript failed (%d)", eError);
 310                 return PVRSRV_ERROR_GENERIC;
 311         }
 312
 313         return PVRSRV_OK;
 314 }
 315
 316 static enum PVRSRV_ERROR DevInitSGXPart1(void *pvDeviceNode)
 317 {
 318         struct PVRSRV_SGXDEV_INFO *psDevInfo;
 319         void *hKernelDevMemContext;
 320         struct IMG_DEV_PHYADDR sPDDevPAddr;
 321         u32 i;
 322         struct PVRSRV_DEVICE_NODE *psDeviceNode = (struct PVRSRV_DEVICE_NODE *)
 323                                                                    pvDeviceNode;
 324         struct DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap =
 325             psDeviceNode->sDevMemoryInfo.psDeviceMemoryHeap;
 326         enum PVRSRV_ERROR eError;
 327
 328         PDUMPCOMMENT("SGX Initialisation Part 1");
 329
 330         PDUMPCOMMENT("SGX Core Version Information: %s",
 331                      SGX_CORE_FRIENDLY_NAME);
 332         PDUMPCOMMENT("SGX Core Revision Information: multi rev support");
 333
 334         if (OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 335                        sizeof(struct PVRSRV_SGXDEV_INFO),
 336                        (void **)&psDevInfo, NULL) != PVRSRV_OK) {
 337                 PVR_DPF(PVR_DBG_ERROR,
 338                         "DevInitSGXPart1 : Failed to alloc memory for DevInfo");
 339                 return PVRSRV_ERROR_OUT_OF_MEMORY;
 340         }
 341         OSMemSet(psDevInfo, 0, sizeof(struct PVRSRV_SGXDEV_INFO));
 342
 343         psDevInfo->eDeviceType = DEV_DEVICE_TYPE;
 344         psDevInfo->eDeviceClass = DEV_DEVICE_CLASS;
 345
 346         psDeviceNode->pvDevice = (void *) psDevInfo;
 347
 348         psDevInfo->pvDeviceMemoryHeap = (void *) psDeviceMemoryHeap;
 349
 350         hKernelDevMemContext = BM_CreateContext(psDeviceNode, &sPDDevPAddr,
 351                                                 NULL, NULL);
 352         if (!hKernelDevMemContext)
 353                 goto err1;
 354
 355         psDevInfo->sKernelPDDevPAddr = sPDDevPAddr;
 356
 357         for (i = 0; i < psDeviceNode->sDevMemoryInfo.ui32HeapCount; i++) {
 358                 void *hDevMemHeap;
 359
 360                 switch (psDeviceMemoryHeap[i].DevMemHeapType) {
 361                 case DEVICE_MEMORY_HEAP_KERNEL:
 362                 case DEVICE_MEMORY_HEAP_SHARED:
 363                 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
 364                         {
 365                                 hDevMemHeap =
 366                                     BM_CreateHeap(hKernelDevMemContext,
 367                                                   &psDeviceMemoryHeap[i]);
 368
 369                                 if (!hDevMemHeap)
 370                                         goto err2;
 371
 372                                 psDeviceMemoryHeap[i].hDevMemHeap = hDevMemHeap;
 373                                 break;
 374                         }
 375                 }
 376         }
 377
 378         eError = MMU_BIFResetPDAlloc(psDevInfo);
 379         if (eError != PVRSRV_OK) {
 380                 PVR_DPF(PVR_DBG_ERROR,
 381                          "DevInitSGX : Failed to alloc memory for BIF reset");
 382                 goto err2;
 383         }
 384
 385         return PVRSRV_OK;
 386 err2:
 387         while (i) {
 388                 int type;
 389
 390                 i--;
 391                 type = psDeviceMemoryHeap[i].DevMemHeapType;
 392                 if (type != DEVICE_MEMORY_HEAP_KERNEL &&
 393                     type != DEVICE_MEMORY_HEAP_SHARED &&
 394                     type != DEVICE_MEMORY_HEAP_SHARED_EXPORTED)
 395                         continue;
 396                 BM_DestroyHeap(psDeviceMemoryHeap[i].hDevMemHeap);
 397         }
 398         BM_DestroyContext(hKernelDevMemContext);
 399 err1:
 400         OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 401                   sizeof(struct PVRSRV_SGXDEV_INFO), psDevInfo, NULL);
 402
 403         return PVRSRV_ERROR_GENERIC;
 404 }
 405
 406 enum PVRSRV_ERROR SGXGetInfoForSrvinitKM(void *hDevHandle,
 407                                 struct SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo)
 408 {
 409         struct PVRSRV_DEVICE_NODE *psDeviceNode;
 410         struct PVRSRV_SGXDEV_INFO *psDevInfo;
 411         enum PVRSRV_ERROR eError;
 412
 413         PDUMPCOMMENT("SGXGetInfoForSrvinit");
 414
 415         psDeviceNode = (struct PVRSRV_DEVICE_NODE *)hDevHandle;
 416         psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 417
 418         psInitInfo->sPDDevPAddr = psDevInfo->sKernelPDDevPAddr;
 419
 420         eError =
 421             PVRSRVGetDeviceMemHeapsKM(hDevHandle, &psInitInfo->asHeapInfo[0]);
 422         if (eError != PVRSRV_OK) {
 423                 PVR_DPF(PVR_DBG_ERROR, "SGXGetInfoForSrvinit: "
 424                                 "PVRSRVGetDeviceMemHeapsKM failed (%d)",
 425                          eError);
 426                 return PVRSRV_ERROR_GENERIC;
 427         }
 428
 429         return eError;
 430 }
 431
 432 enum PVRSRV_ERROR DevInitSGXPart2KM(struct PVRSRV_PER_PROCESS_DATA *psPerProc,
 433                                    void *hDevHandle,
 434                                    struct SGX_BRIDGE_INIT_INFO *psInitInfo)
 435 {
 436         struct PVRSRV_DEVICE_NODE *psDeviceNode;
 437         struct PVRSRV_SGXDEV_INFO *psDevInfo;
 438         enum PVRSRV_ERROR eError;
 439         struct SGX_DEVICE_MAP *psSGXDeviceMap;
 440         enum PVR_POWER_STATE eDefaultPowerState;
 441         u32 l;
 442
 443         PDUMPCOMMENT("SGX Initialisation Part 2");
 444
 445         psDeviceNode = (struct PVRSRV_DEVICE_NODE *)hDevHandle;
 446         psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 447
 448         eError = InitDevInfo(psPerProc, psDeviceNode, psInitInfo);
 449         if (eError != PVRSRV_OK) {
 450                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM: "
 451                                         "Failed to load EDM program");
 452                 goto failed_init_dev_info;
 453         }
 454
 455
 456         eError = SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
 457                                        (void **) &psSGXDeviceMap);
 458         if (eError != PVRSRV_OK) {
 459                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM: "
 460                                         "Failed to get device memory map!");
 461                 return PVRSRV_ERROR_INIT_FAILURE;
 462         }
 463
 464         if (psSGXDeviceMap->pvRegsCpuVBase) {
 465                 psDevInfo->pvRegsBaseKM = psSGXDeviceMap->pvRegsCpuVBase;
 466         } else {
 467                 psDevInfo->pvRegsBaseKM =
 468                     OSMapPhysToLin(psSGXDeviceMap->sRegsCpuPBase,
 469                                    psSGXDeviceMap->ui32RegsSize,
 470                                    PVRSRV_HAP_KERNEL_ONLY | PVRSRV_HAP_UNCACHED,
 471                                    NULL);
 472                 if (!psDevInfo->pvRegsBaseKM) {
 473                         PVR_DPF(PVR_DBG_ERROR,
 474                                  "DevInitSGXPart2KM: Failed to map in regs\n");
 475                         return PVRSRV_ERROR_BAD_MAPPING;
 476                 }
 477         }
 478         psDevInfo->ui32RegSize = psSGXDeviceMap->ui32RegsSize;
 479         psDevInfo->sRegsPhysBase = psSGXDeviceMap->sRegsSysPBase;
 480
 481         psDeviceNode->pvISRData = psDeviceNode;
 482
 483         PVR_ASSERT(psDeviceNode->pfnDeviceISR == SGX_ISRHandler);
 484
 485         pvr_dev_lock();
 486         l = readl(&psDevInfo->psSGXHostCtl->ui32PowerStatus);
 487         l |= PVRSRV_USSE_EDM_POWMAN_NO_WORK;
 488         writel(l, &psDevInfo->psSGXHostCtl->ui32PowerStatus);
 489         pvr_dev_unlock();
 490         eDefaultPowerState = PVRSRV_POWER_STATE_D3;
 491
 492         eError = PVRSRVRegisterPowerDevice(psDeviceNode->sDevId.ui32DeviceIndex,
 493                                            SGXPrePowerStateExt,
 494                                            SGXPostPowerStateExt,
 495                                            SGXPreClockSpeedChange,
 496                                            SGXPostClockSpeedChange,
 497                                            (void *) psDeviceNode,
 498                                            PVRSRV_POWER_STATE_D3,
 499                                            eDefaultPowerState);
 500         if (eError != PVRSRV_OK) {
 501                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM: "
 502                                 "failed to register device with power manager");
 503                 return eError;
 504         }
 505
 506         OSMemSet(psDevInfo->psKernelCCB, 0,
 507                  sizeof(struct PVRSRV_SGX_KERNEL_CCB));
 508         OSMemSet(psDevInfo->psKernelCCBCtl, 0,
 509                  sizeof(struct PVRSRV_SGX_CCB_CTL));
 510         OSMemSet(psDevInfo->pui32KernelCCBEventKicker, 0,
 511                  sizeof(*psDevInfo->pui32KernelCCBEventKicker));
 512         PDUMPCOMMENT("Initialise Kernel CCB");
 513         PDUMPMEM(NULL, psDevInfo->psKernelCCBMemInfo, 0,
 514                  sizeof(struct PVRSRV_SGX_KERNEL_CCB), PDUMP_FLAGS_CONTINUOUS,
 515                  MAKEUNIQUETAG(psDevInfo->psKernelCCBMemInfo));
 516         PDUMPCOMMENT("Initialise Kernel CCB Control");
 517         PDUMPMEM(NULL, psDevInfo->psKernelCCBCtlMemInfo, 0,
 518                  sizeof(struct PVRSRV_SGX_CCB_CTL), PDUMP_FLAGS_CONTINUOUS,
 519                  MAKEUNIQUETAG(psDevInfo->psKernelCCBCtlMemInfo));
 520         PDUMPCOMMENT("Initialise Kernel CCB Event Kicker");
 521         PDUMPMEM(NULL, psDevInfo->psKernelCCBEventKickerMemInfo, 0,
 522                  sizeof(*psDevInfo->pui32KernelCCBEventKicker),
 523                  PDUMP_FLAGS_CONTINUOUS,
 524                  MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
 525
 526         psDevInfo->hTimer = SGXOSTimerInit(psDeviceNode);
 527         if (!psDevInfo->hTimer)
 528                 PVR_DPF(PVR_DBG_ERROR, "DevInitSGXPart2KM : "
 529                         "Failed to initialize HW recovery timer");
 530
 531         return PVRSRV_OK;
 532
 533 failed_init_dev_info:
 534         return eError;
 535 }
 536
 537 static enum PVRSRV_ERROR DevDeInitSGX(void *pvDeviceNode)
 538 {
 539         struct PVRSRV_DEVICE_NODE *psDeviceNode =
 540                 (struct PVRSRV_DEVICE_NODE *)pvDeviceNode;
 541         struct PVRSRV_SGXDEV_INFO *psDevInfo =
 542                 (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 543         enum PVRSRV_ERROR eError;
 544         u32 ui32Heap;
 545         struct DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
 546         struct SGX_DEVICE_MAP *psSGXDeviceMap;
 547
 548         if (!psDevInfo) {
 549                 PVR_DPF(PVR_DBG_ERROR, "DevDeInitSGX: Null DevInfo");
 550                 return PVRSRV_OK;
 551         }
 552         if (psDevInfo->hTimer) {
 553                 SGXOSTimerCancel(psDevInfo->hTimer);
 554                 SGXOSTimerDeInit(psDevInfo->hTimer);
 555                 psDevInfo->hTimer = NULL;
 556         }
 557
 558         MMU_BIFResetPDFree(psDevInfo);
 559
 560         DeinitDevInfo(psDevInfo);
 561
 562
 563         psDeviceMemoryHeap =
 564             (struct DEVICE_MEMORY_HEAP_INFO *)psDevInfo->pvDeviceMemoryHeap;
 565         for (ui32Heap = 0;
 566              ui32Heap < psDeviceNode->sDevMemoryInfo.ui32HeapCount;
 567              ui32Heap++) {
 568                 switch (psDeviceMemoryHeap[ui32Heap].DevMemHeapType) {
 569                 case DEVICE_MEMORY_HEAP_KERNEL:
 570                 case DEVICE_MEMORY_HEAP_SHARED:
 571                 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
 572                         {
 573                                 if (psDeviceMemoryHeap[ui32Heap].hDevMemHeap !=
 574                                     NULL)
 575                                         BM_DestroyHeap(psDeviceMemoryHeap
 576                                                        [ui32Heap].hDevMemHeap);
 577                                 break;
 578                         }
 579                 }
 580         }
 581
 582         if (!pvr_put_ctx(psDeviceNode->sDevMemoryInfo.pBMKernelContext))
 583                 pr_err("%s: kernel context still in use, can't free it",
 584                         __func__);
 585
 586         eError = PVRSRVRemovePowerDevice(
 587                                 ((struct PVRSRV_DEVICE_NODE *)pvDeviceNode)->
 588                                   sDevId.ui32DeviceIndex);
 589         if (eError != PVRSRV_OK)
 590                 return eError;
 591
 592         eError = SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
 593                                        (void **)&psSGXDeviceMap);
 594         if (eError != PVRSRV_OK) {
 595                 PVR_DPF(PVR_DBG_ERROR,
 596                          "DevDeInitSGX: Failed to get device memory map!");
 597                 return eError;
 598         }
 599
 600         if (!psSGXDeviceMap->pvRegsCpuVBase)
 601                 if (psDevInfo->pvRegsBaseKM != NULL)
 602                         OSUnMapPhysToLin(psDevInfo->pvRegsBaseKM,
 603                                          psDevInfo->ui32RegSize,
 604                                          PVRSRV_HAP_KERNEL_ONLY |
 605                                                  PVRSRV_HAP_UNCACHED,
 606                                          NULL);
 607
 608         OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 609                   sizeof(struct PVRSRV_SGXDEV_INFO), psDevInfo, NULL);
 610
 611         psDeviceNode->pvDevice = NULL;
 612
 613         if (psDeviceMemoryHeap != NULL)
 614                 OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
 615                           sizeof(struct DEVICE_MEMORY_HEAP_INFO) *
 616                           psDeviceNode->sDevMemoryInfo.ui32HeapCount,
 617                           psDeviceMemoryHeap, NULL);
 618
 619         return PVRSRV_OK;
 620 }
 621
 622 static struct PVRSRV_PER_PROCESS_DATA *find_cur_proc_data(
 623                                         struct PVRSRV_DEVICE_NODE *dev)
 624 {
 625         struct PVRSRV_SGXDEV_INFO *dev_info = dev->pvDevice;
 626         u32 page_dir = readl(dev_info->pvRegsBaseKM +
 627                                 EUR_CR_BIF_DIR_LIST_BASE0);
 628         struct BM_CONTEXT *bm_ctx;
 629         struct RESMAN_CONTEXT *res_ctx = NULL;
 630         struct PVRSRV_PER_PROCESS_DATA *proc_data = NULL;
 631
 632         bm_ctx = bm_find_context(dev->sDevMemoryInfo.pBMContext, page_dir);
 633         if (bm_ctx)
 634                 res_ctx = pvr_get_resman_ctx(bm_ctx);
 635
 636         if (res_ctx)
 637                 proc_data = pvr_get_proc_by_ctx(res_ctx);
 638
 639         return proc_data;
 640 }
 641
 642 static void pr_err_process_info(struct PVRSRV_PER_PROCESS_DATA *proc)
 643 {
 644         struct task_struct *tsk;
 645         int pid;
 646
 647         if (!proc)
 648                 return;
 649
 650         pid = proc->ui32PID;
 651         rcu_read_lock();
 652         tsk = pid_task(find_vpid(pid), PIDTYPE_PID);
 653         pr_err("PID = %d, process name = %s\n", pid, tsk->comm);
 654         rcu_read_unlock();
 655 }
 656
 657 static void pr_err_sgx_registers(struct PVRSRV_SGXDEV_INFO *psDevInfo)
 658 {
 659         pr_err("EVENT_STATUS =     0x%08X\n"
 660                 "EVENT_STATUS2 =    0x%08X\n"
 661                 "BIF_CTRL =         0x%08X\n"
 662                 "BIF_INT_STAT =     0x%08X\n"
 663                 "BIF_MEM_REQ_STAT = 0x%08X\n"
 664                 "BIF_FAULT  =       0x%08X\n"
 665                 "CLKGATECTL =       0x%08X\n",
 666                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_EVENT_STATUS),
 667                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_EVENT_STATUS2),
 668                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_CTRL),
 669                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_INT_STAT),
 670                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
 671                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_BIF_FAULT),
 672                 readl(psDevInfo->pvRegsBaseKM + EUR_CR_CLKGATECTL));
 673 }
 674
 675 /* Should be called with pvr_lock held */
 676 void
 677 HWRecoveryResetSGX(struct PVRSRV_DEVICE_NODE *psDeviceNode, const char *caller)
 678 {
 679         enum PVRSRV_ERROR eError;
 680         struct PVRSRV_SGXDEV_INFO *psDevInfo =
 681             (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 682         struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 683                                         psDevInfo->psSGXHostCtl;
 684         struct PVRSRV_PER_PROCESS_DATA *proc;
 685         u32 l;
 686         int max_retries = 10;
 687
 688         BUG_ON(!pvr_is_locked());
 689
 690         l = readl(&psSGXHostCtl->ui32InterruptClearFlags);
 691         l |= PVRSRV_USSE_EDM_INTERRUPT_HWR;
 692         writel(l, &psSGXHostCtl->ui32InterruptClearFlags);
 693
 694         pr_err("SGX Hardware Recovery triggered (from %s)\n", caller);
 695
 696         proc = find_cur_proc_data(psDeviceNode);
 697
 698         pr_err_process_info(proc);
 699         pr_err_sgx_registers(psDevInfo);
 700
 701 #ifdef CONFIG_DEBUG_FS
 702         pvr_hwrec_dump(proc, psDevInfo);
 703 #endif
 704
 705         PDUMPSUSPEND();
 706
 707         do {
 708                 eError = SGXInitialise(psDevInfo, IMG_TRUE);
 709                 if (eError != PVRSRV_ERROR_RETRY)
 710                         break;
 711         } while (max_retries--);
 712
 713         if (eError != PVRSRV_OK) {
 714                 pr_err("%s: recovery failed (%d). Disabling the driver",
 715                         __func__, eError);
 716                 pvr_disable();
 717
 718                 PDUMPRESUME();
 719
 720                 return;
 721         }
 722
 723         PDUMPRESUME();
 724
 725         SGXScheduleProcessQueues(psDeviceNode);
 726
 727         PVRSRVProcessQueues(IMG_TRUE);
 728 }
 729
 730 static unsigned long sgx_reset_forced;
 731
 732 static void SGXOSTimer(struct work_struct *work)
 733 {
 734         struct timer_work_data *data = container_of(work,
 735                                                     struct timer_work_data,
 736                                                     work.work);
 737         struct PVRSRV_DEVICE_NODE *psDeviceNode = data->psDeviceNode;
 738         struct PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
 739         static u32 ui32EDMTasks;
 740         static u32 ui32LockupCounter;
 741         static u32 ui32NumResets;
 742         u32 ui32CurrentEDMTasks;
 743         IMG_BOOL bLockup = IMG_FALSE;
 744         IMG_BOOL bPoweredDown;
 745
 746         pvr_lock();
 747
 748         if (!data->armed || pvr_is_disabled()) {
 749                 pvr_unlock();
 750                 return;
 751         }
 752
 753         psDevInfo->ui32TimeStamp++;
 754
 755 #if defined(NO_HARDWARE)
 756         bPoweredDown = IMG_TRUE;
 757 #else
 758         bPoweredDown = (IMG_BOOL) !SGXIsDevicePowered(psDeviceNode);
 759 #endif
 760
 761         if (bPoweredDown) {
 762                 ui32LockupCounter = 0;
 763         } else {
 764                 pvr_dev_lock();
 765                 ui32CurrentEDMTasks = OSReadHWReg(psDevInfo->pvRegsBaseKM,
 766                                                 psDevInfo->ui32EDMTaskReg0);
 767                 if (psDevInfo->ui32EDMTaskReg1 != 0)
 768                         ui32CurrentEDMTasks ^=
 769                             OSReadHWReg(psDevInfo->pvRegsBaseKM,
 770                                         psDevInfo->ui32EDMTaskReg1);
 771                 if ((ui32CurrentEDMTasks == ui32EDMTasks) &&
 772                     (psDevInfo->ui32NumResets == ui32NumResets)) {
 773                         ui32LockupCounter++;
 774                         if (ui32LockupCounter == 3) {
 775                                 ui32LockupCounter = 0;
 776                                 PVR_DPF(PVR_DBG_ERROR, "SGXOSTimer() "
 777                                         "detected SGX lockup (0x%x tasks)",
 778                                          ui32EDMTasks);
 779
 780                                 bLockup = IMG_TRUE;
 781                         }
 782                 } else {
 783                         ui32LockupCounter = 0;
 784                         ui32EDMTasks = ui32CurrentEDMTasks;
 785                         ui32NumResets = psDevInfo->ui32NumResets;
 786                 }
 787                 pvr_dev_unlock();
 788         }
 789
 790         bLockup |= cmpxchg(&sgx_reset_forced, 1, 0);
 791
 792         if (bLockup) {
 793                 struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 794                                                 psDevInfo->psSGXHostCtl;
 795                 u32 l;
 796
 797                 pvr_dev_lock();
 798                 l = readl(&psSGXHostCtl->ui32HostDetectedLockups);
 799                 l++;
 800                 writel(l, &psSGXHostCtl->ui32HostDetectedLockups);
 801
 802                 HWRecoveryResetSGX(psDeviceNode, __func__);
 803                 pvr_dev_unlock();
 804         }
 805
 806         queue_delayed_work(data->work_queue, &data->work,
 807                            msecs_to_jiffies(data->interval));
 808
 809         pvr_unlock();
 810 }
 811
 812 struct timer_work_data *
 813 SGXOSTimerInit(struct PVRSRV_DEVICE_NODE *psDeviceNode)
 814 {
 815         struct timer_work_data *data;
 816
 817         data = kzalloc(sizeof(struct timer_work_data), GFP_KERNEL);
 818         if (!data)
 819                 return NULL;
 820
 821         data->work_queue = create_workqueue("SGXOSTimer");
 822         if (!data->work_queue) {
 823                 kfree(data);
 824                 return NULL;
 825         }
 826
 827         data->interval = 150;
 828         data->psDeviceNode = psDeviceNode;
 829         INIT_DELAYED_WORK(&data->work, SGXOSTimer);
 830
 831         return data;
 832 }
 833
 834 void SGXOSTimerDeInit(struct timer_work_data *data)
 835 {
 836         data->armed = false;
 837         destroy_workqueue(data->work_queue);
 838         kfree(data);
 839 }
 840
 841 enum PVRSRV_ERROR SGXOSTimerEnable(struct timer_work_data *data)
 842 {
 843         if (!data)
 844                 return PVRSRV_ERROR_GENERIC;
 845
 846         if (queue_delayed_work(data->work_queue, &data->work,
 847                                msecs_to_jiffies(data->interval))) {
 848                 data->armed = true;
 849                 return PVRSRV_OK;
 850         }
 851
 852         return PVRSRV_ERROR_GENERIC;
 853 }
 854
 855 enum PVRSRV_ERROR SGXOSTimerCancel(struct timer_work_data *data)
 856 {
 857         if (!data)
 858                 return PVRSRV_ERROR_GENERIC;
 859
 860         data->armed = false;
 861         cancel_delayed_work(&data->work);
 862
 863         return PVRSRV_OK;
 864 }
 865
 866 int sgx_force_reset(void)
 867 {
 868         return !cmpxchg(&sgx_reset_forced, 0, 1);
 869 }
 870
 871 static IMG_BOOL SGX_ISRHandler(void *pvData)
 872 {
 873         IMG_BOOL bInterruptProcessed = IMG_FALSE;
 874
 875         {
 876                 u32 ui32EventStatus, ui32EventEnable;
 877                 u32 ui32EventClear = 0;
 878                 struct PVRSRV_DEVICE_NODE *psDeviceNode;
 879                 struct PVRSRV_SGXDEV_INFO *psDevInfo;
 880
 881                 if (pvData == NULL) {
 882                         PVR_DPF(PVR_DBG_ERROR,
 883                                  "SGX_ISRHandler: Invalid params\n");
 884                         return bInterruptProcessed;
 885                 }
 886
 887                 psDeviceNode = (struct PVRSRV_DEVICE_NODE *)pvData;
 888                 psDevInfo = (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 889
 890                 ui32EventStatus =
 891                     OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
 892                 ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM,
 893                                                 EUR_CR_EVENT_HOST_ENABLE);
 894
 895                 gui32EventStatusServicesByISR = ui32EventStatus;
 896
 897                 ui32EventStatus &= ui32EventEnable;
 898
 899                 if (ui32EventStatus & EUR_CR_EVENT_STATUS_SW_EVENT_MASK)
 900                         ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK;
 901
 902                 if (ui32EventClear) {
 903                         bInterruptProcessed = IMG_TRUE;
 904
 905                         ui32EventClear |=
 906                             EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK;
 907
 908                         OSWriteHWReg(psDevInfo->pvRegsBaseKM,
 909                                      EUR_CR_EVENT_HOST_CLEAR, ui32EventClear);
 910                 }
 911         }
 912
 913         return bInterruptProcessed;
 914 }
 915
 916 static void SGX_MISRHandler(void *pvData)
 917 {
 918         struct PVRSRV_DEVICE_NODE *psDeviceNode =
 919                         (struct PVRSRV_DEVICE_NODE *)pvData;
 920         struct PVRSRV_SGXDEV_INFO *psDevInfo =
 921                         (struct PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
 922         struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl =
 923                         psDevInfo->psSGXHostCtl;
 924         u32 l1, l2;
 925         int dev_idx;
 926         enum PVRSRV_ERROR err;
 927
 928         dev_idx = psDeviceNode->sDevId.ui32DeviceIndex;
 929
 930         pvr_dev_lock();
 931
 932         err = PVRSRVSetDevicePowerStateKM(dev_idx, PVRSRV_POWER_STATE_D0);
 933         BUG_ON(err != PVRSRV_OK);
 934
 935         l1 = readl(&psSGXHostCtl->ui32InterruptFlags);
 936         l2 = readl(&psSGXHostCtl->ui32InterruptClearFlags);
 937
 938         if ((l1 & PVRSRV_USSE_EDM_INTERRUPT_HWR) &&
 939             !(l2 & PVRSRV_USSE_EDM_INTERRUPT_HWR))
 940                 HWRecoveryResetSGX(psDeviceNode, __func__);
 941
 942         if (psDeviceNode->bReProcessDeviceCommandComplete)
 943                 SGXScheduleProcessQueues(psDeviceNode);
 944
 945         SGXTestActivePowerEvent(psDeviceNode);
 946
 947         pvr_dev_unlock();
 948 }
 949
 950 enum PVRSRV_ERROR SGXRegisterDevice(struct PVRSRV_DEVICE_NODE *psDeviceNode)
 951 {
 952         struct DEVICE_MEMORY_INFO *psDevMemoryInfo;
 953         struct DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
 954
 955         psDeviceNode->sDevId.eDeviceType = DEV_DEVICE_TYPE;
 956         psDeviceNode->sDevId.eDeviceClass = DEV_DEVICE_CLASS;
 957
 958         psDeviceNode->pfnInitDevice = DevInitSGXPart1;
 959         psDeviceNode->pfnDeInitDevice = DevDeInitSGX;
 960
 961         psDeviceNode->pfnInitDeviceCompatCheck = SGXDevInitCompatCheck;
 962
 963         psDeviceNode->pfnMMUInitialise = MMU_Initialise;
 964         psDeviceNode->pfnMMUFinalise = MMU_Finalise;
 965         psDeviceNode->pfnMMUInsertHeap = MMU_InsertHeap;
 966         psDeviceNode->pfnMMUCreate = MMU_Create;
 967         psDeviceNode->pfnMMUDelete = MMU_Delete;
 968         psDeviceNode->pfnMMUAlloc = MMU_Alloc;
 969         psDeviceNode->pfnMMUFree = MMU_Free;
 970         psDeviceNode->pfnMMUMapPages = MMU_MapPages;
 971         psDeviceNode->pfnMMUMapShadow = MMU_MapShadow;
 972         psDeviceNode->pfnMMUUnmapPages = MMU_UnmapPages;
 973         psDeviceNode->pfnMMUMapScatter = MMU_MapScatter;
 974         psDeviceNode->pfnMMUGetPhysPageAddr = MMU_GetPhysPageAddr;
 975         psDeviceNode->pfnMMUGetPDDevPAddr = MMU_GetPDDevPAddr;
 976
 977         psDeviceNode->pfnDeviceISR = SGX_ISRHandler;
 978         psDeviceNode->pfnDeviceMISR = SGX_MISRHandler;
 979
 980         psDeviceNode->pfnDeviceCommandComplete = SGXCommandComplete;
 981
 982         psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo;
 983
 984         psDevMemoryInfo->ui32AddressSpaceSizeLog2 =
 985             SGX_FEATURE_ADDRESS_SPACE_SIZE;
 986
 987         psDevMemoryInfo->ui32Flags = 0;
 988         psDevMemoryInfo->ui32HeapCount = SGX_MAX_HEAP_ID;
 989         psDevMemoryInfo->ui32SyncHeapID = SGX_SYNCINFO_HEAP_ID;
 990
 991         psDevMemoryInfo->ui32MappingHeapID = SGX_GENERAL_HEAP_ID;
 992
 993         if (OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
 994                        sizeof(struct DEVICE_MEMORY_HEAP_INFO) *
 995                        psDevMemoryInfo->ui32HeapCount,
 996                        (void **) &psDevMemoryInfo->psDeviceMemoryHeap,
 997                        NULL) != PVRSRV_OK) {
 998                 PVR_DPF(PVR_DBG_ERROR, "SGXRegisterDevice : "
 999                                 "Failed to alloc memory for "
1000                                 "struct DEVICE_MEMORY_HEAP_INFO");
1001                 return PVRSRV_ERROR_OUT_OF_MEMORY;
1002         }
1003         OSMemSet(psDevMemoryInfo->psDeviceMemoryHeap, 0,
1004                  sizeof(struct DEVICE_MEMORY_HEAP_INFO) *
1005                  psDevMemoryInfo->ui32HeapCount);
1006
1007         psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap;
1008
1009         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32HeapID =
1010             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_GENERAL_HEAP_ID);
1011         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].sDevVAddrBase.uiAddr =
1012             SGX_GENERAL_HEAP_BASE;
1013         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32HeapSize =
1014             SGX_GENERAL_HEAP_SIZE;
1015         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32Attribs =
1016             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1017             PVRSRV_HAP_SINGLE_PROCESS;
1018         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].pszName = "General";
1019         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].pszBSName = "General BS";
1020         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].DevMemHeapType =
1021             DEVICE_MEMORY_HEAP_PERCONTEXT;
1022
1023         psDeviceMemoryHeap[SGX_GENERAL_HEAP_ID].ui32DataPageSize =
1024             SGX_MMU_PAGE_SIZE;
1025
1026         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32HeapID =
1027             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID);
1028         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].sDevVAddrBase.uiAddr =
1029             SGX_TADATA_HEAP_BASE;
1030         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32HeapSize =
1031             SGX_TADATA_HEAP_SIZE;
1032         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32Attribs =
1033             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION
1034             | PVRSRV_HAP_MULTI_PROCESS;
1035         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].pszName = "TA Data";
1036         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].pszBSName = "TA Data BS";
1037         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].DevMemHeapType =
1038             DEVICE_MEMORY_HEAP_PERCONTEXT;
1039
1040         psDeviceMemoryHeap[SGX_TADATA_HEAP_ID].ui32DataPageSize =
1041             SGX_MMU_PAGE_SIZE;
1042
1043         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32HeapID =
1044             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_CODE_HEAP_ID);
1045         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].sDevVAddrBase.uiAddr =
1046             SGX_KERNEL_CODE_HEAP_BASE;
1047         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32HeapSize =
1048             SGX_KERNEL_CODE_HEAP_SIZE;
1049         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32Attribs =
1050             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1051             PVRSRV_HAP_MULTI_PROCESS;
1052         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].pszName = "Kernel Code";
1053         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].pszBSName =
1054             "Kernel Code BS";
1055         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].DevMemHeapType =
1056             DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1057
1058         psDeviceMemoryHeap[SGX_KERNEL_CODE_HEAP_ID].ui32DataPageSize =
1059             SGX_MMU_PAGE_SIZE;
1060
1061         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32HeapID =
1062             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_DATA_HEAP_ID);
1063         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].sDevVAddrBase.uiAddr =
1064             SGX_KERNEL_DATA_HEAP_BASE;
1065         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32HeapSize =
1066             SGX_KERNEL_DATA_HEAP_SIZE;
1067         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32Attribs =
1068             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1069             PVRSRV_HAP_MULTI_PROCESS;
1070         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].pszName = "KernelData";
1071         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].pszBSName = "KernelData BS";
1072         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].DevMemHeapType =
1073             DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1074
1075         psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID].ui32DataPageSize =
1076             SGX_MMU_PAGE_SIZE;
1077
1078         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32HeapID =
1079             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_PIXELSHADER_HEAP_ID);
1080         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].sDevVAddrBase.uiAddr =
1081             SGX_PIXELSHADER_HEAP_BASE;
1082         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32HeapSize =
1083             SGX_PIXELSHADER_HEAP_SIZE;
1084         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32Attribs =
1085             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1086             PVRSRV_HAP_SINGLE_PROCESS;
1087         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].pszName = "PixelShaderUSSE";
1088         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].pszBSName =
1089             "PixelShaderUSSE BS";
1090         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].DevMemHeapType =
1091             DEVICE_MEMORY_HEAP_PERCONTEXT;
1092
1093         psDeviceMemoryHeap[SGX_PIXELSHADER_HEAP_ID].ui32DataPageSize =
1094             SGX_MMU_PAGE_SIZE;
1095
1096         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32HeapID =
1097             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_VERTEXSHADER_HEAP_ID);
1098         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].sDevVAddrBase.uiAddr =
1099             SGX_VERTEXSHADER_HEAP_BASE;
1100         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32HeapSize =
1101             SGX_VERTEXSHADER_HEAP_SIZE;
1102         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32Attribs =
1103             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1104             PVRSRV_HAP_SINGLE_PROCESS;
1105         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].pszName =
1106             "VertexShaderUSSE";
1107         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].pszBSName =
1108             "VertexShaderUSSE BS";
1109         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].DevMemHeapType =
1110             DEVICE_MEMORY_HEAP_PERCONTEXT;
1111
1112         psDeviceMemoryHeap[SGX_VERTEXSHADER_HEAP_ID].ui32DataPageSize =
1113             SGX_MMU_PAGE_SIZE;
1114
1115         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32HeapID =
1116             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_PDSPIXEL_CODEDATA_HEAP_ID);
1117         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].sDevVAddrBase.uiAddr =
1118             SGX_PDSPIXEL_CODEDATA_HEAP_BASE;
1119         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32HeapSize =
1120             SGX_PDSPIXEL_CODEDATA_HEAP_SIZE;
1121         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32Attribs =
1122             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1123             PVRSRV_HAP_SINGLE_PROCESS;
1124         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].pszName =
1125             "PDSPixelCodeData";
1126         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].pszBSName =
1127             "PDSPixelCodeData BS";
1128         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].DevMemHeapType =
1129             DEVICE_MEMORY_HEAP_PERCONTEXT;
1130
1131         psDeviceMemoryHeap[SGX_PDSPIXEL_CODEDATA_HEAP_ID].ui32DataPageSize =
1132             SGX_MMU_PAGE_SIZE;
1133
1134         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32HeapID =
1135             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_PDSVERTEX_CODEDATA_HEAP_ID);
1136         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].sDevVAddrBase.
1137             uiAddr = SGX_PDSVERTEX_CODEDATA_HEAP_BASE;
1138         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32HeapSize =
1139             SGX_PDSVERTEX_CODEDATA_HEAP_SIZE;
1140         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32Attribs =
1141             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1142             PVRSRV_HAP_SINGLE_PROCESS;
1143         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].pszName =
1144             "PDSVertexCodeData";
1145         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].pszBSName =
1146             "PDSVertexCodeData BS";
1147         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].DevMemHeapType =
1148             DEVICE_MEMORY_HEAP_PERCONTEXT;
1149
1150         psDeviceMemoryHeap[SGX_PDSVERTEX_CODEDATA_HEAP_ID].ui32DataPageSize =
1151             SGX_MMU_PAGE_SIZE;
1152
1153         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32HeapID =
1154             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_SYNCINFO_HEAP_ID);
1155         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].sDevVAddrBase.uiAddr =
1156             SGX_SYNCINFO_HEAP_BASE;
1157         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32HeapSize =
1158             SGX_SYNCINFO_HEAP_SIZE;
1159
1160         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32Attribs =
1161             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1162             PVRSRV_HAP_MULTI_PROCESS;
1163         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].pszName = "CacheCoherent";
1164         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].pszBSName = "CacheCoherent BS";
1165
1166         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].DevMemHeapType =
1167             DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1168
1169         psDeviceMemoryHeap[SGX_SYNCINFO_HEAP_ID].ui32DataPageSize =
1170             SGX_MMU_PAGE_SIZE;
1171
1172         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32HeapID =
1173             HEAP_ID(PVRSRV_DEVICE_TYPE_SGX, SGX_3DPARAMETERS_HEAP_ID);
1174         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].sDevVAddrBase.uiAddr =
1175             SGX_3DPARAMETERS_HEAP_BASE;
1176         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32HeapSize =
1177             SGX_3DPARAMETERS_HEAP_SIZE;
1178         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].pszName = "3DParameters";
1179         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].pszBSName =
1180             "3DParameters BS";
1181         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32Attribs =
1182             PVRSRV_HAP_WRITECOMBINE | PVRSRV_MEM_RAM_BACKED_ALLOCATION |
1183             PVRSRV_HAP_SINGLE_PROCESS;
1184         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].DevMemHeapType =
1185             DEVICE_MEMORY_HEAP_PERCONTEXT;
1186
1187         psDeviceMemoryHeap[SGX_3DPARAMETERS_HEAP_ID].ui32DataPageSize =
1188             SGX_MMU_PAGE_SIZE;
1189
1190         return PVRSRV_OK;
1191 }
1192
1193 enum PVRSRV_ERROR SGXGetClientInfoKM(void *hDevCookie,
1194                                          struct SGX_CLIENT_INFO *psClientInfo)
1195 {
1196         struct PVRSRV_SGXDEV_INFO *psDevInfo =
1197             (struct PVRSRV_SGXDEV_INFO *)
1198                         ((struct PVRSRV_DEVICE_NODE *)hDevCookie)->pvDevice;
1199
1200         psDevInfo->ui32ClientRefCount++;
1201 #ifdef PDUMP
1202         if (psDevInfo->ui32ClientRefCount == 1)
1203                 psDevInfo->psKernelCCBInfo->ui32CCBDumpWOff = 0;
1204 #endif
1205         psClientInfo->ui32ProcessID = OSGetCurrentProcessIDKM();
1206
1207         OSMemCopy(&psClientInfo->asDevData, &psDevInfo->asSGXDevData,
1208                   sizeof(psClientInfo->asDevData));
1209
1210         return PVRSRV_OK;
1211 }
1212
1213 enum PVRSRV_ERROR SGXDevInitCompatCheck(struct PVRSRV_DEVICE_NODE *psDeviceNode)
1214 {
1215         struct PVRSRV_SGXDEV_INFO *psDevInfo;
1216         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo;
1217         enum PVRSRV_ERROR eError;
1218 #if !defined(NO_HARDWARE)
1219         u32 opts;
1220         u32 opt_mismatch;
1221         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1222 #endif
1223
1224         if (psDeviceNode->sDevId.eDeviceType != PVRSRV_DEVICE_TYPE_SGX) {
1225                 PVR_DPF(PVR_DBG_ERROR,
1226                          "SGXDevInitCompatCheck: Device not of type SGX");
1227                 eError = PVRSRV_ERROR_INVALID_PARAMS;
1228                 goto exit;
1229         }
1230         psDevInfo = psDeviceNode->pvDevice;
1231         psMemInfo = psDevInfo->psKernelSGXMiscMemInfo;
1232
1233 #if !defined(NO_HARDWARE)
1234
1235         eError = SGXGetBuildInfoKM(psDevInfo, psDeviceNode);
1236         if (eError != PVRSRV_OK) {
1237                 pr_err("pvr: unable to validate device DDK version\n");
1238                 goto exit;
1239         }
1240         psSGXFeatures =
1241             &((struct PVRSRV_SGX_MISCINFO_INFO *)(psMemInfo->pvLinAddrKM))->
1242                                                             sSGXFeatures;
1243         if ((psSGXFeatures->ui32DDKVersion !=
1244              ((PVRVERSION_MAJ << 16) | (PVRVERSION_MIN << 8) |
1245               PVRVERSION_BRANCH)) ||
1246              (psSGXFeatures->ui32DDKBuild != PVRVERSION_BUILD)) {
1247                 pr_err("pvr: incompatible driver DDK revision (%d)"
1248                         "/device DDK revision (%d).\n",
1249                          PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild);
1250                 eError = PVRSRV_ERROR_DDK_VERSION_MISMATCH;
1251                 goto exit;
1252         } else {
1253                 PVR_DPF(PVR_DBG_WARNING, "(Success) SGXInit: "
1254                                 "driver DDK (%ld) and device DDK (%ld) match",
1255                          PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild);
1256         }
1257
1258         opts = psSGXFeatures->ui32BuildOptions;
1259         opt_mismatch = opts ^ SGX_BUILD_OPTIONS;
1260         /* we support the ABIs both with and without EDM tracing option */
1261         opt_mismatch &= ~PVRSRV_USSE_EDM_STATUS_DEBUG_SET_OFFSET;
1262         if (opt_mismatch) {
1263                 if (SGX_BUILD_OPTIONS & opt_mismatch)
1264                         pr_err("pvr: mismatch in driver and microkernel build "
1265                                 "options; extra options present in driver: "
1266                                 "(0x%x)", SGX_BUILD_OPTIONS & opt_mismatch);
1267
1268                 if (opts & opt_mismatch)
1269                         pr_err("pvr: Mismatch in driver and microkernel build "
1270                                 "options; extra options present in "
1271                                 "microkernel: (0x%x)", opts & opt_mismatch);
1272                 eError = PVRSRV_ERROR_BUILD_MISMATCH;
1273                 goto exit;
1274         } else {
1275                 PVR_DPF(PVR_DBG_WARNING, "(Success) SGXInit: "
1276                                 "Driver and microkernel build options match.");
1277         }
1278
1279 #endif
1280         eError = PVRSRV_OK;
1281 exit:
1282         return eError;
1283 }
1284
1285 static
1286 enum PVRSRV_ERROR SGXGetBuildInfoKM(struct PVRSRV_SGXDEV_INFO *psDevInfo,
1287                                     struct PVRSRV_DEVICE_NODE *psDeviceNode)
1288 {
1289         enum PVRSRV_ERROR eError;
1290         struct SGXMKIF_COMMAND sCommandData;
1291         struct PVRSRV_SGX_MISCINFO_INFO *psSGXMiscInfoInt;
1292         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1293
1294         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo =
1295             psDevInfo->psKernelSGXMiscMemInfo;
1296
1297         if (!psMemInfo->pvLinAddrKM) {
1298                 PVR_DPF(PVR_DBG_ERROR, "SGXGetMiscInfoKM: Invalid address.");
1299                 return PVRSRV_ERROR_INVALID_PARAMS;
1300         }
1301         psSGXMiscInfoInt = psMemInfo->pvLinAddrKM;
1302         psSGXMiscInfoInt->ui32MiscInfoFlags &= ~PVRSRV_USSE_MISCINFO_READY;
1303         psSGXFeatures = &psSGXMiscInfoInt->sSGXFeatures;
1304
1305         OSMemSet(psMemInfo->pvLinAddrKM, 0,
1306                  sizeof(struct PVRSRV_SGX_MISCINFO_INFO));
1307
1308         sCommandData.ui32Data[1] = psMemInfo->sDevVAddr.uiAddr;
1309
1310         OSMemSet(psSGXFeatures, 0, sizeof(*psSGXFeatures));
1311
1312         mb();
1313
1314         eError = SGXScheduleCCBCommandKM(psDeviceNode,
1315                                          SGXMKIF_COMMAND_REQUEST_SGXMISCINFO,
1316                                          &sCommandData, KERNEL_ID, 0);
1317
1318         if (eError != PVRSRV_OK) {
1319                 PVR_DPF(PVR_DBG_ERROR,
1320                          "SGXGetMiscInfoKM: SGXScheduleCCBCommandKM failed.");
1321                 return eError;
1322         }
1323
1324 #if !defined(NO_HARDWARE)
1325         {
1326                 IMG_BOOL bTimeout = IMG_TRUE;
1327
1328                 LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US) {
1329                         if ((psSGXMiscInfoInt->
1330                              ui32MiscInfoFlags & PVRSRV_USSE_MISCINFO_READY) !=
1331                             0) {
1332                                 bTimeout = IMG_FALSE;
1333                                 break;
1334                         }
1335                 }
1336                 END_LOOP_UNTIL_TIMEOUT();
1337
1338                 if (bTimeout)
1339                         return PVRSRV_ERROR_TIMEOUT;
1340         }
1341 #endif
1342
1343         return PVRSRV_OK;
1344 }
1345
1346 enum PVRSRV_ERROR SGXGetMiscInfoKM(struct PVRSRV_SGXDEV_INFO *psDevInfo,
1347                                        struct SGX_MISC_INFO *psMiscInfo,
1348                                        struct PVRSRV_DEVICE_NODE *psDeviceNode)
1349 {
1350         switch (psMiscInfo->eRequest) {
1351         case SGX_MISC_INFO_REQUEST_CLOCKSPEED:
1352                 {
1353                         psMiscInfo->uData.ui32SGXClockSpeed =
1354                             psDevInfo->ui32CoreClockSpeed;
1355                         return PVRSRV_OK;
1356                 }
1357
1358         case SGX_MISC_INFO_REQUEST_SGXREV:
1359                 {
1360                         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1361                         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo =
1362                             psDevInfo->psKernelSGXMiscMemInfo;
1363
1364                         SGXGetBuildInfoKM(psDevInfo, psDeviceNode);
1365                         psSGXFeatures =
1366                             &((struct PVRSRV_SGX_MISCINFO_INFO *)(psMemInfo->
1367                                                   pvLinAddrKM))->sSGXFeatures;
1368
1369                         psMiscInfo->uData.sSGXFeatures = *psSGXFeatures;
1370
1371                         PVR_DPF(PVR_DBG_MESSAGE, "SGXGetMiscInfoKM: "
1372                                         "Core 0x%lx, sw ID 0x%lx, "
1373                                         "sw Rev 0x%lx\n",
1374                                  psSGXFeatures->ui32CoreRev,
1375                                  psSGXFeatures->ui32CoreIdSW,
1376                                  psSGXFeatures->ui32CoreRevSW);
1377                         PVR_DPF(PVR_DBG_MESSAGE, "SGXGetMiscInfoKM: "
1378                                         "DDK version 0x%lx, DDK build 0x%lx\n",
1379                                  psSGXFeatures->ui32DDKVersion,
1380                                  psSGXFeatures->ui32DDKBuild);
1381
1382                         return PVRSRV_OK;
1383                 }
1384
1385         case SGX_MISC_INFO_REQUEST_DRIVER_SGXREV:
1386                 {
1387                         struct PVRSRV_KERNEL_MEM_INFO *psMemInfo =
1388                             psDevInfo->psKernelSGXMiscMemInfo;
1389                         struct PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
1390
1391                         psSGXFeatures = &((struct PVRSRV_SGX_MISCINFO_INFO *)(
1392                                         psMemInfo->pvLinAddrKM))->sSGXFeatures;
1393
1394                         OSMemSet(psMemInfo->pvLinAddrKM, 0,
1395                                  sizeof(struct PVRSRV_SGX_MISCINFO_INFO));
1396
1397                         psSGXFeatures->ui32DDKVersion =
1398                             (PVRVERSION_MAJ << 16) |
1399                             (PVRVERSION_MIN << 8) | PVRVERSION_BRANCH;
1400                         psSGXFeatures->ui32DDKBuild = PVRVERSION_BUILD;
1401
1402                         psMiscInfo->uData.sSGXFeatures = *psSGXFeatures;
1403                         return PVRSRV_OK;
1404                 }
1405
1406         case SGX_MISC_INFO_REQUEST_SET_HWPERF_STATUS:
1407                 {
1408                         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1409                             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1410                         unsigned ui32MatchingFlags;
1411
1412                         if ((psMiscInfo->uData.ui32NewHWPerfStatus &
1413                              ~(PVRSRV_SGX_HWPERF_GRAPHICS_ON |
1414                                PVRSRV_SGX_HWPERF_MK_EXECUTION_ON)) != 0) {
1415                                 return PVRSRV_ERROR_INVALID_PARAMS;
1416                         }
1417
1418                         pvr_dev_lock();
1419                         ui32MatchingFlags = readl(&psDevInfo->
1420                                                  psSGXHostCtl->ui32HWPerfFlags);
1421                         ui32MatchingFlags &=
1422                                 psMiscInfo->uData.ui32NewHWPerfStatus;
1423                         if ((ui32MatchingFlags & PVRSRV_SGX_HWPERF_GRAPHICS_ON)
1424                             == 0UL) {
1425                                 psHWPerfCB->ui32OrdinalGRAPHICS = 0xffffffff;
1426                         }
1427                         if ((ui32MatchingFlags &
1428                              PVRSRV_SGX_HWPERF_MK_EXECUTION_ON) == 0UL) {
1429                                 psHWPerfCB->ui32OrdinalMK_EXECUTION =
1430                                     0xffffffffUL;
1431                         }
1432
1433
1434                         writel(psMiscInfo->uData.ui32NewHWPerfStatus,
1435                                 &psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1436                         pvr_dev_unlock();
1437 #if defined(PDUMP)
1438                         PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
1439                                               "SGX ukernel HWPerf status %u\n",
1440                                               readl(&psDevInfo->psSGXHostCtl->
1441                                                               ui32HWPerfFlags));
1442                         PDUMPMEM(NULL, psDevInfo->psKernelSGXHostCtlMemInfo,
1443                                  offsetof(struct SGXMKIF_HOST_CTL,
1444                                           ui32HWPerfFlags),
1445                                  sizeof(psDevInfo->psSGXHostCtl->
1446                                         ui32HWPerfFlags),
1447                                  PDUMP_FLAGS_CONTINUOUS,
1448                                  MAKEUNIQUETAG(psDevInfo->
1449                                                psKernelSGXHostCtlMemInfo));
1450 #endif
1451
1452                         return PVRSRV_OK;
1453                 }
1454         case SGX_MISC_INFO_REQUEST_HWPERF_CB_ON:
1455                 {
1456
1457                         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1458                             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1459                         u32 l;
1460
1461                         psHWPerfCB->ui32OrdinalGRAPHICS = 0xffffffffUL;
1462
1463                         pvr_dev_lock();;
1464                         l = readl(&psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1465                         l |= PVRSRV_SGX_HWPERF_GRAPHICS_ON;
1466                         writel(l, &psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1467                         pvr_dev_unlock();
1468
1469                         return PVRSRV_OK;
1470                 }
1471         case SGX_MISC_INFO_REQUEST_HWPERF_CB_OFF:
1472                 {
1473                         pvr_dev_lock();
1474                         writel(0, &psDevInfo->psSGXHostCtl->ui32HWPerfFlags);
1475                         pvr_dev_unlock();
1476
1477                         return PVRSRV_OK;
1478                 }
1479         case SGX_MISC_INFO_REQUEST_HWPERF_RETRIEVE_CB:
1480                 {
1481                         struct SGX_MISC_INFO_HWPERF_RETRIEVE_CB *psRetrieve =
1482                             &psMiscInfo->uData.sRetrieveCB;
1483                         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1484                             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1485                         unsigned i;
1486
1487                         for (i = 0;
1488                              psHWPerfCB->ui32Woff != psHWPerfCB->ui32Roff
1489                              && i < psRetrieve->ui32ArraySize; i++) {
1490                                 struct SGXMKIF_HWPERF_CB_ENTRY *psData =
1491                                     &psHWPerfCB->psHWPerfCBData[psHWPerfCB->
1492                                                                 ui32Roff];
1493
1494                                 psRetrieve->psHWPerfData[i].ui32FrameNo =
1495                                     psData->ui32FrameNo;
1496                                 psRetrieve->psHWPerfData[i].ui32Type =
1497                                     (psData->ui32Type &
1498                                      PVRSRV_SGX_HWPERF_TYPE_OP_MASK);
1499                                 psRetrieve->psHWPerfData[i].ui32StartTime =
1500                                     psData->ui32Time;
1501                                 psRetrieve->psHWPerfData[i].ui32StartTimeWraps =
1502                                     psData->ui32TimeWraps;
1503                                 psRetrieve->psHWPerfData[i].ui32EndTime =
1504                                     psData->ui32Time;
1505                                 psRetrieve->psHWPerfData[i].ui32EndTimeWraps =
1506                                     psData->ui32TimeWraps;
1507                                 psRetrieve->psHWPerfData[i].ui32ClockSpeed =
1508                                     psDevInfo->ui32CoreClockSpeed;
1509                                 psRetrieve->psHWPerfData[i].ui32TimeMax =
1510                                     psDevInfo->ui32uKernelTimerClock;
1511                                 psHWPerfCB->ui32Roff =
1512                                     (psHWPerfCB->ui32Roff + 1) &
1513                                     (SGXMKIF_HWPERF_CB_SIZE - 1);
1514                         }
1515                         psRetrieve->ui32DataCount = i;
1516                         psRetrieve->ui32Time = OSClockus();
1517                         return PVRSRV_OK;
1518                 }
1519         default:
1520                 {
1521                         return PVRSRV_ERROR_INVALID_PARAMS;
1522                 }
1523         }
1524 }
1525
1526
1527
1528 static bool sgxps_active;
1529 static unsigned long sgxps_timeout;
1530
1531 IMG_BOOL isSGXPerfServerActive(void)
1532 {
1533         if (!sgxps_active)
1534                 return 0;
1535
1536         if (time_before_eq((unsigned long)OSClockus(), sgxps_timeout))
1537                 return 1;
1538
1539         sgxps_active = false;
1540         PVR_DPF(DBGPRIV_WARNING, "pvr: perf server inactive\n");
1541
1542         return 0;
1543 }
1544
1545
1546 void SGXPerfServerMonitor(u32 u32TimeStamp)
1547 {
1548         if (!sgxps_active) {
1549                 PVR_DPF(DBGPRIV_WARNING, "pvr: perf server active\n");
1550                 sgxps_active = true;
1551         }
1552
1553         /* turn off after 1 second of inactivity */
1554         sgxps_timeout = u32TimeStamp + 1000000;
1555 }
1556
1557
1558 enum PVRSRV_ERROR SGXReadDiffCountersKM(void *hDevHandle, u32 ui32Reg,
1559                                    u32 *pui32Old, IMG_BOOL bNew, u32 ui32New,
1560                                    u32 ui32NewReset, u32 ui32CountersReg,
1561                                    u32 *pui32Time, IMG_BOOL *pbActive,
1562                                    struct PVRSRV_SGXDEV_DIFF_INFO *psDiffs)
1563 {
1564         struct SYS_DATA *psSysData;
1565         struct PVRSRV_POWER_DEV *psPowerDevice;
1566         IMG_BOOL bPowered = IMG_FALSE;
1567         struct PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
1568         struct PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1569
1570         if (bNew)
1571                 psDevInfo->ui32HWGroupRequested = ui32New;
1572         psDevInfo->ui32HWReset |= ui32NewReset;
1573
1574         if (SysAcquireData(&psSysData) != PVRSRV_OK)
1575                 return PVRSRV_ERROR_GENERIC;
1576
1577         psPowerDevice = psSysData->psPowerDeviceList;
1578         while (psPowerDevice) {
1579                 if (psPowerDevice->ui32DeviceIndex ==
1580                     psDeviceNode->sDevId.ui32DeviceIndex) {
1581                         bPowered =
1582                             (IMG_BOOL)(psPowerDevice->eCurrentPowerState ==
1583                                         PVRSRV_POWER_STATE_D0);
1584                         break;
1585                 }
1586
1587                 psPowerDevice = psPowerDevice->psNext;
1588         }
1589
1590         *pbActive = bPowered;
1591
1592         pvr_dev_lock();
1593
1594         {
1595                 struct PVRSRV_SGXDEV_DIFF_INFO sNew,
1596                                                *psPrev = &psDevInfo->sDiffInfo;
1597                 u32 i;
1598
1599                 sNew.ui32Time[0] = OSClockus();
1600                 *pui32Time = sNew.ui32Time[0];
1601                 if (sNew.ui32Time[0] != psPrev->ui32Time[0] && bPowered) {
1602
1603                         SGXPerfServerMonitor(*pui32Time);
1604
1605                         *pui32Old =
1606                             OSReadHWReg(psDevInfo->pvRegsBaseKM, ui32Reg);
1607
1608                         for (i = 0; i < PVRSRV_SGX_DIFF_NUM_COUNTERS; ++i) {
1609                                 sNew.aui32Counters[i] =
1610                                     OSReadHWReg(psDevInfo->pvRegsBaseKM,
1611                                                 ui32CountersReg + (i * 4));
1612                         }
1613
1614                         if (psDevInfo->ui32HWGroupRequested != *pui32Old) {
1615                                 if (psDevInfo->ui32HWReset != 0) {
1616                                         OSWriteHWReg(psDevInfo->pvRegsBaseKM,
1617                                                      ui32Reg,
1618                                                      psDevInfo->
1619                                                      ui32HWGroupRequested |
1620                                                      psDevInfo->ui32HWReset);
1621                                         psDevInfo->ui32HWReset = 0;
1622                                 }
1623                                 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Reg,
1624                                              psDevInfo->ui32HWGroupRequested);
1625                         }
1626
1627                         sNew.ui32Marker[0] = psDevInfo->ui32KickTACounter;
1628                         sNew.ui32Marker[1] = psDevInfo->ui32KickTARenderCounter;
1629
1630                         sNew.ui32Time[1] = readl(
1631                                 &psDevInfo->psSGXHostCtl->ui32TimeWraps);
1632
1633                         for (i = 0; i < PVRSRV_SGX_DIFF_NUM_COUNTERS; ++i) {
1634                                 psDiffs->aui32Counters[i] =
1635                                     sNew.aui32Counters[i] -
1636                                     psPrev->aui32Counters[i];
1637                         }
1638
1639                         psDiffs->ui32Marker[0] =
1640                             sNew.ui32Marker[0] - psPrev->ui32Marker[0];
1641                         psDiffs->ui32Marker[1] =
1642                             sNew.ui32Marker[1] - psPrev->ui32Marker[1];
1643
1644                         psDiffs->ui32Time[0] =
1645                             sNew.ui32Time[0] - psPrev->ui32Time[0];
1646                         psDiffs->ui32Time[1] =
1647                             sNew.ui32Time[1] - psPrev->ui32Time[1];
1648
1649                         *psPrev = sNew;
1650                 } else {
1651                         for (i = 0; i < PVRSRV_SGX_DIFF_NUM_COUNTERS; ++i)
1652                                 psDiffs->aui32Counters[i] = 0;
1653
1654                         psDiffs->ui32Marker[0] = 0;
1655                         psDiffs->ui32Marker[1] = 0;
1656
1657                         psDiffs->ui32Time[0] = 0;
1658                         psDiffs->ui32Time[1] = 0;
1659                 }
1660         }
1661
1662         SGXTestActivePowerEvent(psDeviceNode);
1663
1664         pvr_dev_unlock();
1665
1666         return PVRSRV_OK;
1667 }
1668
1669 enum PVRSRV_ERROR SGXReadHWPerfCBKM(void *hDevHandle, u32 ui32ArraySize,
1670                         struct PVRSRV_SGX_HWPERF_CB_ENTRY *psClientHWPerfEntry,
1671                         u32 *pui32DataCount, u32 *pui32ClockSpeed,
1672                         u32 *pui32HostTimeStamp)
1673 {
1674         enum PVRSRV_ERROR eError = PVRSRV_OK;
1675         struct PVRSRV_DEVICE_NODE *psDeviceNode = hDevHandle;
1676         struct PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1677         struct SGXMKIF_HWPERF_CB *psHWPerfCB =
1678             psDevInfo->psKernelHWPerfCBMemInfo->pvLinAddrKM;
1679         unsigned i;
1680
1681         for (i = 0;
1682              psHWPerfCB->ui32Woff != psHWPerfCB->ui32Roff && i < ui32ArraySize;
1683              i++) {
1684                 struct SGXMKIF_HWPERF_CB_ENTRY *psMKPerfEntry =
1685                     &psHWPerfCB->psHWPerfCBData[psHWPerfCB->ui32Roff];
1686
1687                 psClientHWPerfEntry[i].ui32FrameNo = psMKPerfEntry->ui32FrameNo;
1688                 psClientHWPerfEntry[i].ui32Type = psMKPerfEntry->ui32Type;
1689                 psClientHWPerfEntry[i].ui32Ordinal = psMKPerfEntry->ui32Ordinal;
1690                 psClientHWPerfEntry[i].ui32Clocksx16 =
1691                     SGXConvertTimeStamp(psDevInfo, psMKPerfEntry->ui32TimeWraps,
1692                                         psMKPerfEntry->ui32Time);
1693                 OSMemCopy(&psClientHWPerfEntry[i].ui32Counters[0],
1694                           &psMKPerfEntry->ui32Counters[0],
1695                           sizeof(psMKPerfEntry->ui32Counters));
1696
1697                 psHWPerfCB->ui32Roff =
1698                     (psHWPerfCB->ui32Roff + 1) & (SGXMKIF_HWPERF_CB_SIZE - 1);
1699         }
1700
1701         *pui32DataCount = i;
1702         *pui32ClockSpeed = psDevInfo->ui32CoreClockSpeed;
1703         *pui32HostTimeStamp = OSClockus();
1704
1705         return eError;
1706 }