pvr/sgxinfo.h

   1 /**********************************************************************
   2  *
   3  * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful but, except
  10  * as otherwise stated in writing, without any warranty; without even the
  11  * implied warranty of merchantability or fitness for a particular purpose.
  12  * See the GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * Imagination Technologies Ltd. <gpl-support@imgtec.com>
  23  * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
  24  *
  25  ******************************************************************************/
  26
  27 #if !defined(__SGXINFO_H__)
  28 #define __SGXINFO_H__
  29
  30 #include "sgxscript.h"
  31
  32 #include "servicesint.h"
  33
  34 #include "services.h"
  35 #include "sgxapi_km.h"
  36
  37 #define SGX_MP_CORE_SELECT(x, i)        (x)
  38
  39 #define SGX_MAX_DEV_DATA                24
  40 #define SGX_MAX_INIT_MEM_HANDLES        16
  41
  42 #define SGX_BIF_DIR_LIST_INDEX_EDM      0
  43
  44 struct SGX_BRIDGE_INFO_FOR_SRVINIT {
  45         struct IMG_DEV_PHYADDR sPDDevPAddr;
  46         struct PVRSRV_HEAP_INFO asHeapInfo[PVRSRV_MAX_CLIENT_HEAPS];
  47 };
  48
  49 struct SGX_BRIDGE_INIT_INFO {
  50         void *hKernelCCBMemInfo;
  51         void *hKernelCCBCtlMemInfo;
  52         void *hKernelCCBEventKickerMemInfo;
  53         void *hKernelSGXHostCtlMemInfo;
  54         void *hKernelSGXTA3DCtlMemInfo;
  55         void *hKernelSGXMiscMemInfo;
  56         u32 ui32HostKickAddress;
  57         u32 ui32GetMiscInfoAddress;
  58         void *hKernelHWPerfCBMemInfo;
  59 #if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
  60         void *hKernelEDMStatusBufferMemInfo;
  61 #endif
  62
  63         u32 ui32EDMTaskReg0;
  64         u32 ui32EDMTaskReg1;
  65
  66         u32 ui32ClkGateStatusReg;
  67         u32 ui32ClkGateStatusMask;
  68
  69         u32 ui32CacheControl;
  70
  71         u32 asInitDevData[SGX_MAX_DEV_DATA];
  72         void *asInitMemHandles[SGX_MAX_INIT_MEM_HANDLES];
  73
  74         struct SGX_INIT_SCRIPTS sScripts;
  75
  76         u32 state_buf_ofs;
  77 };
  78
  79 struct SGXMKIF_COMMAND {
  80         u32 ui32ServiceAddress;
  81         u32 ui32Data[3];
  82 };
  83
  84 struct PVRSRV_SGX_KERNEL_CCB {
  85         struct SGXMKIF_COMMAND asCommands[256];
  86 };
  87
  88 struct PVRSRV_SGX_CCB_CTL {
  89         u32 ui32WriteOffset;
  90         u32 ui32ReadOffset;
  91 };
  92
  93 #define SGX_AUXCCBFLAGS_SHARED                                  0x00000001
  94
  95 enum SGXMKIF_COMMAND_TYPE {
  96         SGXMKIF_COMMAND_EDM_KICK = 0,
  97         SGXMKIF_COMMAND_VIDEO_KICK = 1,
  98         SGXMKIF_COMMAND_REQUEST_SGXMISCINFO = 2,
  99
 100         SGXMKIF_COMMAND_FORCE_I32 = -1,
 101
 102 };
 103
 104 #define PVRSRV_CCBFLAGS_RASTERCMD                       0x1
 105 #define PVRSRV_CCBFLAGS_TRANSFERCMD                     0x2
 106 #define PVRSRV_CCBFLAGS_PROCESS_QUEUESCMD               0x3
 107 #define PVRSRV_CCBFLAGS_POWERCMD                        0x5
 108
 109 #define PVRSRV_POWERCMD_POWEROFF                        0x1
 110 #define PVRSRV_POWERCMD_IDLE                            0x2
 111
 112 #define SGX_BIF_INVALIDATE_PTCACHE                      0x1
 113 #define SGX_BIF_INVALIDATE_PDCACHE                      0x2
 114
 115 struct SGXMKIF_HWDEVICE_SYNC_LIST {
 116         struct IMG_DEV_VIRTADDR sAccessDevAddr;
 117         u32 ui32NumSyncObjects;
 118
 119         struct PVRSRV_DEVICE_SYNC_OBJECT asSyncData[1];
 120 };
 121
 122 struct SGX_DEVICE_SYNC_LIST {
 123         struct SGXMKIF_HWDEVICE_SYNC_LIST *psHWDeviceSyncList;
 124
 125         void *hKernelHWSyncListMemInfo;
 126         struct PVRSRV_CLIENT_MEM_INFO *psHWDeviceSyncListClientMemInfo;
 127         struct PVRSRV_CLIENT_MEM_INFO *psAccessResourceClientMemInfo;
 128
 129         volatile u32 *pui32Lock;
 130
 131         struct SGX_DEVICE_SYNC_LIST *psNext;
 132
 133         u32 ui32NumSyncObjects;
 134         void *ahSyncHandles[1];
 135 };
 136
 137 struct SGX_INTERNEL_STATUS_UPDATE {
 138         struct CTL_STATUS sCtlStatus;
 139         void *hKernelMemInfo;
 140         /* pdump specific - required? */
 141         u32 ui32LastStatusUpdateDumpVal;
 142 };
 143
 144 struct SGX_CCB_KICK {
 145         enum SGXMKIF_COMMAND_TYPE eCommand;
 146         struct SGXMKIF_COMMAND sCommand;
 147         void *hCCBKernelMemInfo;
 148
 149         u32 ui32NumDstSyncObjects;
 150         void *hKernelHWSyncListMemInfo;
 151         void *sDstSyncHandle;
 152
 153         u32 ui32NumTAStatusVals;
 154         u32 ui32Num3DStatusVals;
 155
 156         void *ahTAStatusSyncInfo[SGX_MAX_TA_STATUS_VALS];
 157         void *ah3DStatusSyncInfo[SGX_MAX_3D_STATUS_VALS];
 158
 159         IMG_BOOL bFirstKickOrResume;
 160 #if (defined(NO_HARDWARE) || defined(PDUMP))
 161         IMG_BOOL bTerminateOrAbort;
 162 #endif
 163         IMG_BOOL bKickRender;
 164
 165         u32 ui32CCBOffset;
 166
 167         u32 ui32NumSrcSyncs;
 168         void *ahSrcKernelSyncInfo[SGX_MAX_SRC_SYNCS];
 169
 170         IMG_BOOL bTADependency;
 171         void *hTA3DSyncInfo;
 172
 173         void *hTASyncInfo;
 174         void *h3DSyncInfo;
 175 #if defined(PDUMP)
 176         u32 ui32CCBDumpWOff;
 177 #endif
 178 #if defined(NO_HARDWARE)
 179         u32 ui32WriteOpsPendingVal;
 180 #endif
 181 };
 182
 183 #define SGX_KERNEL_USE_CODE_BASE_INDEX          15
 184
 185 struct SGXMKIF_HOST_CTL {
 186
 187         u32 ui32PowerStatus;
 188         u32 ui32uKernelDetectedLockups;
 189         u32 ui32HostDetectedLockups;
 190         u32 ui32HWRecoverySampleRate;
 191         u32 ui32ActivePowManSampleRate;
 192         u32 ui32InterruptFlags;
 193         u32 ui32InterruptClearFlags;
 194
 195         u32 ui32ResManFlags;
 196         struct IMG_DEV_VIRTADDR sResManCleanupData;
 197
 198         u32 ui32NumActivePowerEvents;
 199
 200         u32 ui32HWPerfFlags;
 201
 202 #if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
 203         /* !< See SGXMK_STATUS_BUFFER */
 204         struct IMG_DEV_VIRTADDR sEDMStatusBuffer;
 205 #endif
 206
 207         /*< to count time wraps in the Timer task */
 208         u32 ui32TimeWraps;
 209
 210         u32 render_state_buf_ta_handle;
 211         u32 render_state_buf_3d_handle;
 212 };
 213
 214 struct SGX_CLIENT_INFO {
 215         u32 ui32ProcessID;
 216         void *pvProcess;
 217         struct PVRSRV_MISC_INFO sMiscInfo;
 218
 219         u32 asDevData[SGX_MAX_DEV_DATA];
 220
 221 };
 222
 223 struct SGX_INTERNAL_DEVINFO {
 224         u32 ui32Flags;
 225         void *hHostCtlKernelMemInfoHandle;
 226         IMG_BOOL bForcePTOff;
 227 };
 228
 229 #define SGXTQ_MAX_STATUS                (SGX_MAX_TRANSFER_STATUS_VALS + 2)
 230
 231 #define SGXMKIF_TQFLAGS_NOSYNCUPDATE                            0x00000001
 232 #define SGXMKIF_TQFLAGS_KEEPPENDING                             0x00000002
 233 #define SGXMKIF_TQFLAGS_TATQ_SYNC                               0x00000004
 234 #define SGXMKIF_TQFLAGS_3DTQ_SYNC                               0x00000008
 235 struct SGXMKIF_CMDTA_SHARED {
 236         u32 ui32NumTAStatusVals;
 237         u32 ui32Num3DStatusVals;
 238
 239         u32 ui32TATQSyncWriteOpsPendingVal;
 240         struct IMG_DEV_VIRTADDR sTATQSyncWriteOpsCompleteDevVAddr;
 241         u32 ui32TATQSyncReadOpsPendingVal;
 242         struct IMG_DEV_VIRTADDR sTATQSyncReadOpsCompleteDevVAddr;
 243
 244         u32 ui323DTQSyncWriteOpsPendingVal;
 245         struct IMG_DEV_VIRTADDR s3DTQSyncWriteOpsCompleteDevVAddr;
 246         u32 ui323DTQSyncReadOpsPendingVal;
 247         struct IMG_DEV_VIRTADDR s3DTQSyncReadOpsCompleteDevVAddr;
 248
 249         u32 ui32NumSrcSyncs;
 250         struct PVRSRV_DEVICE_SYNC_OBJECT asSrcSyncs[SGX_MAX_SRC_SYNCS];
 251
 252         struct CTL_STATUS sCtlTAStatusInfo[SGX_MAX_TA_STATUS_VALS];
 253         struct CTL_STATUS sCtl3DStatusInfo[SGX_MAX_3D_STATUS_VALS];
 254
 255         struct PVRSRV_DEVICE_SYNC_OBJECT sTA3DDependency;
 256
 257 };
 258
 259 struct SGXMKIF_TRANSFERCMD_SHARED {
 260
 261         u32 ui32SrcReadOpPendingVal;
 262         struct IMG_DEV_VIRTADDR sSrcReadOpsCompleteDevAddr;
 263
 264         u32 ui32SrcWriteOpPendingVal;
 265         struct IMG_DEV_VIRTADDR sSrcWriteOpsCompleteDevAddr;
 266
 267         u32 ui32DstReadOpPendingVal;
 268         struct IMG_DEV_VIRTADDR sDstReadOpsCompleteDevAddr;
 269
 270         u32 ui32DstWriteOpPendingVal;
 271         struct IMG_DEV_VIRTADDR sDstWriteOpsCompleteDevAddr;
 272
 273         u32 ui32TASyncWriteOpsPendingVal;
 274         struct IMG_DEV_VIRTADDR sTASyncWriteOpsCompleteDevVAddr;
 275         u32 ui32TASyncReadOpsPendingVal;
 276         struct IMG_DEV_VIRTADDR sTASyncReadOpsCompleteDevVAddr;
 277
 278         u32 ui323DSyncWriteOpsPendingVal;
 279         struct IMG_DEV_VIRTADDR s3DSyncWriteOpsCompleteDevVAddr;
 280         u32 ui323DSyncReadOpsPendingVal;
 281         struct IMG_DEV_VIRTADDR s3DSyncReadOpsCompleteDevVAddr;
 282
 283         u32 ui32NumStatusVals;
 284         struct CTL_STATUS sCtlStatusInfo[SGXTQ_MAX_STATUS];
 285 };
 286
 287 struct PVRSRV_TRANSFER_SGX_KICK {
 288         void *hCCBMemInfo;
 289         u32 ui32SharedCmdCCBOffset;
 290
 291         struct IMG_DEV_VIRTADDR sHWTransferContextDevVAddr;
 292
 293         void *hTASyncInfo;
 294         void *h3DSyncInfo;
 295
 296         u32 ui32NumSrcSync;
 297         void *ahSrcSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
 298
 299         u32 ui32NumDstSync;
 300         void *ahDstSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
 301
 302         u32 ui32Flags;
 303
 304         u32 ui32PDumpFlags;
 305 #if defined(PDUMP)
 306         u32 ui32CCBDumpWOff;
 307 #endif
 308 };
 309
 310 #define PVRSRV_SGX_DIFF_NUM_COUNTERS    9
 311
 312 struct PVRSRV_SGXDEV_DIFF_INFO {
 313         u32 aui32Counters[PVRSRV_SGX_DIFF_NUM_COUNTERS];
 314         u32 ui32Time[2];
 315         u32 ui32Marker[2];
 316 };
 317
 318 #define SGXMKIF_HWPERF_CB_SIZE                                  0x100
 319
 320 struct SGXMKIF_HWPERF_CB_ENTRY {
 321         u32 ui32FrameNo;
 322         u32 ui32Type;
 323         u32 ui32Ordinal;
 324         u32 ui32TimeWraps;
 325         u32 ui32Time;
 326         u32 ui32Counters[PVRSRV_SGX_HWPERF_NUM_COUNTERS];
 327 };
 328
 329 struct SGXMKIF_HWPERF_CB {
 330         u32 ui32Woff;
 331         u32 ui32Roff;
 332         u32 ui32OrdinalGRAPHICS;
 333         u32 ui32OrdinalMK_EXECUTION;
 334         struct SGXMKIF_HWPERF_CB_ENTRY psHWPerfCBData[SGXMKIF_HWPERF_CB_SIZE];
 335 };
 336
 337 struct PVRSRV_SGX_MISCINFO_INFO {
 338         u32 ui32MiscInfoFlags;
 339         struct PVRSRV_SGX_MISCINFO_FEATURES sSGXFeatures;
 340 };
 341
 342 #endif