e62674599b3d137743cf587e25a275582fcbac34
[pandora-kernel.git] / include / video / omapdss.h
1 /*
2  * Copyright (C) 2008 Nokia Corporation
3  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License version 2 as published by
7  * the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
20
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/platform_device.h>
25 #include <asm/atomic.h>
26
27 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
28 #define DISPC_IRQ_VSYNC                 (1 << 1)
29 #define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
30 #define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
31 #define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
32 #define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
33 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
34 #define DISPC_IRQ_GFX_END_WIN           (1 << 7)
35 #define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
36 #define DISPC_IRQ_OCP_ERR               (1 << 9)
37 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
38 #define DISPC_IRQ_VID1_END_WIN          (1 << 11)
39 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
40 #define DISPC_IRQ_VID2_END_WIN          (1 << 13)
41 #define DISPC_IRQ_SYNC_LOST             (1 << 14)
42 #define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
43 #define DISPC_IRQ_WAKEUP                (1 << 16)
44 #define DISPC_IRQ_SYNC_LOST2            (1 << 17)
45 #define DISPC_IRQ_VSYNC2                (1 << 18)
46 #define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
47 #define DISPC_IRQ_FRAMEDONE2            (1 << 22)
48
49 struct omap_dss_device;
50 struct omap_overlay_manager;
51
52 enum omap_display_type {
53         OMAP_DISPLAY_TYPE_NONE          = 0,
54         OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
55         OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
56         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
57         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
58         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
59         OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
60 };
61
62 enum omap_plane {
63         OMAP_DSS_GFX    = 0,
64         OMAP_DSS_VIDEO1 = 1,
65         OMAP_DSS_VIDEO2 = 2
66 };
67
68 enum omap_channel {
69         OMAP_DSS_CHANNEL_LCD    = 0,
70         OMAP_DSS_CHANNEL_DIGIT  = 1,
71         OMAP_DSS_CHANNEL_LCD2   = 2,
72 };
73
74 enum omap_color_mode {
75         OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
76         OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
77         OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
78         OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
79         OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
80         OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
81         OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
82         OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
83         OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
84         OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
85         OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
86         OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
87         OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
88         OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
89 };
90
91 enum omap_lcd_display_type {
92         OMAP_DSS_LCD_DISPLAY_STN,
93         OMAP_DSS_LCD_DISPLAY_TFT,
94 };
95
96 enum omap_dss_load_mode {
97         OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
98         OMAP_DSS_LOAD_CLUT_ONLY         = 1,
99         OMAP_DSS_LOAD_FRAME_ONLY        = 2,
100         OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
101 };
102
103 enum omap_dss_trans_key_type {
104         OMAP_DSS_COLOR_KEY_GFX_DST = 0,
105         OMAP_DSS_COLOR_KEY_VID_SRC = 1,
106 };
107
108 enum omap_rfbi_te_mode {
109         OMAP_DSS_RFBI_TE_MODE_1 = 1,
110         OMAP_DSS_RFBI_TE_MODE_2 = 2,
111 };
112
113 enum omap_panel_config {
114         OMAP_DSS_LCD_IVS                = 1<<0,
115         OMAP_DSS_LCD_IHS                = 1<<1,
116         OMAP_DSS_LCD_IPC                = 1<<2,
117         OMAP_DSS_LCD_IEO                = 1<<3,
118         OMAP_DSS_LCD_RF                 = 1<<4,
119         OMAP_DSS_LCD_ONOFF              = 1<<5,
120
121         OMAP_DSS_LCD_TFT                = 1<<20,
122 };
123
124 enum omap_dss_venc_type {
125         OMAP_DSS_VENC_TYPE_COMPOSITE,
126         OMAP_DSS_VENC_TYPE_SVIDEO,
127 };
128
129 enum omap_display_caps {
130         OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
131         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
132 };
133
134 enum omap_dss_update_mode {
135         OMAP_DSS_UPDATE_DISABLED = 0,
136         OMAP_DSS_UPDATE_AUTO,
137         OMAP_DSS_UPDATE_MANUAL,
138 };
139
140 enum omap_dss_display_state {
141         OMAP_DSS_DISPLAY_DISABLED = 0,
142         OMAP_DSS_DISPLAY_ACTIVE,
143         OMAP_DSS_DISPLAY_SUSPENDED,
144 };
145
146 /* XXX perhaps this should be removed */
147 enum omap_dss_overlay_managers {
148         OMAP_DSS_OVL_MGR_LCD,
149         OMAP_DSS_OVL_MGR_TV,
150         OMAP_DSS_OVL_MGR_LCD2,
151 };
152
153 enum omap_dss_rotation_type {
154         OMAP_DSS_ROT_DMA = 0,
155         OMAP_DSS_ROT_VRFB = 1,
156 };
157
158 /* clockwise rotation angle */
159 enum omap_dss_rotation_angle {
160         OMAP_DSS_ROT_0   = 0,
161         OMAP_DSS_ROT_90  = 1,
162         OMAP_DSS_ROT_180 = 2,
163         OMAP_DSS_ROT_270 = 3,
164 };
165
166 enum omap_overlay_caps {
167         OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
168         OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
169 };
170
171 enum omap_overlay_manager_caps {
172         OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
173 };
174
175 enum omap_dss_clk_source {
176         OMAP_DSS_CLK_SRC_FCK = 0,               /* OMAP2/3: DSS1_ALWON_FCLK
177                                                  * OMAP4: DSS_FCLK */
178         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,   /* OMAP3: DSI1_PLL_FCLK
179                                                  * OMAP4: PLL1_CLK1 */
180         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,     /* OMAP3: DSI2_PLL_FCLK
181                                                  * OMAP4: PLL1_CLK2 */
182         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,  /* OMAP4: PLL2_CLK1 */
183         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,    /* OMAP4: PLL2_CLK2 */
184 };
185
186 /* RFBI */
187
188 struct rfbi_timings {
189         int cs_on_time;
190         int cs_off_time;
191         int we_on_time;
192         int we_off_time;
193         int re_on_time;
194         int re_off_time;
195         int we_cycle_time;
196         int re_cycle_time;
197         int cs_pulse_width;
198         int access_time;
199
200         int clk_div;
201
202         u32 tim[5];             /* set by rfbi_convert_timings() */
203
204         int converted;
205 };
206
207 void omap_rfbi_write_command(const void *buf, u32 len);
208 void omap_rfbi_read_data(void *buf, u32 len);
209 void omap_rfbi_write_data(const void *buf, u32 len);
210 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
211                 u16 x, u16 y,
212                 u16 w, u16 h);
213 int omap_rfbi_enable_te(bool enable, unsigned line);
214 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
215                              unsigned hs_pulse_time, unsigned vs_pulse_time,
216                              int hs_pol_inv, int vs_pol_inv, int extif_div);
217 void rfbi_bus_lock(void);
218 void rfbi_bus_unlock(void);
219
220 /* DSI */
221 void dsi_bus_lock(struct omap_dss_device *dssdev);
222 void dsi_bus_unlock(struct omap_dss_device *dssdev);
223 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
224                 int len);
225 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
226                 u8 dcs_cmd);
227 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
228                 u8 param);
229 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
230                 u8 *data, int len);
231 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
232                 u8 *buf, int buflen);
233 int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
234                 u8 *data);
235 int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
236                 u8 *data1, u8 *data2);
237 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
238                 u16 len);
239 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
240 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
241
242 /* Board specific data */
243 struct omap_dss_board_info {
244         int (*get_last_off_on_transaction_id)(struct device *dev);
245         int num_devices;
246         struct omap_dss_device **devices;
247         struct omap_dss_device *default_device;
248         void (*dsi_mux_pads)(bool enable);
249 };
250
251 #if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
252 /* Init with the board info */
253 extern int omap_display_init(struct omap_dss_board_info *board_data);
254 #else
255 static inline int omap_display_init(struct omap_dss_board_info *board_data)
256 {
257         return 0;
258 }
259 #endif
260
261 struct omap_display_platform_data {
262         struct omap_dss_board_info *board_data;
263         /* TODO: Additional members to be added when PM is considered */
264
265         bool (*opt_clock_available)(const char *clk_role);
266 };
267
268 struct omap_video_timings {
269         /* Unit: pixels */
270         u16 x_res;
271         /* Unit: pixels */
272         u16 y_res;
273         /* Unit: KHz */
274         u32 pixel_clock;
275         /* Unit: pixel clocks */
276         u16 hsw;        /* Horizontal synchronization pulse width */
277         /* Unit: pixel clocks */
278         u16 hfp;        /* Horizontal front porch */
279         /* Unit: pixel clocks */
280         u16 hbp;        /* Horizontal back porch */
281         /* Unit: line clocks */
282         u16 vsw;        /* Vertical synchronization pulse width */
283         /* Unit: line clocks */
284         u16 vfp;        /* Vertical front porch */
285         /* Unit: line clocks */
286         u16 vbp;        /* Vertical back porch */
287 };
288
289 #ifdef CONFIG_OMAP2_DSS_VENC
290 /* Hardcoded timings for tv modes. Venc only uses these to
291  * identify the mode, and does not actually use the configs
292  * itself. However, the configs should be something that
293  * a normal monitor can also show */
294 extern const struct omap_video_timings omap_dss_pal_timings;
295 extern const struct omap_video_timings omap_dss_ntsc_timings;
296 #endif
297
298 struct omap_overlay_info {
299         bool enabled;
300
301         u32 paddr;
302         void __iomem *vaddr;
303         u16 screen_width;
304         u16 width;
305         u16 height;
306         enum omap_color_mode color_mode;
307         u8 rotation;
308         enum omap_dss_rotation_type rotation_type;
309         bool mirror;
310
311         u16 pos_x;
312         u16 pos_y;
313         u16 out_width;  /* if 0, out_width == width */
314         u16 out_height; /* if 0, out_height == height */
315         u8 global_alpha;
316         u8 pre_mult_alpha;
317 };
318
319 struct omap_overlay {
320         struct kobject kobj;
321         struct list_head list;
322
323         /* static fields */
324         const char *name;
325         int id;
326         enum omap_color_mode supported_modes;
327         enum omap_overlay_caps caps;
328
329         /* dynamic fields */
330         struct omap_overlay_manager *manager;
331         struct omap_overlay_info info;
332
333         /* if true, info has been changed, but not applied() yet */
334         bool info_dirty;
335
336         int (*set_manager)(struct omap_overlay *ovl,
337                 struct omap_overlay_manager *mgr);
338         int (*unset_manager)(struct omap_overlay *ovl);
339
340         int (*set_overlay_info)(struct omap_overlay *ovl,
341                         struct omap_overlay_info *info);
342         void (*get_overlay_info)(struct omap_overlay *ovl,
343                         struct omap_overlay_info *info);
344
345         int (*wait_for_go)(struct omap_overlay *ovl);
346 };
347
348 struct omap_overlay_manager_info {
349         u32 default_color;
350
351         enum omap_dss_trans_key_type trans_key_type;
352         u32 trans_key;
353         bool trans_enabled;
354
355         bool alpha_enabled;
356 };
357
358 struct omap_overlay_manager {
359         struct kobject kobj;
360         struct list_head list;
361
362         /* static fields */
363         const char *name;
364         int id;
365         enum omap_overlay_manager_caps caps;
366         int num_overlays;
367         struct omap_overlay **overlays;
368         enum omap_display_type supported_displays;
369
370         /* dynamic fields */
371         struct omap_dss_device *device;
372         struct omap_overlay_manager_info info;
373
374         bool device_changed;
375         /* if true, info has been changed but not applied() yet */
376         bool info_dirty;
377
378         int (*set_device)(struct omap_overlay_manager *mgr,
379                 struct omap_dss_device *dssdev);
380         int (*unset_device)(struct omap_overlay_manager *mgr);
381
382         int (*set_manager_info)(struct omap_overlay_manager *mgr,
383                         struct omap_overlay_manager_info *info);
384         void (*get_manager_info)(struct omap_overlay_manager *mgr,
385                         struct omap_overlay_manager_info *info);
386
387         int (*apply)(struct omap_overlay_manager *mgr);
388         int (*wait_for_go)(struct omap_overlay_manager *mgr);
389         int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
390
391         int (*enable)(struct omap_overlay_manager *mgr);
392         int (*disable)(struct omap_overlay_manager *mgr);
393 };
394
395 struct omap_dss_device {
396         struct device dev;
397
398         enum omap_display_type type;
399
400         enum omap_channel channel;
401
402         union {
403                 struct {
404                         u8 data_lines;
405                 } dpi;
406
407                 struct {
408                         u8 channel;
409                         u8 data_lines;
410                 } rfbi;
411
412                 struct {
413                         u8 datapairs;
414                 } sdi;
415
416                 struct {
417                         u8 clk_lane;
418                         u8 clk_pol;
419                         u8 data1_lane;
420                         u8 data1_pol;
421                         u8 data2_lane;
422                         u8 data2_pol;
423                         u8 data3_lane;
424                         u8 data3_pol;
425                         u8 data4_lane;
426                         u8 data4_pol;
427
428                         int module;
429
430                         bool ext_te;
431                         u8 ext_te_gpio;
432                 } dsi;
433
434                 struct {
435                         enum omap_dss_venc_type type;
436                         bool invert_polarity;
437                 } venc;
438         } phy;
439
440         struct {
441                 struct {
442                         struct {
443                                 u16 lck_div;
444                                 u16 pck_div;
445                                 enum omap_dss_clk_source lcd_clk_src;
446                         } channel;
447
448                         enum omap_dss_clk_source dispc_fclk_src;
449                 } dispc;
450
451                 struct {
452                         u16 regn;
453                         u16 regm;
454                         u16 regm_dispc;
455                         u16 regm_dsi;
456
457                         u16 lp_clk_div;
458                         enum omap_dss_clk_source dsi_fclk_src;
459                 } dsi;
460
461                 struct {
462                         u16 regn;
463                         u16 regm2;
464                 } hdmi;
465         } clocks;
466
467         struct {
468                 struct omap_video_timings timings;
469
470                 int acbi;       /* ac-bias pin transitions per interrupt */
471                 /* Unit: line clocks */
472                 int acb;        /* ac-bias pin frequency */
473
474                 enum omap_panel_config config;
475         } panel;
476
477         struct {
478                 u8 pixel_size;
479                 struct rfbi_timings rfbi_timings;
480         } ctrl;
481
482         int reset_gpio;
483
484         int max_backlight_level;
485
486         const char *name;
487
488         /* used to match device to driver */
489         const char *driver_name;
490
491         void *data;
492
493         struct omap_dss_driver *driver;
494
495         /* helper variable for driver suspend/resume */
496         bool activate_after_resume;
497
498         enum omap_display_caps caps;
499
500         struct omap_overlay_manager *manager;
501
502         enum omap_dss_display_state state;
503
504         /* platform specific  */
505         int (*platform_enable)(struct omap_dss_device *dssdev);
506         void (*platform_disable)(struct omap_dss_device *dssdev);
507         int (*set_backlight)(struct omap_dss_device *dssdev, int level);
508         int (*get_backlight)(struct omap_dss_device *dssdev);
509 };
510
511 struct omap_dss_driver {
512         struct device_driver driver;
513
514         int (*probe)(struct omap_dss_device *);
515         void (*remove)(struct omap_dss_device *);
516
517         int (*enable)(struct omap_dss_device *display);
518         void (*disable)(struct omap_dss_device *display);
519         int (*suspend)(struct omap_dss_device *display);
520         int (*resume)(struct omap_dss_device *display);
521         int (*run_test)(struct omap_dss_device *display, int test);
522
523         int (*set_update_mode)(struct omap_dss_device *dssdev,
524                         enum omap_dss_update_mode);
525         enum omap_dss_update_mode (*get_update_mode)(
526                         struct omap_dss_device *dssdev);
527
528         int (*update)(struct omap_dss_device *dssdev,
529                                u16 x, u16 y, u16 w, u16 h);
530         int (*sync)(struct omap_dss_device *dssdev);
531
532         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
533         int (*get_te)(struct omap_dss_device *dssdev);
534
535         u8 (*get_rotate)(struct omap_dss_device *dssdev);
536         int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
537
538         bool (*get_mirror)(struct omap_dss_device *dssdev);
539         int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
540
541         int (*memory_read)(struct omap_dss_device *dssdev,
542                         void *buf, size_t size,
543                         u16 x, u16 y, u16 w, u16 h);
544
545         void (*get_resolution)(struct omap_dss_device *dssdev,
546                         u16 *xres, u16 *yres);
547         void (*get_dimensions)(struct omap_dss_device *dssdev,
548                         u32 *width, u32 *height);
549         int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
550
551         int (*check_timings)(struct omap_dss_device *dssdev,
552                         struct omap_video_timings *timings);
553         void (*set_timings)(struct omap_dss_device *dssdev,
554                         struct omap_video_timings *timings);
555         void (*get_timings)(struct omap_dss_device *dssdev,
556                         struct omap_video_timings *timings);
557
558         int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
559         u32 (*get_wss)(struct omap_dss_device *dssdev);
560 };
561
562 int omap_dss_register_driver(struct omap_dss_driver *);
563 void omap_dss_unregister_driver(struct omap_dss_driver *);
564
565 void omap_dss_get_device(struct omap_dss_device *dssdev);
566 void omap_dss_put_device(struct omap_dss_device *dssdev);
567 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
568 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
569 struct omap_dss_device *omap_dss_find_device(void *data,
570                 int (*match)(struct omap_dss_device *dssdev, void *data));
571
572 int omap_dss_start_device(struct omap_dss_device *dssdev);
573 void omap_dss_stop_device(struct omap_dss_device *dssdev);
574
575 int omap_dss_get_num_overlay_managers(void);
576 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
577
578 int omap_dss_get_num_overlays(void);
579 struct omap_overlay *omap_dss_get_overlay(int num);
580
581 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
582                 u16 *xres, u16 *yres);
583 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
584
585 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
586 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
587 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
588
589 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
590 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
591                 unsigned long timeout);
592
593 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
594 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
595
596 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
597                 bool enable);
598 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
599
600 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
601                                     u16 *x, u16 *y, u16 *w, u16 *h,
602                                     bool enlarge_update_area);
603 int omap_dsi_update(struct omap_dss_device *dssdev,
604                 int channel,
605                 u16 x, u16 y, u16 w, u16 h,
606                 void (*callback)(int, void *), void *data);
607 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
608 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
609 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
610
611 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
612 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
613                 bool disconnect_lanes, bool enter_ulps);
614
615 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
616 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
617 void dpi_set_timings(struct omap_dss_device *dssdev,
618                         struct omap_video_timings *timings);
619 int dpi_check_timings(struct omap_dss_device *dssdev,
620                         struct omap_video_timings *timings);
621
622 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
623 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
624
625 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
626 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
627 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
628                 u16 *x, u16 *y, u16 *w, u16 *h);
629 int omap_rfbi_update(struct omap_dss_device *dssdev,
630                 u16 x, u16 y, u16 w, u16 h,
631                 void (*callback)(void *), void *data);
632 int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
633                 int data_lines);
634
635 #endif