include/video/omapdss.h

   1 /*
   2  * Copyright (C) 2008 Nokia Corporation
   3  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __OMAP_OMAPDSS_H
  19 #define __OMAP_OMAPDSS_H
  20
  21 #include <linux/list.h>
  22 #include <linux/kobject.h>
  23 #include <linux/device.h>
  24 #include <linux/platform_device.h>
  25 #include <asm/atomic.h>
  26
  27 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
  28 #define DISPC_IRQ_VSYNC                 (1 << 1)
  29 #define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
  30 #define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
  31 #define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
  32 #define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
  33 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
  34 #define DISPC_IRQ_GFX_END_WIN           (1 << 7)
  35 #define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
  36 #define DISPC_IRQ_OCP_ERR               (1 << 9)
  37 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
  38 #define DISPC_IRQ_VID1_END_WIN          (1 << 11)
  39 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
  40 #define DISPC_IRQ_VID2_END_WIN          (1 << 13)
  41 #define DISPC_IRQ_SYNC_LOST             (1 << 14)
  42 #define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
  43 #define DISPC_IRQ_WAKEUP                (1 << 16)
  44 #define DISPC_IRQ_SYNC_LOST2            (1 << 17)
  45 #define DISPC_IRQ_VSYNC2                (1 << 18)
  46 #define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
  47 #define DISPC_IRQ_FRAMEDONE2            (1 << 22)
  48
  49 struct omap_dss_device;
  50 struct omap_overlay_manager;
  51
  52 enum omap_display_type {
  53         OMAP_DISPLAY_TYPE_NONE          = 0,
  54         OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
  55         OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
  56         OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
  57         OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
  58         OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
  59         OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
  60 };
  61
  62 enum omap_plane {
  63         OMAP_DSS_GFX    = 0,
  64         OMAP_DSS_VIDEO1 = 1,
  65         OMAP_DSS_VIDEO2 = 2
  66 };
  67
  68 enum omap_channel {
  69         OMAP_DSS_CHANNEL_LCD    = 0,
  70         OMAP_DSS_CHANNEL_DIGIT  = 1,
  71         OMAP_DSS_CHANNEL_LCD2   = 2,
  72 };
  73
  74 enum omap_color_mode {
  75         OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
  76         OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
  77         OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
  78         OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
  79         OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
  80         OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
  81         OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
  82         OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
  83         OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
  84         OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
  85         OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
  86         OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
  87         OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
  88         OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
  89 };
  90
  91 enum omap_lcd_display_type {
  92         OMAP_DSS_LCD_DISPLAY_STN,
  93         OMAP_DSS_LCD_DISPLAY_TFT,
  94 };
  95
  96 enum omap_dss_load_mode {
  97         OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
  98         OMAP_DSS_LOAD_CLUT_ONLY         = 1,
  99         OMAP_DSS_LOAD_FRAME_ONLY        = 2,
 100         OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
 101 };
 102
 103 enum omap_dss_trans_key_type {
 104         OMAP_DSS_COLOR_KEY_GFX_DST = 0,
 105         OMAP_DSS_COLOR_KEY_VID_SRC = 1,
 106 };
 107
 108 enum omap_rfbi_te_mode {
 109         OMAP_DSS_RFBI_TE_MODE_1 = 1,
 110         OMAP_DSS_RFBI_TE_MODE_2 = 2,
 111 };
 112
 113 enum omap_panel_config {
 114         OMAP_DSS_LCD_IVS                = 1<<0,
 115         OMAP_DSS_LCD_IHS                = 1<<1,
 116         OMAP_DSS_LCD_IPC                = 1<<2,
 117         OMAP_DSS_LCD_IEO                = 1<<3,
 118         OMAP_DSS_LCD_RF                 = 1<<4,
 119         OMAP_DSS_LCD_ONOFF              = 1<<5,
 120
 121         OMAP_DSS_LCD_TFT                = 1<<20,
 122 };
 123
 124 enum omap_dss_venc_type {
 125         OMAP_DSS_VENC_TYPE_COMPOSITE,
 126         OMAP_DSS_VENC_TYPE_SVIDEO,
 127 };
 128
 129 enum omap_display_caps {
 130         OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
 131         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
 132 };
 133
 134 enum omap_dss_update_mode {
 135         OMAP_DSS_UPDATE_DISABLED = 0,
 136         OMAP_DSS_UPDATE_AUTO,
 137         OMAP_DSS_UPDATE_MANUAL,
 138 };
 139
 140 enum omap_dss_display_state {
 141         OMAP_DSS_DISPLAY_DISABLED = 0,
 142         OMAP_DSS_DISPLAY_ACTIVE,
 143         OMAP_DSS_DISPLAY_SUSPENDED,
 144 };
 145
 146 /* XXX perhaps this should be removed */
 147 enum omap_dss_overlay_managers {
 148         OMAP_DSS_OVL_MGR_LCD,
 149         OMAP_DSS_OVL_MGR_TV,
 150         OMAP_DSS_OVL_MGR_LCD2,
 151 };
 152
 153 enum omap_dss_rotation_type {
 154         OMAP_DSS_ROT_DMA = 0,
 155         OMAP_DSS_ROT_VRFB = 1,
 156 };
 157
 158 /* clockwise rotation angle */
 159 enum omap_dss_rotation_angle {
 160         OMAP_DSS_ROT_0   = 0,
 161         OMAP_DSS_ROT_90  = 1,
 162         OMAP_DSS_ROT_180 = 2,
 163         OMAP_DSS_ROT_270 = 3,
 164 };
 165
 166 enum omap_overlay_caps {
 167         OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
 168         OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
 169 };
 170
 171 enum omap_overlay_manager_caps {
 172         OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
 173 };
 174
 175 enum omap_dss_clk_source {
 176         OMAP_DSS_CLK_SRC_FCK = 0,               /* OMAP2/3: DSS1_ALWON_FCLK
 177                                                  * OMAP4: DSS_FCLK */
 178         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,   /* OMAP3: DSI1_PLL_FCLK
 179                                                  * OMAP4: PLL1_CLK1 */
 180         OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,     /* OMAP3: DSI2_PLL_FCLK
 181                                                  * OMAP4: PLL1_CLK2 */
 182         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,  /* OMAP4: PLL2_CLK1 */
 183         OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,    /* OMAP4: PLL2_CLK2 */
 184 };
 185
 186 /* RFBI */
 187
 188 struct rfbi_timings {
 189         int cs_on_time;
 190         int cs_off_time;
 191         int we_on_time;
 192         int we_off_time;
 193         int re_on_time;
 194         int re_off_time;
 195         int we_cycle_time;
 196         int re_cycle_time;
 197         int cs_pulse_width;
 198         int access_time;
 199
 200         int clk_div;
 201
 202         u32 tim[5];             /* set by rfbi_convert_timings() */
 203
 204         int converted;
 205 };
 206
 207 void omap_rfbi_write_command(const void *buf, u32 len);
 208 void omap_rfbi_read_data(void *buf, u32 len);
 209 void omap_rfbi_write_data(const void *buf, u32 len);
 210 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
 211                 u16 x, u16 y,
 212                 u16 w, u16 h);
 213 int omap_rfbi_enable_te(bool enable, unsigned line);
 214 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
 215                              unsigned hs_pulse_time, unsigned vs_pulse_time,
 216                              int hs_pol_inv, int vs_pol_inv, int extif_div);
 217
 218 /* DSI */
 219 void dsi_bus_lock(struct omap_dss_device *dssdev);
 220 void dsi_bus_unlock(struct omap_dss_device *dssdev);
 221 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
 222                 int len);
 223 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
 224                 u8 dcs_cmd);
 225 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 226                 u8 param);
 227 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
 228                 u8 *data, int len);
 229 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 230                 u8 *buf, int buflen);
 231 int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 232                 u8 *data);
 233 int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
 234                 u8 *data1, u8 *data2);
 235 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
 236                 u16 len);
 237 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
 238 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
 239
 240 /* Board specific data */
 241 struct omap_dss_board_info {
 242         int (*get_last_off_on_transaction_id)(struct device *dev);
 243         int num_devices;
 244         struct omap_dss_device **devices;
 245         struct omap_dss_device *default_device;
 246         void (*dsi_mux_pads)(bool enable);
 247 };
 248
 249 #if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
 250 /* Init with the board info */
 251 extern int omap_display_init(struct omap_dss_board_info *board_data);
 252 #else
 253 static inline int omap_display_init(struct omap_dss_board_info *board_data)
 254 {
 255         return 0;
 256 }
 257 #endif
 258
 259 struct omap_display_platform_data {
 260         struct omap_dss_board_info *board_data;
 261         /* TODO: Additional members to be added when PM is considered */
 262
 263         bool (*opt_clock_available)(const char *clk_role);
 264 };
 265
 266 struct omap_video_timings {
 267         /* Unit: pixels */
 268         u16 x_res;
 269         /* Unit: pixels */
 270         u16 y_res;
 271         /* Unit: KHz */
 272         u32 pixel_clock;
 273         /* Unit: pixel clocks */
 274         u16 hsw;        /* Horizontal synchronization pulse width */
 275         /* Unit: pixel clocks */
 276         u16 hfp;        /* Horizontal front porch */
 277         /* Unit: pixel clocks */
 278         u16 hbp;        /* Horizontal back porch */
 279         /* Unit: line clocks */
 280         u16 vsw;        /* Vertical synchronization pulse width */
 281         /* Unit: line clocks */
 282         u16 vfp;        /* Vertical front porch */
 283         /* Unit: line clocks */
 284         u16 vbp;        /* Vertical back porch */
 285 };
 286
 287 #ifdef CONFIG_OMAP2_DSS_VENC
 288 /* Hardcoded timings for tv modes. Venc only uses these to
 289  * identify the mode, and does not actually use the configs
 290  * itself. However, the configs should be something that
 291  * a normal monitor can also show */
 292 extern const struct omap_video_timings omap_dss_pal_timings;
 293 extern const struct omap_video_timings omap_dss_ntsc_timings;
 294 #endif
 295
 296 struct omap_overlay_info {
 297         bool enabled;
 298
 299         u32 paddr;
 300         void __iomem *vaddr;
 301         u16 screen_width;
 302         u16 width;
 303         u16 height;
 304         enum omap_color_mode color_mode;
 305         u8 rotation;
 306         enum omap_dss_rotation_type rotation_type;
 307         bool mirror;
 308
 309         u16 pos_x;
 310         u16 pos_y;
 311         u16 out_width;  /* if 0, out_width == width */
 312         u16 out_height; /* if 0, out_height == height */
 313         u8 global_alpha;
 314         u8 pre_mult_alpha;
 315 };
 316
 317 struct omap_overlay {
 318         struct kobject kobj;
 319         struct list_head list;
 320
 321         /* static fields */
 322         const char *name;
 323         int id;
 324         enum omap_color_mode supported_modes;
 325         enum omap_overlay_caps caps;
 326
 327         /* dynamic fields */
 328         struct omap_overlay_manager *manager;
 329         struct omap_overlay_info info;
 330
 331         /* if true, info has been changed, but not applied() yet */
 332         bool info_dirty;
 333
 334         int (*set_manager)(struct omap_overlay *ovl,
 335                 struct omap_overlay_manager *mgr);
 336         int (*unset_manager)(struct omap_overlay *ovl);
 337
 338         int (*set_overlay_info)(struct omap_overlay *ovl,
 339                         struct omap_overlay_info *info);
 340         void (*get_overlay_info)(struct omap_overlay *ovl,
 341                         struct omap_overlay_info *info);
 342
 343         int (*wait_for_go)(struct omap_overlay *ovl);
 344 };
 345
 346 struct omap_overlay_manager_info {
 347         u32 default_color;
 348
 349         enum omap_dss_trans_key_type trans_key_type;
 350         u32 trans_key;
 351         bool trans_enabled;
 352
 353         bool alpha_enabled;
 354 };
 355
 356 struct omap_overlay_manager {
 357         struct kobject kobj;
 358         struct list_head list;
 359
 360         /* static fields */
 361         const char *name;
 362         int id;
 363         enum omap_overlay_manager_caps caps;
 364         int num_overlays;
 365         struct omap_overlay **overlays;
 366         enum omap_display_type supported_displays;
 367
 368         /* dynamic fields */
 369         struct omap_dss_device *device;
 370         struct omap_overlay_manager_info info;
 371
 372         bool device_changed;
 373         /* if true, info has been changed but not applied() yet */
 374         bool info_dirty;
 375
 376         int (*set_device)(struct omap_overlay_manager *mgr,
 377                 struct omap_dss_device *dssdev);
 378         int (*unset_device)(struct omap_overlay_manager *mgr);
 379
 380         int (*set_manager_info)(struct omap_overlay_manager *mgr,
 381                         struct omap_overlay_manager_info *info);
 382         void (*get_manager_info)(struct omap_overlay_manager *mgr,
 383                         struct omap_overlay_manager_info *info);
 384
 385         int (*apply)(struct omap_overlay_manager *mgr);
 386         int (*wait_for_go)(struct omap_overlay_manager *mgr);
 387         int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
 388
 389         int (*enable)(struct omap_overlay_manager *mgr);
 390         int (*disable)(struct omap_overlay_manager *mgr);
 391 };
 392
 393 struct omap_dss_device {
 394         struct device dev;
 395
 396         enum omap_display_type type;
 397
 398         enum omap_channel channel;
 399
 400         union {
 401                 struct {
 402                         u8 data_lines;
 403                 } dpi;
 404
 405                 struct {
 406                         u8 channel;
 407                         u8 data_lines;
 408                 } rfbi;
 409
 410                 struct {
 411                         u8 datapairs;
 412                 } sdi;
 413
 414                 struct {
 415                         u8 clk_lane;
 416                         u8 clk_pol;
 417                         u8 data1_lane;
 418                         u8 data1_pol;
 419                         u8 data2_lane;
 420                         u8 data2_pol;
 421
 422                         int module;
 423
 424                         bool ext_te;
 425                         u8 ext_te_gpio;
 426                 } dsi;
 427
 428                 struct {
 429                         enum omap_dss_venc_type type;
 430                         bool invert_polarity;
 431                 } venc;
 432         } phy;
 433
 434         struct {
 435                 struct {
 436                         struct {
 437                                 u16 lck_div;
 438                                 u16 pck_div;
 439                                 enum omap_dss_clk_source lcd_clk_src;
 440                         } channel;
 441
 442                         enum omap_dss_clk_source dispc_fclk_src;
 443                 } dispc;
 444
 445                 struct {
 446                         u16 regn;
 447                         u16 regm;
 448                         u16 regm_dispc;
 449                         u16 regm_dsi;
 450
 451                         u16 lp_clk_div;
 452                         enum omap_dss_clk_source dsi_fclk_src;
 453                 } dsi;
 454
 455                 struct {
 456                         u16 regn;
 457                         u16 regm2;
 458                 } hdmi;
 459         } clocks;
 460
 461         struct {
 462                 struct omap_video_timings timings;
 463
 464                 int acbi;       /* ac-bias pin transitions per interrupt */
 465                 /* Unit: line clocks */
 466                 int acb;        /* ac-bias pin frequency */
 467
 468                 enum omap_panel_config config;
 469         } panel;
 470
 471         struct {
 472                 u8 pixel_size;
 473                 struct rfbi_timings rfbi_timings;
 474         } ctrl;
 475
 476         int reset_gpio;
 477
 478         int max_backlight_level;
 479
 480         const char *name;
 481
 482         /* used to match device to driver */
 483         const char *driver_name;
 484
 485         void *data;
 486
 487         struct omap_dss_driver *driver;
 488
 489         /* helper variable for driver suspend/resume */
 490         bool activate_after_resume;
 491
 492         enum omap_display_caps caps;
 493
 494         struct omap_overlay_manager *manager;
 495
 496         enum omap_dss_display_state state;
 497
 498         /* platform specific  */
 499         int (*platform_enable)(struct omap_dss_device *dssdev);
 500         void (*platform_disable)(struct omap_dss_device *dssdev);
 501         int (*set_backlight)(struct omap_dss_device *dssdev, int level);
 502         int (*get_backlight)(struct omap_dss_device *dssdev);
 503 };
 504
 505 struct omap_dss_driver {
 506         struct device_driver driver;
 507
 508         int (*probe)(struct omap_dss_device *);
 509         void (*remove)(struct omap_dss_device *);
 510
 511         int (*enable)(struct omap_dss_device *display);
 512         void (*disable)(struct omap_dss_device *display);
 513         int (*suspend)(struct omap_dss_device *display);
 514         int (*resume)(struct omap_dss_device *display);
 515         int (*run_test)(struct omap_dss_device *display, int test);
 516
 517         int (*set_update_mode)(struct omap_dss_device *dssdev,
 518                         enum omap_dss_update_mode);
 519         enum omap_dss_update_mode (*get_update_mode)(
 520                         struct omap_dss_device *dssdev);
 521
 522         int (*update)(struct omap_dss_device *dssdev,
 523                                u16 x, u16 y, u16 w, u16 h);
 524         int (*sync)(struct omap_dss_device *dssdev);
 525
 526         int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 527         int (*get_te)(struct omap_dss_device *dssdev);
 528
 529         u8 (*get_rotate)(struct omap_dss_device *dssdev);
 530         int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 531
 532         bool (*get_mirror)(struct omap_dss_device *dssdev);
 533         int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
 534
 535         int (*memory_read)(struct omap_dss_device *dssdev,
 536                         void *buf, size_t size,
 537                         u16 x, u16 y, u16 w, u16 h);
 538
 539         void (*get_resolution)(struct omap_dss_device *dssdev,
 540                         u16 *xres, u16 *yres);
 541         void (*get_dimensions)(struct omap_dss_device *dssdev,
 542                         u32 *width, u32 *height);
 543         int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
 544
 545         int (*check_timings)(struct omap_dss_device *dssdev,
 546                         struct omap_video_timings *timings);
 547         void (*set_timings)(struct omap_dss_device *dssdev,
 548                         struct omap_video_timings *timings);
 549         void (*get_timings)(struct omap_dss_device *dssdev,
 550                         struct omap_video_timings *timings);
 551
 552         int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
 553         u32 (*get_wss)(struct omap_dss_device *dssdev);
 554 };
 555
 556 int omap_dss_register_driver(struct omap_dss_driver *);
 557 void omap_dss_unregister_driver(struct omap_dss_driver *);
 558
 559 void omap_dss_get_device(struct omap_dss_device *dssdev);
 560 void omap_dss_put_device(struct omap_dss_device *dssdev);
 561 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
 562 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
 563 struct omap_dss_device *omap_dss_find_device(void *data,
 564                 int (*match)(struct omap_dss_device *dssdev, void *data));
 565
 566 int omap_dss_start_device(struct omap_dss_device *dssdev);
 567 void omap_dss_stop_device(struct omap_dss_device *dssdev);
 568
 569 int omap_dss_get_num_overlay_managers(void);
 570 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
 571
 572 int omap_dss_get_num_overlays(void);
 573 struct omap_overlay *omap_dss_get_overlay(int num);
 574
 575 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
 576                 u16 *xres, u16 *yres);
 577 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
 578
 579 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 580 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 581 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 582
 583 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
 584 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
 585                 unsigned long timeout);
 586
 587 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
 588 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
 589
 590 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
 591                 bool enable);
 592 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
 593
 594 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
 595                                     u16 *x, u16 *y, u16 *w, u16 *h,
 596                                     bool enlarge_update_area);
 597 int omap_dsi_update(struct omap_dss_device *dssdev,
 598                 int channel,
 599                 u16 x, u16 y, u16 w, u16 h,
 600                 void (*callback)(int, void *), void *data);
 601 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
 602 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
 603 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
 604
 605 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
 606 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
 607                 bool disconnect_lanes, bool enter_ulps);
 608
 609 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
 610 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
 611 void dpi_set_timings(struct omap_dss_device *dssdev,
 612                         struct omap_video_timings *timings);
 613 int dpi_check_timings(struct omap_dss_device *dssdev,
 614                         struct omap_video_timings *timings);
 615
 616 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
 617 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
 618
 619 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
 620 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
 621 int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
 622                 u16 *x, u16 *y, u16 *w, u16 *h);
 623 int omap_rfbi_update(struct omap_dss_device *dssdev,
 624                 u16 x, u16 y, u16 w, u16 h,
 625                 void (*callback)(void *), void *data);
 626
 627 #endif