2 * include/linux/mmc/sh_mmcif.h
4 * platform data for eMMC driver
6 * Copyright (C) 2010 Renesas Solutions Corp.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
14 #ifndef __SH_MMCIF_H__
15 #define __SH_MMCIF_H__
17 #include <linux/platform_device.h>
21 * MMCIF : CE_CLK_CTRL [19:16]
22 * 1000 : Peripheral clock / 512
23 * 0111 : Peripheral clock / 256
24 * 0110 : Peripheral clock / 128
25 * 0101 : Peripheral clock / 64
26 * 0100 : Peripheral clock / 32
27 * 0011 : Peripheral clock / 16
28 * 0010 : Peripheral clock / 8
29 * 0001 : Peripheral clock / 4
30 * 0000 : Peripheral clock / 2
31 * 1111 : Peripheral clock (sup_pclk set '1')
34 struct sh_mmcif_plat_data {
35 void (*set_pwr)(struct platform_device *pdev, int state);
36 void (*down_pwr)(struct platform_device *pdev);
37 int (*get_cd)(struct platform_device *pdef);
38 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
43 #define MMCIF_CE_CMD_SET 0x00000000
44 #define MMCIF_CE_ARG 0x00000008
45 #define MMCIF_CE_ARG_CMD12 0x0000000C
46 #define MMCIF_CE_CMD_CTRL 0x00000010
47 #define MMCIF_CE_BLOCK_SET 0x00000014
48 #define MMCIF_CE_CLK_CTRL 0x00000018
49 #define MMCIF_CE_BUF_ACC 0x0000001C
50 #define MMCIF_CE_RESP3 0x00000020
51 #define MMCIF_CE_RESP2 0x00000024
52 #define MMCIF_CE_RESP1 0x00000028
53 #define MMCIF_CE_RESP0 0x0000002C
54 #define MMCIF_CE_RESP_CMD12 0x00000030
55 #define MMCIF_CE_DATA 0x00000034
56 #define MMCIF_CE_INT 0x00000040
57 #define MMCIF_CE_INT_MASK 0x00000044
58 #define MMCIF_CE_HOST_STS1 0x00000048
59 #define MMCIF_CE_HOST_STS2 0x0000004C
60 #define MMCIF_CE_VERSION 0x0000007C
63 #define BUF_ACC_DMAWEN (1 << 25)
64 #define BUF_ACC_DMAREN (1 << 24)
65 #define BUF_ACC_BUSW_32 (0 << 17)
66 #define BUF_ACC_BUSW_16 (1 << 17)
67 #define BUF_ACC_ATYP (1 << 16)
70 #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
71 #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
72 #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
73 #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
74 #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
75 (1 << 9) | (1 << 8)) /* resp busy timeout */
76 #define SRWDTO_29 ((1 << 7) | (1 << 6) | \
77 (1 << 5) | (1 << 4)) /* read/write timeout */
78 #define SCCSTO_29 ((1 << 3) | (1 << 2) | \
79 (1 << 1) | (1 << 0)) /* ccs timeout */
82 #define SOFT_RST_ON (1 << 31)
83 #define SOFT_RST_OFF 0
85 static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
87 return readl(addr + reg);
90 static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
92 writel(val, addr + reg);
95 #define SH_MMCIF_BBS 512 /* boot block size */
97 static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
98 unsigned long cmd, unsigned long arg)
100 sh_mmcif_writel(base, MMCIF_CE_INT, 0);
101 sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
102 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
105 static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
110 for (cnt = 0; cnt < 1000000; cnt++) {
111 tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
113 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
121 static inline int sh_mmcif_boot_cmd(void __iomem *base,
122 unsigned long cmd, unsigned long arg)
124 sh_mmcif_boot_cmd_send(base, cmd, arg);
125 return sh_mmcif_boot_cmd_poll(base, 0x00010000);
128 static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
129 unsigned int block_nr,
135 sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
137 if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
141 sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
142 if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
145 for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
146 buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
151 static inline int sh_mmcif_boot_do_read(void __iomem *base,
152 unsigned long first_block,
153 unsigned long nr_blocks,
159 /* CMD16 - Set the block size */
160 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
162 for (k = 0; !ret && k < nr_blocks; k++)
163 ret = sh_mmcif_boot_do_read_single(base, first_block + k,
164 buf + (k * SH_MMCIF_BBS));
169 static inline void sh_mmcif_boot_init(void __iomem *base)
172 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
173 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
176 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
178 /* Set block size in MMCIF hardware */
179 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
181 /* Enable the clock, set it to Bus clock/256 (about 325Khz).
182 * It is unclear where 0x70000 comes from or if it is even needed.
183 * It is there for byte-compatibility with code that is known to
186 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
187 CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 |
188 SCCSTO_29 | 0x70000);
191 sh_mmcif_boot_cmd(base, 0x00000040, 0);
195 sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
196 } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
200 sh_mmcif_boot_cmd(base, 0x02806040, 0);
202 /* CMD3 - Set card relative address */
203 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
206 static inline void sh_mmcif_boot_slurp(void __iomem *base,
208 unsigned long no_bytes)
212 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
213 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
216 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
218 /* CMD7 - Select the card */
219 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
221 tmp = no_bytes / SH_MMCIF_BBS;
222 tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;
224 sh_mmcif_boot_do_read(base, 512, tmp, buf);
227 #endif /* __SH_MMCIF_H__ */