2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/dma-mapping.h>
29 * typedef dma_cookie_t - an opaque DMA cookie
31 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
33 typedef s32 dma_cookie_t;
34 #define DMA_MIN_COOKIE 1
35 #define DMA_MAX_COOKIE INT_MAX
37 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
40 * enum dma_status - DMA transaction status
41 * @DMA_SUCCESS: transaction completed successfully
42 * @DMA_IN_PROGRESS: transaction not yet processed
43 * @DMA_PAUSED: transaction is paused
44 * @DMA_ERROR: transaction failed
54 * enum dma_transaction_type - DMA transaction types/indexes
56 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
57 * automatically set as dma devices are registered.
59 enum dma_transaction_type {
73 /* last transaction type for creation of the capabilities mask */
74 #define DMA_TX_TYPE_END (DMA_SLAVE + 1)
78 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
79 * control completion, and communicate status.
80 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
82 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
83 * acknowledges receipt, i.e. has has a chance to establish any dependency
85 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
86 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
87 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
88 * (if not set, do the source dma-unmapping as page)
89 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
90 * (if not set, do the destination dma-unmapping as page)
91 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
92 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
93 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
94 * sources that were the result of a previous operation, in the case of a PQ
95 * operation it continues the calculation with new sources
96 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
97 * on the result of this operation
100 DMA_PREP_INTERRUPT = (1 << 0),
101 DMA_CTRL_ACK = (1 << 1),
102 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
103 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
104 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
105 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
106 DMA_PREP_PQ_DISABLE_P = (1 << 6),
107 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
108 DMA_PREP_CONTINUE = (1 << 8),
109 DMA_PREP_FENCE = (1 << 9),
113 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
114 * on a running channel.
115 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
116 * @DMA_PAUSE: pause ongoing transfers
117 * @DMA_RESUME: resume paused transfer
118 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
119 * that need to runtime reconfigure the slave channels (as opposed to passing
120 * configuration data in statically from the platform). An additional
121 * argument of struct dma_slave_config must be passed in with this
132 * enum sum_check_bits - bit position of pq_check_flags
134 enum sum_check_bits {
140 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
141 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
142 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
144 enum sum_check_flags {
145 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
146 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
151 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
152 * See linux/cpumask.h
154 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
157 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
158 * @memcpy_count: transaction counter
159 * @bytes_transferred: byte counter
162 struct dma_chan_percpu {
164 unsigned long memcpy_count;
165 unsigned long bytes_transferred;
169 * struct dma_chan - devices supply DMA channels, clients use them
170 * @device: ptr to the dma device who supplies this channel, always !%NULL
171 * @cookie: last cookie value returned to client
172 * @chan_id: channel ID for sysfs
173 * @dev: class device for sysfs
174 * @device_node: used to add this to the device chan list
175 * @local: per-cpu pointer to a struct dma_chan_percpu
176 * @client-count: how many clients are using this channel
177 * @table_count: number of appearances in the mem-to-mem allocation table
178 * @private: private data for certain client-channel associations
181 struct dma_device *device;
186 struct dma_chan_dev *dev;
188 struct list_head device_node;
189 struct dma_chan_percpu __percpu *local;
196 * struct dma_chan_dev - relate sysfs device node to backing channel device
197 * @chan - driver channel device
198 * @device - sysfs device
199 * @dev_id - parent dma_device dev_id
200 * @idr_ref - reference count to gate release of dma_device dev_id
202 struct dma_chan_dev {
203 struct dma_chan *chan;
204 struct device device;
210 * enum dma_slave_buswidth - defines bus with of the DMA slave
211 * device, source or target buses
213 enum dma_slave_buswidth {
214 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
215 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
216 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
217 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
218 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
222 * struct dma_slave_config - dma slave channel runtime config
223 * @direction: whether the data shall go in or out on this slave
224 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
225 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
226 * need to differentiate source and target addresses.
227 * @src_addr: this is the physical address where DMA slave data
228 * should be read (RX), if the source is memory this argument is
230 * @dst_addr: this is the physical address where DMA slave data
231 * should be written (TX), if the source is memory this argument
233 * @src_addr_width: this is the width in bytes of the source (RX)
234 * register where DMA data shall be read. If the source
235 * is memory this may be ignored depending on architecture.
236 * Legal values: 1, 2, 4, 8.
237 * @dst_addr_width: same as src_addr_width but for destination
238 * target (TX) mutatis mutandis.
239 * @src_maxburst: the maximum number of words (note: words, as in
240 * units of the src_addr_width member, not bytes) that can be sent
241 * in one burst to the device. Typically something like half the
242 * FIFO depth on I/O peripherals so you don't overflow it. This
243 * may or may not be applicable on memory sources.
244 * @dst_maxburst: same as src_maxburst but for destination target
247 * This struct is passed in as configuration data to a DMA engine
248 * in order to set up a certain channel for DMA transport at runtime.
249 * The DMA device/engine has to provide support for an additional
250 * command in the channel config interface, DMA_SLAVE_CONFIG
251 * and this struct will then be passed in as an argument to the
252 * DMA engine device_control() function.
254 * The rationale for adding configuration information to this struct
255 * is as follows: if it is likely that most DMA slave controllers in
256 * the world will support the configuration option, then make it
257 * generic. If not: if it is fixed so that it be sent in static from
258 * the platform data, then prefer to do that. Else, if it is neither
259 * fixed at runtime, nor generic enough (such as bus mastership on
260 * some CPU family and whatnot) then create a custom slave config
261 * struct and pass that, then make this config a member of that
262 * struct, if applicable.
264 struct dma_slave_config {
265 enum dma_data_direction direction;
268 enum dma_slave_buswidth src_addr_width;
269 enum dma_slave_buswidth dst_addr_width;
274 static inline const char *dma_chan_name(struct dma_chan *chan)
276 return dev_name(&chan->dev->device);
279 void dma_chan_cleanup(struct kref *kref);
282 * typedef dma_filter_fn - callback filter for dma_request_channel
283 * @chan: channel to be reviewed
284 * @filter_param: opaque parameter passed through dma_request_channel
286 * When this optional parameter is specified in a call to dma_request_channel a
287 * suitable channel is passed to this routine for further dispositioning before
288 * being returned. Where 'suitable' indicates a non-busy channel that
289 * satisfies the given capability mask. It returns 'true' to indicate that the
290 * channel is suitable.
292 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
294 typedef void (*dma_async_tx_callback)(void *dma_async_param);
296 * struct dma_async_tx_descriptor - async transaction descriptor
297 * ---dma generic offload fields---
298 * @cookie: tracking cookie for this transaction, set to -EBUSY if
299 * this tx is sitting on a dependency list
300 * @flags: flags to augment operation preparation, control completion, and
302 * @phys: physical address of the descriptor
303 * @chan: target channel for this operation
304 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
305 * @callback: routine to call after this operation is complete
306 * @callback_param: general parameter to pass to the callback routine
307 * ---async_tx api specific fields---
308 * @next: at completion submit this descriptor
309 * @parent: pointer to the next level up in the dependency chain
310 * @lock: protect the parent and next pointers
312 struct dma_async_tx_descriptor {
314 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
316 struct dma_chan *chan;
317 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
318 dma_async_tx_callback callback;
319 void *callback_param;
320 #ifndef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
321 struct dma_async_tx_descriptor *next;
322 struct dma_async_tx_descriptor *parent;
327 #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
328 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
331 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
334 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
338 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
341 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
344 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
348 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
354 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
356 spin_lock_bh(&txd->lock);
358 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
360 spin_unlock_bh(&txd->lock);
362 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
367 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
371 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
375 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
379 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
386 * struct dma_tx_state - filled in to report the status of
388 * @last: last completed DMA cookie
389 * @used: last issued DMA cookie (i.e. the one in progress)
390 * @residue: the remaining number of bytes left to transmit
391 * on the selected transfer for states DMA_IN_PROGRESS and
392 * DMA_PAUSED if this is implemented in the driver, else 0
394 struct dma_tx_state {
401 * struct dma_device - info on the entity supplying DMA services
402 * @chancnt: how many DMA channels are supported
403 * @privatecnt: how many DMA channels are requested by dma_request_channel
404 * @channels: the list of struct dma_chan
405 * @global_node: list_head for global dma_device_list
406 * @cap_mask: one or more dma_capability flags
407 * @max_xor: maximum number of xor sources, 0 if no capability
408 * @max_pq: maximum number of PQ sources and PQ-continue capability
409 * @copy_align: alignment shift for memcpy operations
410 * @xor_align: alignment shift for xor operations
411 * @pq_align: alignment shift for pq operations
412 * @fill_align: alignment shift for memset operations
413 * @dev_id: unique device ID
414 * @dev: struct device reference for dma mapping api
415 * @device_alloc_chan_resources: allocate resources and return the
416 * number of allocated descriptors
417 * @device_free_chan_resources: release DMA channel's resources
418 * @device_prep_dma_memcpy: prepares a memcpy operation
419 * @device_prep_dma_xor: prepares a xor operation
420 * @device_prep_dma_xor_val: prepares a xor validation operation
421 * @device_prep_dma_pq: prepares a pq operation
422 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
423 * @device_prep_dma_memset: prepares a memset operation
424 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
425 * @device_prep_slave_sg: prepares a slave dma operation
426 * @device_control: manipulate all pending operations on a channel, returns
428 * @device_tx_status: poll for transaction completion, the optional
429 * txstate parameter can be supplied with a pointer to get a
430 * struct with auxilary transfer status information, otherwise the call
431 * will just return a simple status code
432 * @device_issue_pending: push pending transactions to hardware
436 unsigned int chancnt;
437 unsigned int privatecnt;
438 struct list_head channels;
439 struct list_head global_node;
440 dma_cap_mask_t cap_mask;
441 unsigned short max_xor;
442 unsigned short max_pq;
447 #define DMA_HAS_PQ_CONTINUE (1 << 15)
452 int (*device_alloc_chan_resources)(struct dma_chan *chan);
453 void (*device_free_chan_resources)(struct dma_chan *chan);
455 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
456 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
457 size_t len, unsigned long flags);
458 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
459 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
460 unsigned int src_cnt, size_t len, unsigned long flags);
461 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
462 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
463 size_t len, enum sum_check_flags *result, unsigned long flags);
464 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
465 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
466 unsigned int src_cnt, const unsigned char *scf,
467 size_t len, unsigned long flags);
468 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
469 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
470 unsigned int src_cnt, const unsigned char *scf, size_t len,
471 enum sum_check_flags *pqres, unsigned long flags);
472 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
473 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
474 unsigned long flags);
475 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
476 struct dma_chan *chan, unsigned long flags);
477 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
478 struct dma_chan *chan,
479 struct scatterlist *dst_sg, unsigned int dst_nents,
480 struct scatterlist *src_sg, unsigned int src_nents,
481 unsigned long flags);
483 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
484 struct dma_chan *chan, struct scatterlist *sgl,
485 unsigned int sg_len, enum dma_data_direction direction,
486 unsigned long flags);
487 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
490 enum dma_status (*device_tx_status)(struct dma_chan *chan,
492 struct dma_tx_state *txstate);
493 void (*device_issue_pending)(struct dma_chan *chan);
496 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
502 mask = (1 << align) - 1;
503 if (mask & (off1 | off2 | len))
508 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
509 size_t off2, size_t len)
511 return dmaengine_check_align(dev->copy_align, off1, off2, len);
514 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
515 size_t off2, size_t len)
517 return dmaengine_check_align(dev->xor_align, off1, off2, len);
520 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
521 size_t off2, size_t len)
523 return dmaengine_check_align(dev->pq_align, off1, off2, len);
526 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
527 size_t off2, size_t len)
529 return dmaengine_check_align(dev->fill_align, off1, off2, len);
533 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
537 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
540 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
542 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
545 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
547 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
549 return (flags & mask) == mask;
552 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
554 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
557 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
559 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
562 /* dma_maxpq - reduce maxpq in the face of continued operations
563 * @dma - dma device with PQ capability
564 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
566 * When an engine does not support native continuation we need 3 extra
567 * source slots to reuse P and Q with the following coefficients:
568 * 1/ {00} * P : remove P from Q', but use it as a source for P'
569 * 2/ {01} * Q : use Q to continue Q' calculation
570 * 3/ {00} * Q : subtract Q from P' to cancel (2)
572 * In the case where P is disabled we only need 1 extra source:
573 * 1/ {01} * Q : use Q to continue Q' calculation
575 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
577 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
578 return dma_dev_to_maxpq(dma);
579 else if (dmaf_p_disabled_continue(flags))
580 return dma_dev_to_maxpq(dma) - 1;
581 else if (dmaf_continue(flags))
582 return dma_dev_to_maxpq(dma) - 3;
586 /* --- public DMA engine API --- */
588 #ifdef CONFIG_DMA_ENGINE
589 void dmaengine_get(void);
590 void dmaengine_put(void);
592 static inline void dmaengine_get(void)
595 static inline void dmaengine_put(void)
600 #ifdef CONFIG_NET_DMA
601 #define net_dmaengine_get() dmaengine_get()
602 #define net_dmaengine_put() dmaengine_put()
604 static inline void net_dmaengine_get(void)
607 static inline void net_dmaengine_put(void)
612 #ifdef CONFIG_ASYNC_TX_DMA
613 #define async_dmaengine_get() dmaengine_get()
614 #define async_dmaengine_put() dmaengine_put()
615 #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
616 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
618 #define async_dma_find_channel(type) dma_find_channel(type)
619 #endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */
621 static inline void async_dmaengine_get(void)
624 static inline void async_dmaengine_put(void)
627 static inline struct dma_chan *
628 async_dma_find_channel(enum dma_transaction_type type)
632 #endif /* CONFIG_ASYNC_TX_DMA */
634 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
635 void *dest, void *src, size_t len);
636 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
637 struct page *page, unsigned int offset, void *kdata, size_t len);
638 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
639 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
640 unsigned int src_off, size_t len);
641 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
642 struct dma_chan *chan);
644 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
646 tx->flags |= DMA_CTRL_ACK;
649 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
651 tx->flags &= ~DMA_CTRL_ACK;
654 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
656 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
659 #define first_dma_cap(mask) __first_dma_cap(&(mask))
660 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
662 return min_t(int, DMA_TX_TYPE_END,
663 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
666 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
667 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
669 return min_t(int, DMA_TX_TYPE_END,
670 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
673 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
675 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
677 set_bit(tx_type, dstp->bits);
680 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
682 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
684 clear_bit(tx_type, dstp->bits);
687 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
688 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
690 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
693 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
695 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
697 return test_bit(tx_type, srcp->bits);
700 #define for_each_dma_cap_mask(cap, mask) \
701 for ((cap) = first_dma_cap(mask); \
702 (cap) < DMA_TX_TYPE_END; \
703 (cap) = next_dma_cap((cap), (mask)))
706 * dma_async_issue_pending - flush pending transactions to HW
707 * @chan: target DMA channel
709 * This allows drivers to push copies to HW in batches,
710 * reducing MMIO writes where possible.
712 static inline void dma_async_issue_pending(struct dma_chan *chan)
714 chan->device->device_issue_pending(chan);
717 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
720 * dma_async_is_tx_complete - poll for transaction completion
722 * @cookie: transaction identifier to check status of
723 * @last: returns last completed cookie, can be NULL
724 * @used: returns last issued cookie, can be NULL
726 * If @last and @used are passed in, upon return they reflect the driver
727 * internal state and can be used with dma_async_is_complete() to check
728 * the status of multiple cookies without re-checking hardware state.
730 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
731 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
733 struct dma_tx_state state;
734 enum dma_status status;
736 status = chan->device->device_tx_status(chan, cookie, &state);
744 #define dma_async_memcpy_complete(chan, cookie, last, used)\
745 dma_async_is_tx_complete(chan, cookie, last, used)
748 * dma_async_is_complete - test a cookie against chan state
749 * @cookie: transaction identifier to test status of
750 * @last_complete: last know completed transaction
751 * @last_used: last cookie value handed out
753 * dma_async_is_complete() is used in dma_async_memcpy_complete()
754 * the test logic is separated for lightweight testing of multiple cookies
756 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
757 dma_cookie_t last_complete, dma_cookie_t last_used)
759 if (last_complete <= last_used) {
760 if ((cookie <= last_complete) || (cookie > last_used))
763 if ((cookie <= last_complete) && (cookie > last_used))
766 return DMA_IN_PROGRESS;
770 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
775 st->residue = residue;
779 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
780 #ifdef CONFIG_DMA_ENGINE
781 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
782 void dma_issue_pending_all(void);
784 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
788 static inline void dma_issue_pending_all(void)
794 /* --- DMA device --- */
796 int dma_async_device_register(struct dma_device *device);
797 void dma_async_device_unregister(struct dma_device *device);
798 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
799 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
800 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
801 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
802 void dma_release_channel(struct dma_chan *chan);
804 /* --- Helper iov-locking functions --- */
806 struct dma_page_list {
807 char __user *base_address;
812 struct dma_pinned_list {
814 struct dma_page_list page_list[0];
817 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
818 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
820 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
821 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
822 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
823 struct dma_pinned_list *pinned_list, struct page *page,
824 unsigned int offset, size_t len);
826 #endif /* DMAENGINE_H */