2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
5 * Copyright (C) 2004-2007 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 /* This file shoule be up to date with:
10 * - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
11 * - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
12 * - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
15 #ifndef _MACH_ANOMALY_H_
16 #define _MACH_ANOMALY_H_
18 /* We do not support 0.1 or 0.2 silicon - sorry */
19 #if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
20 #error Kernel will not work on BF533 Version 0.1 or 0.2
23 /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
24 #if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
25 || defined(CONFIG_BF_REV_0_3))
26 #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
27 * slot1 and store of a P register in slot 2 is not
29 #define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
30 * every corresponding match */
31 #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
32 * Channel DMA stops */
33 #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
35 #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
37 #define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
38 #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
40 #define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
42 #define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
44 #define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
45 #define ANOMALY_05000272 /* Certain data cache write through modes fail for
47 #define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
48 #define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
49 * an edge is detected may clear interrupt */
50 #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
51 * DMA system instability */
52 #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
54 #define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
56 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
57 * killed in a particular stage*/
58 #define ANOMALY_05000311 /* Erroneous flag pin operations under specific
60 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
61 * registers are interrupted */
62 #define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer */
63 #define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
64 * Next System MMR Access */
65 #define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V
66 * and 1.15V Not Allowed for LQFP Packages */
67 #endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
69 /* These issues only occur on 0.3 or 0.4 BF533 */
70 #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
71 #define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
72 * updated at the same time. */
73 #define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
74 * Cache Fill can be corrupted after or during
75 * Instruction DMA if certain core stalls exist */
76 #define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
77 * Purpose TX or RX modes */
78 #define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
79 * preceding memory read */
80 #define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
81 * inactive channels in certain conditions */
82 #define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
84 #define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
85 #define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
86 #define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
88 #define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
89 * Differences in certain Conditions */
90 #define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
91 #define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
93 #define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
94 * IDLE around a Change of Control causes
95 * unpredictable results */
96 #define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
97 * shadow of a conditional branch */
98 #define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
100 #define ANOMALY_05000253 /* Maximum external clock speed for Timers */
101 #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
102 * interrupt not functional */
103 #define ANOMALY_05000257 /* An interrupt or exception during short Hardware
104 * loops may cause the instruction fetch unit to
106 #define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
107 * the ICPLB Data registers differ */
108 #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
109 #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
110 #define ANOMALY_05000262 /* Stores to data cache may be lost */
111 #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
112 #define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
113 * instruction will cause an infinite stall in the
114 * second to last instruction in a hardware loop */
115 #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
116 * SPORT external receive and transmit clocks. */
117 #define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
118 * internal voltage regulator (VDDint) to increase. */
119 #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
120 * internal voltage regulator (VDDint) to decrease */
121 #endif /* issues only occur on 0.3 or 0.4 BF533 */
123 /* These issues are only on 0.4 silicon */
124 #if (defined(CONFIG_BF_REV_0_4))
125 #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
126 #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
128 #endif /* issues are only on 0.4 silicon */
130 /* These issues are only on 0.3 silicon */
131 #if defined(CONFIG_BF_REV_0_3)
132 #define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
133 * External Frame Syncs */
134 #define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
135 * Instruction or Data Fetches, or by Fetches at the
136 * boundary of reserved memory space */
137 #define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
138 * when polarity setting is changed */
139 #define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
141 #define ANOMALY_05000199 /* DMA current address shows wrong value during carry
143 #define ANOMALY_05000201 /* Receive frame sync not ignored during active
144 * frames in sport MCM */
145 #define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
147 #if defined(CONFIG_BF533)
148 #define ANOMALY_05000204 /* Incorrect data read with write-through cache and
149 * allocate cache lines on reads only mode */
150 #endif /* CONFIG_BF533 */
151 #define ANOMALY_05000207 /* Recovery from "brown-out" condition */
152 #define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
154 #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
155 * Sync Transmit Mode */
156 #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
157 #endif /* only on 0.3 silicon */
159 #if defined(CONFIG_BF_REV_0_2)
160 #define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not
162 #define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at
164 #define ANOMALY_05000116 /* Trace Buffers may record discontinuities into
165 * emulation mode and/or exception, NMI, reset
167 #define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be
168 * incorrect if data cache or DMA is active */
169 #define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1,
171 #define ANOMALY_05000125 /* Erroneous exception when enabling cache */
172 #define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect
174 #define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */
175 #define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill
176 * block in the loader file */
177 #define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an
179 #define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence
180 * of consecutive dual dag events */
181 #define ANOMALY_05000142 /* Interrupts may be lost when a programmable input
182 * flag is configured to be edge sensitive */
183 #define ANOMALY_05000143 /* A read from external memory may return a wrong
184 * value with data cache enabled */
185 #define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing
187 #define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to
188 * generate a waveform from PPI_CLK */
189 #define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor
191 #define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA
193 #define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory
194 * device, the upper 8-bits of each word must be
196 #define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */
197 #define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode
198 * outside of valid channels */
199 #define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a
200 * certain PPI mode is in use */
201 #define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to
202 * the next system MMR access thinking it should be
204 #define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame
205 * sync in certain conditions */
206 #define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
207 #define ANOMALY_05000169 /* DATA CPLB page miss can result in lost
208 * write-through cache data writes */
209 #define ANOMALY_05000173 /* DMA vs Core accesses to external memory */
210 #define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
211 #define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
212 #define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
213 * accumulator saturation */
214 #define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
216 #define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
217 #define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in
219 #define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs
221 #define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */
225 #endif /* _MACH_ANOMALY_H_ */