2 * linux/include/asm-arm/cacheflush.h
4 * Copyright (C) 1999-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef _ASMARM_CACHEFLUSH_H
11 #define _ASMARM_CACHEFLUSH_H
13 #include <linux/sched.h>
17 #include <asm/shmparam.h>
19 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
28 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) || \
29 defined(CONFIG_CPU_ARM740T)
31 # define MULTI_CACHE 1
37 #if defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM7TDMI)
39 # define MULTI_CACHE 1
45 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
46 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
47 # define MULTI_CACHE 1
50 #if defined(CONFIG_CPU_ARM926T)
52 # define MULTI_CACHE 1
54 # define _CACHE arm926
58 #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
60 # define MULTI_CACHE 1
66 #if defined(CONFIG_CPU_XSCALE)
68 # define MULTI_CACHE 1
70 # define _CACHE xscale
74 #if defined(CONFIG_CPU_XSC3)
76 # define MULTI_CACHE 1
82 #if defined(CONFIG_CPU_V6)
84 # define MULTI_CACHE 1
90 #if !defined(_CACHE) && !defined(MULTI_CACHE)
91 #error Unknown cache maintainence model
95 * This flag is used to indicate that the page pointed to by a pte
96 * is dirty and requires cleaning before returning it to the user.
98 #define PG_dcache_dirty PG_arch_1
101 * MM Cache Management
102 * ===================
104 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
105 * implement these methods.
107 * Start addresses are inclusive and end addresses are exclusive;
108 * start addresses should be rounded down, end addresses up.
110 * See Documentation/cachetlb.txt for more information.
111 * Please note that the implementation of these, and the required
112 * effects are cache-type (VIVT/VIPT/PIPT) specific.
114 * flush_cache_kern_all()
116 * Unconditionally clean and invalidate the entire cache.
118 * flush_cache_user_mm(mm)
120 * Clean and invalidate all user space cache entries
121 * before a change of page tables.
123 * flush_cache_user_range(start, end, flags)
125 * Clean and invalidate a range of cache entries in the
126 * specified address space before a change of page tables.
127 * - start - user start address (inclusive, page aligned)
128 * - end - user end address (exclusive, page aligned)
129 * - flags - vma->vm_flags field
131 * coherent_kern_range(start, end)
133 * Ensure coherency between the Icache and the Dcache in the
134 * region described by start, end. If you have non-snooping
135 * Harvard caches, you need to implement this function.
136 * - start - virtual start address
137 * - end - virtual end address
139 * DMA Cache Coherency
140 * ===================
142 * dma_inv_range(start, end)
144 * Invalidate (discard) the specified virtual address range.
145 * May not write back any entries. If 'start' or 'end'
146 * are not cache line aligned, those lines must be written
148 * - start - virtual start address
149 * - end - virtual end address
151 * dma_clean_range(start, end)
153 * Clean (write back) the specified virtual address range.
154 * - start - virtual start address
155 * - end - virtual end address
157 * dma_flush_range(start, end)
159 * Clean and invalidate the specified virtual address range.
160 * - start - virtual start address
161 * - end - virtual end address
164 struct cpu_cache_fns {
165 void (*flush_kern_all)(void);
166 void (*flush_user_all)(void);
167 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
169 void (*coherent_kern_range)(unsigned long, unsigned long);
170 void (*coherent_user_range)(unsigned long, unsigned long);
171 void (*flush_kern_dcache_page)(void *);
173 void (*dma_inv_range)(unsigned long, unsigned long);
174 void (*dma_clean_range)(unsigned long, unsigned long);
175 void (*dma_flush_range)(unsigned long, unsigned long);
179 * Select the calling method
183 extern struct cpu_cache_fns cpu_cache;
185 #define __cpuc_flush_kern_all cpu_cache.flush_kern_all
186 #define __cpuc_flush_user_all cpu_cache.flush_user_all
187 #define __cpuc_flush_user_range cpu_cache.flush_user_range
188 #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
189 #define __cpuc_coherent_user_range cpu_cache.coherent_user_range
190 #define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page
193 * These are private to the dma-mapping API. Do not use directly.
194 * Their sole purpose is to ensure that data held in the cache
195 * is visible to DMA, or data written by DMA to system memory is
196 * visible to the CPU.
198 #define dmac_inv_range cpu_cache.dma_inv_range
199 #define dmac_clean_range cpu_cache.dma_clean_range
200 #define dmac_flush_range cpu_cache.dma_flush_range
204 #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
205 #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
206 #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
207 #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
208 #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
209 #define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page)
211 extern void __cpuc_flush_kern_all(void);
212 extern void __cpuc_flush_user_all(void);
213 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
214 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
215 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
216 extern void __cpuc_flush_dcache_page(void *);
219 * These are private to the dma-mapping API. Do not use directly.
220 * Their sole purpose is to ensure that data held in the cache
221 * is visible to DMA, or data written by DMA to system memory is
222 * visible to the CPU.
224 #define dmac_inv_range __glue(_CACHE,_dma_inv_range)
225 #define dmac_clean_range __glue(_CACHE,_dma_clean_range)
226 #define dmac_flush_range __glue(_CACHE,_dma_flush_range)
228 extern void dmac_inv_range(unsigned long, unsigned long);
229 extern void dmac_clean_range(unsigned long, unsigned long);
230 extern void dmac_flush_range(unsigned long, unsigned long);
235 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
236 * vmalloc, ioremap etc) in kernel space for pages. Since the
237 * direct-mappings of these pages may contain cached data, we need
238 * to do a full cache flush to ensure that writebacks don't corrupt
239 * data placed into these pages via the new mappings.
241 #define flush_cache_vmap(start, end) flush_cache_all()
242 #define flush_cache_vunmap(start, end) flush_cache_all()
245 * Copy user data from/to a page which is mapped into a different
246 * processes address space. Really, we want to allow our "user
247 * space" model to handle this.
249 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
251 memcpy(dst, src, len); \
252 flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
255 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
257 memcpy(dst, src, len); \
261 * Convert calls to our calling convention.
263 #define flush_cache_all() __cpuc_flush_kern_all()
264 #ifndef CONFIG_CPU_CACHE_VIPT
265 static inline void flush_cache_mm(struct mm_struct *mm)
267 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
268 __cpuc_flush_user_all();
272 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
274 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
275 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
280 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
282 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
283 unsigned long addr = user_addr & PAGE_MASK;
284 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
289 flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
290 unsigned long uaddr, void *kaddr,
291 unsigned long len, int write)
293 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
294 unsigned long addr = (unsigned long)kaddr;
295 __cpuc_coherent_kern_range(addr, addr + len);
299 extern void flush_cache_mm(struct mm_struct *mm);
300 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
301 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
302 extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
303 unsigned long uaddr, void *kaddr,
304 unsigned long len, int write);
308 * flush_cache_user_range is used when we want to ensure that the
309 * Harvard caches are synchronised for the user space address range.
310 * This is used for the ARM private sys_cacheflush system call.
312 #define flush_cache_user_range(vma,start,end) \
313 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
316 * Perform necessary cache operations to ensure that data previously
317 * stored within this range of addresses can be executed by the CPU.
319 #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
322 * Perform necessary cache operations to ensure that the TLB will
323 * see data written in the specified area.
325 #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
328 * flush_dcache_page is used when the kernel has written to the page
329 * cache page at virtual address page->virtual.
331 * If this page isn't mapped (ie, page_mapping == NULL), or it might
332 * have userspace mappings, then we _must_ always clean + invalidate
333 * the dcache entries associated with the kernel mapping.
335 * Otherwise we can defer the operation, and clean the cache when we are
336 * about to change to user space. This is the same method as used on SPARC64.
337 * See update_mmu_cache for the user space part.
339 extern void flush_dcache_page(struct page *);
341 #define flush_dcache_mmap_lock(mapping) \
342 write_lock_irq(&(mapping)->tree_lock)
343 #define flush_dcache_mmap_unlock(mapping) \
344 write_unlock_irq(&(mapping)->tree_lock)
346 #define flush_icache_user_range(vma,page,addr,len) \
347 flush_dcache_page(page)
350 * We don't appear to need to do anything here. In fact, if we did, we'd
351 * duplicate cache flushing elsewhere performed by flush_dcache_page().
353 #define flush_icache_page(vma,page) do { } while (0)
355 #define __cacheid_present(val) (val != read_cpuid(CPUID_ID))
356 #define __cacheid_vivt(val) ((val & (15 << 25)) != (14 << 25))
357 #define __cacheid_vipt(val) ((val & (15 << 25)) == (14 << 25))
358 #define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
359 #define __cacheid_vipt_aliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
361 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
363 #define cache_is_vivt() 1
364 #define cache_is_vipt() 0
365 #define cache_is_vipt_nonaliasing() 0
366 #define cache_is_vipt_aliasing() 0
368 #elif defined(CONFIG_CPU_CACHE_VIPT)
370 #define cache_is_vivt() 0
371 #define cache_is_vipt() 1
372 #define cache_is_vipt_nonaliasing() \
374 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
375 __cacheid_vipt_nonaliasing(__val); \
378 #define cache_is_vipt_aliasing() \
380 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
381 __cacheid_vipt_aliasing(__val); \
386 #define cache_is_vivt() \
388 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
389 (!__cacheid_present(__val)) || __cacheid_vivt(__val); \
392 #define cache_is_vipt() \
394 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
395 __cacheid_present(__val) && __cacheid_vipt(__val); \
398 #define cache_is_vipt_nonaliasing() \
400 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
401 __cacheid_present(__val) && \
402 __cacheid_vipt_nonaliasing(__val); \
405 #define cache_is_vipt_aliasing() \
407 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
408 __cacheid_present(__val) && \
409 __cacheid_vipt_aliasing(__val); \