2 * linux/include/asm/arch-iop32x/iop321.h
4 * Intel IOP321 Chip definitions
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
20 * This is needed for mixed drivers that need to work on all
21 * IOP3xx variants but behave slightly differently on each.
24 #define iop_is_321() 1
28 * IOP321 chipset registers
30 #define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
31 #define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
32 #define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
34 /* Reserved 0x00000000 through 0x000000FF */
36 /* Address Translation Unit 0x00000100 through 0x000001FF */
38 /* Messaging Unit 0x00000300 through 0x000003FF */
40 /* Reserved 0x00000300 through 0x0000030c */
41 #define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310)
42 #define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314)
43 #define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318)
44 #define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C)
45 #define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320)
46 #define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324)
47 #define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328)
48 #define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C)
49 #define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330)
50 #define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334)
51 /* Reserved 0x00000338 through 0x0000034F */
52 #define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350)
53 #define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354)
54 /* Reserved 0x00000358 through 0x0000035C */
55 #define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360)
56 #define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364)
57 #define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368)
58 #define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C)
59 #define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370)
60 #define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374)
61 #define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378)
62 #define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
63 #define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380)
65 #define IOP321_IIxR_MASK 0x7f /* masks all */
66 #define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */
67 #define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */
68 #define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */
69 #define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */
70 #define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */
71 #define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */
72 #define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */
74 /* Reserved 0x00000384 through 0x000003FF */
76 /* DMA Controller 0x00000400 through 0x000004FF */
77 #define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400)
78 #define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404)
79 #define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C)
80 #define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410)
81 #define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414)
82 #define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)
83 #define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C)
84 #define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420)
85 #define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424)
86 /* Reserved 0x00000428 through 0x0000043C */
87 #define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440)
88 #define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444)
89 #define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C)
90 #define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450)
91 #define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454)
92 #define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)
93 #define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C)
94 #define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460)
95 #define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464)
96 /* Reserved 0x00000468 through 0x000004FF */
98 /* Memory controller 0x00000500 through 0x0005FF */
100 /* Peripheral bus interface unit 0x00000680 through 0x0006FF */
101 #define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680)
102 #define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684)
103 #define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688)
104 #define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C)
105 #define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690)
106 #define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694)
107 #define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698)
108 #define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C)
109 #define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0)
110 #define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4)
111 #define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8)
112 #define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC)
113 #define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0)
114 #define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4)
115 #define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8)
116 /* Reserved 0x000006BC */
117 #define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0)
118 /* Reserved 0x000006C4 through 0x000006DC */
119 #define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0)
120 #define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4)
122 #define IOP321_PBCR_EN 0x1
124 #define IOP321_PBISR_BOOR_ERR 0x1
126 /* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
127 #define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700)
128 #define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704)
129 #define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708)
130 /* reserved 0x00000070c */
131 #define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710)
132 /* PERC0 DOESN'T EXIST - index from 1! */
133 #define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710)
135 #define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */
137 /* Internal arbitration unit 0x00000780 through 0x0007BF */
138 #define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780)
139 #define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784)
140 #define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788)
142 /* General Purpose I/O Registers */
143 #define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
144 #define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
145 #define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
147 /* Interrupt Controller */
148 #define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
149 #define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
150 #define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
151 #define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
155 #define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0)
156 #define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4)
158 #ifdef CONFIG_ARCH_IQ80321
159 #define IOP321_TICK_RATE 200000000 /* 200 MHz clock */
160 #elif defined(CONFIG_ARCH_IQ31244)
161 #define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */
164 #ifdef CONFIG_ARCH_EP80219
165 #undef IOP321_TICK_RATE
166 #define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
169 #define IOP321_TMR_TC 0x01
170 #define IOP321_TMR_EN 0x02
171 #define IOP321_TMR_RELOAD 0x04
172 #define IOP321_TMR_PRIVILEGED 0x09
174 #define IOP321_TMR_RATIO_1_1 0x00
175 #define IOP321_TMR_RATIO_4_1 0x10
176 #define IOP321_TMR_RATIO_8_1 0x20
177 #define IOP321_TMR_RATIO_16_1 0x30
179 #define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8)
180 #define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC)
181 #define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0)
182 #define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4)
183 #define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8)
184 #define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC)
186 /* Application accelerator unit 0x00000800 - 0x000008FF */
187 #define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
188 #define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
189 #define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808)
190 #define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
191 #define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810)
192 #define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814)
193 #define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818)
194 #define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C)
195 #define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C)
196 #define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830)
197 #define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834)
198 #define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838)
199 #define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840)
200 #define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844)
201 #define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848)
202 #define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C)
203 #define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850)
204 #define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854)
205 #define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858)
206 #define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C)
207 #define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864)
208 #define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868)
209 #define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C)
210 #define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870)
211 #define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874)
212 #define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878)
213 #define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C)
214 #define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880)
215 #define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888)
216 #define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C)
217 #define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890)
218 #define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894)
219 #define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898)
220 #define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C)
221 #define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0)
222 #define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4)
223 #define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820)
224 #define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824)
225 #define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828)
226 #define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c)
227 #define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860)
228 #define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884)
231 /* SSP serial port unit 0x00001600 - 0x0000167F */
232 /* I2C bus interface unit 0x00001680 - 0x000016FF */
234 /* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
236 #include <asm/hardware/iop3xx.h>
240 extern void iop321_init_irq(void);
241 extern void iop321_time_init(void);
244 #endif // _IOP321_HW_H_