2 * (C) Copyright 2006-2009
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #ifndef _OMAP4430_SYS_H_
26 #define _OMAP4430_SYS_H_
28 #include <asm/arch/sizes.h>
31 * 4430 specific Section
34 /* Stuff on L3 Interconnect */
35 #define SMX_APE_BASE 0x68000000
38 #define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048)
39 #define A_READPERM0 (SMX_APE_BASE + 0x05050)
40 #define A_WRITEPERM0 (SMX_APE_BASE + 0x05058)
43 #define OMAP44XX_GPMC_BASE (0x50000000)
46 #define OMAP44XX_DMM_BASE 0x4E000000
49 #define OMAP44XX_SMS_BASE 0x6C000000
52 #define OMAP44XX_SDRC_BASE 0x6D000000
56 * L4 Peripherals - L4 Wakeup and L4 Core now
58 #define OMAP44XX_CORE_L4_IO_BASE 0x4A000000
60 #define OMAP44XX_WAKEUP_L4_IO_BASE 0x4A300000
62 #define OMAP44XX_L4_PER 0x48000000
64 #define OMAP44XX_L4_IO_BASE OMAP44XX_CORE_L4_IO_BASE
67 #define OMAP44XX_CTRL_GEN_CORE_BASE (OMAP44XX_L4_IO_BASE+0x2000)
68 #define OMAP44XX_CTRL_ID_CODE (OMAP44XX_CTRL_GEN_CORE_BASE + 0x204)
70 #define OMAP44XX_CTRL_BASE 0x4a100000
72 /* TAP information dont know for 3430*/
73 #define OMAP44XX_TAP_BASE (0x49000000) /*giving some junk for virtio */
76 #define OMAP44XX_UART1 (OMAP44XX_L4_PER+0x6a000)
77 #define OMAP44XX_UART2 (OMAP44XX_L4_PER+0x6c000)
78 #define OMAP44XX_UART3 (OMAP44XX_L4_PER+0x20000)
80 /* General Purpose Timers */
81 #define OMAP44XX_GPT1 0x48318000
82 #define OMAP44XX_GPT2 0x48032000
83 #define OMAP44XX_GPT3 0x48034000
84 #define OMAP44XX_GPT4 0x48036000
85 #define OMAP44XX_GPT5 0x40138000
86 #define OMAP44XX_GPT6 0x4013A000
87 #define OMAP44XX_GPT7 0x4013C000
88 #define OMAP44XX_GPT8 0x4013E000
89 #define OMAP44XX_GPT9 0x48040000
90 #define OMAP44XX_GPT10 0x48086000
91 #define OMAP44XX_GPT11 0x48088000
92 #define OMAP44XX_GPT12 0x48304000
94 /* WatchDog Timers (1 secure, 3 GP) */
95 #define WD1_BASE (0x4A322000)
96 #define WD2_BASE (0x4A314000)
97 #define WD3_BASE (0x40130000)
100 #define OMAP44XX_GPIO_BASE1 0x4a310000
101 #define OMAP44XX_GPIO_BASE2 0x48055000
104 #define SYNC_32KTIMER_BASE (0x48320000)
105 #define S32K_CR (SYNC_32KTIMER_BASE+0x10)
108 * SDP4430 specific Section
112 * The 443x's chip selects are programmable. The mask ROM
113 * does configure CS0 to 0x08000000 before dispatch. So, if
114 * you want your code to live below that address, you have to
115 * be prepared to jump though hoops, to reset the base address.
118 #ifdef CONFIG_OMAP44XX
119 /* base address for indirect vectors (internal boot mode) */
120 #define SRAM_OFFSET0 0x40000000
121 #define SRAM_OFFSET1 0x00300000
122 #define SRAM_OFFSET2 0x0000D000
123 #define SRAM_OFFSET3 0x00000800
124 #define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2|SRAM_OFFSET3)
125 #define LOW_LEVEL_SRAM_STACK 0x4030DFFC
128 #if defined(CONFIG_4430SDP)
129 /* FPGA on Debug board.*/
130 # define ETH_CONTROL_REG (DEBUG_BASE+0x30b)
131 # define LAN_RESET_REGISTER (DEBUG_BASE+0x1c)
133 # define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60)
134 # define LED_REGISTER (DEBUG_BASE+0x40)
135 # define FPGA_REV_REGISTER (DEBUG_BASE+0x10)
136 # define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800)
137 # define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900)
138 # define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00)
139 # define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00)
140 # define ENHANCED_UI_EE_NAME "750-2075"
143 #endif /* _OMAP4430_SYS_H_ */