drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
  27 #define DEBUG
  28 #endif
  29
  30 #ifdef DEBUG
  31 extern unsigned int dss_debug;
  32 #ifdef DSS_SUBSYS_NAME
  33 #define DSSDBG(format, ...) \
  34         if (dss_debug) \
  35                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
  36                 ## __VA_ARGS__)
  37 #else
  38 #define DSSDBG(format, ...) \
  39         if (dss_debug) \
  40                 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
  41 #endif
  42
  43 #ifdef DSS_SUBSYS_NAME
  44 #define DSSDBGF(format, ...) \
  45         if (dss_debug) \
  46                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
  47                                 ": %s(" format ")\n", \
  48                                 __func__, \
  49                                 ## __VA_ARGS__)
  50 #else
  51 #define DSSDBGF(format, ...) \
  52         if (dss_debug) \
  53                 printk(KERN_DEBUG "omapdss: " \
  54                                 ": %s(" format ")\n", \
  55                                 __func__, \
  56                                 ## __VA_ARGS__)
  57 #endif
  58
  59 #else /* DEBUG */
  60 #define DSSDBG(format, ...)
  61 #define DSSDBGF(format, ...)
  62 #endif
  63
  64
  65 #ifdef DSS_SUBSYS_NAME
  66 #define DSSERR(format, ...) \
  67         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  68         ## __VA_ARGS__)
  69 #else
  70 #define DSSERR(format, ...) \
  71         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  72 #endif
  73
  74 #ifdef DSS_SUBSYS_NAME
  75 #define DSSINFO(format, ...) \
  76         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  77         ## __VA_ARGS__)
  78 #else
  79 #define DSSINFO(format, ...) \
  80         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  81 #endif
  82
  83 #ifdef DSS_SUBSYS_NAME
  84 #define DSSWARN(format, ...) \
  85         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  86         ## __VA_ARGS__)
  87 #else
  88 #define DSSWARN(format, ...) \
  89         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  90 #endif
  91
  92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  93    number. For example 7:0 */
  94 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  97 #define FLD_MOD(orig, val, start, end) \
  98         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  99
 100 enum dss_io_pad_mode {
 101         DSS_IO_PAD_MODE_RESET,
 102         DSS_IO_PAD_MODE_RFBI,
 103         DSS_IO_PAD_MODE_BYPASS,
 104 };
 105
 106 enum dss_hdmi_venc_clk_source_select {
 107         DSS_VENC_TV_CLK = 0,
 108         DSS_HDMI_M_PCLK = 1,
 109 };
 110
 111 enum dss_dsi_content_type {
 112         DSS_DSI_CONTENT_DCS,
 113         DSS_DSI_CONTENT_GENERIC,
 114 };
 115
 116 struct dss_clock_info {
 117         /* rates that we get with dividers below */
 118         unsigned long fck;
 119
 120         /* dividers */
 121         u16 fck_div;
 122 };
 123
 124 struct dispc_clock_info {
 125         /* rates that we get with dividers below */
 126         unsigned long lck;
 127         unsigned long pck;
 128
 129         /* dividers */
 130         u16 lck_div;
 131         u16 pck_div;
 132 };
 133
 134 struct dsi_clock_info {
 135         /* rates that we get with dividers below */
 136         unsigned long fint;
 137         unsigned long clkin4ddr;
 138         unsigned long clkin;
 139         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 140                                                  * OMAP4: PLLx_CLK1 */
 141         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 142                                                  * OMAP4: PLLx_CLK2 */
 143         unsigned long lp_clk;
 144
 145         /* dividers */
 146         u16 regn;
 147         u16 regm;
 148         u16 regm_dispc; /* OMAP3: REGM3
 149                          * OMAP4: REGM4 */
 150         u16 regm_dsi;   /* OMAP3: REGM4
 151                          * OMAP4: REGM5 */
 152         u16 lp_clk_div;
 153
 154         u8 highfreq;
 155         bool use_sys_clk;
 156 };
 157
 158 enum hdmi_clk_refsel {
 159         HDMI_REFSEL_PCLK = 0,
 160         HDMI_REFSEL_REF1 = 1,
 161         HDMI_REFSEL_REF2 = 2,
 162         HDMI_REFSEL_SYSCLK = 3
 163 };
 164
 165 /* HDMI PLL structure */
 166 struct hdmi_pll_info {
 167         u16 regn;
 168         u16 regm;
 169         u32 regmf;
 170         u16 regm2;
 171         u16 regsd;
 172         u16 dcofreq;
 173         enum hdmi_clk_refsel refsel;
 174 };
 175
 176 struct seq_file;
 177 struct platform_device;
 178
 179 /* core */
 180 struct bus_type *dss_get_bus(void);
 181 struct regulator *dss_get_vdds_dsi(void);
 182 struct regulator *dss_get_vdds_sdi(void);
 183
 184 /* display */
 185 int dss_suspend_all_devices(void);
 186 int dss_resume_all_devices(void);
 187 void dss_disable_all_devices(void);
 188
 189 void dss_init_device(struct platform_device *pdev,
 190                 struct omap_dss_device *dssdev);
 191 void dss_uninit_device(struct platform_device *pdev,
 192                 struct omap_dss_device *dssdev);
 193 bool dss_use_replication(struct omap_dss_device *dssdev,
 194                 enum omap_color_mode mode);
 195 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 196                 u32 fifo_size, u32 burst_size,
 197                 u32 *fifo_low, u32 *fifo_high);
 198
 199 /* manager */
 200 int dss_init_overlay_managers(struct platform_device *pdev);
 201 void dss_uninit_overlay_managers(struct platform_device *pdev);
 202 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
 203 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 204                                 u16 *x, u16 *y, u16 *w, u16 *h,
 205                                 bool enlarge_update_area);
 206 void dss_start_update(struct omap_dss_device *dssdev);
 207
 208 /* overlay */
 209 void dss_init_overlays(struct platform_device *pdev);
 210 void dss_uninit_overlays(struct platform_device *pdev);
 211 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
 212 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 213 #ifdef L4_EXAMPLE
 214 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 215 #endif
 216 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
 217
 218 /* DSS */
 219 int dss_init_platform_driver(void);
 220 void dss_uninit_platform_driver(void);
 221
 222 int dss_runtime_get(void);
 223 void dss_runtime_put(void);
 224
 225 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 226 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 227 void dss_dump_clocks(struct seq_file *s);
 228
 229 void dss_dump_regs(struct seq_file *s);
 230 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 231 void dss_debug_dump_clocks(struct seq_file *s);
 232 #endif
 233
 234 void dss_sdi_init(u8 datapairs);
 235 int dss_sdi_enable(void);
 236 void dss_sdi_disable(void);
 237
 238 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
 239 void dss_select_dsi_clk_source(int dsi_module,
 240                 enum omap_dss_clk_source clk_src);
 241 void dss_select_lcd_clk_source(enum omap_channel channel,
 242                 enum omap_dss_clk_source clk_src);
 243 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 244 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 245 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 246
 247 void dss_set_venc_output(enum omap_dss_venc_type type);
 248 void dss_set_dac_pwrdn_bgz(bool enable);
 249
 250 unsigned long dss_get_dpll4_rate(void);
 251 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 252 int dss_set_clock_div(struct dss_clock_info *cinfo);
 253 int dss_get_clock_div(struct dss_clock_info *cinfo);
 254 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 255                 struct dss_clock_info *dss_cinfo,
 256                 struct dispc_clock_info *dispc_cinfo);
 257
 258 /* SDI */
 259 #ifdef CONFIG_OMAP2_DSS_SDI
 260 int sdi_init(void);
 261 void sdi_exit(void);
 262 int sdi_init_display(struct omap_dss_device *display);
 263 #else
 264 static inline int sdi_init(void)
 265 {
 266         return 0;
 267 }
 268 static inline void sdi_exit(void)
 269 {
 270 }
 271 #endif
 272
 273 /* DSI */
 274 #ifdef CONFIG_OMAP2_DSS_DSI
 275
 276 struct dentry;
 277 struct file_operations;
 278
 279 int dsi_init_platform_driver(void);
 280 void dsi_uninit_platform_driver(void);
 281
 282 int dsi_runtime_get(struct platform_device *dsidev);
 283 void dsi_runtime_put(struct platform_device *dsidev);
 284
 285 void dsi_dump_clocks(struct seq_file *s);
 286 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
 287                 const struct file_operations *debug_fops);
 288 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
 289                 const struct file_operations *debug_fops);
 290
 291 int dsi_init_display(struct omap_dss_device *display);
 292 void dsi_irq_handler(void);
 293 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 294
 295 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 296 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 297                 struct dsi_clock_info *cinfo);
 298 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
 299                 unsigned long req_pck, struct dsi_clock_info *cinfo,
 300                 struct dispc_clock_info *dispc_cinfo);
 301 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 302                 bool enable_hsdiv);
 303 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 304 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 305                 u32 fifo_size, u32 burst_size,
 306                 u32 *fifo_low, u32 *fifo_high);
 307 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 308 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 309 struct platform_device *dsi_get_dsidev_from_id(int module);
 310 #else
 311 static inline int dsi_init_platform_driver(void)
 312 {
 313         return 0;
 314 }
 315 static inline void dsi_uninit_platform_driver(void)
 316 {
 317 }
 318 static inline int dsi_runtime_get(struct platform_device *dsidev)
 319 {
 320         return 0;
 321 }
 322 static inline void dsi_runtime_put(struct platform_device *dsidev)
 323 {
 324 }
 325 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 326 {
 327         WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
 328         return 0;
 329 }
 330 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 331 {
 332         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 333         return 0;
 334 }
 335 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 336                 struct dsi_clock_info *cinfo)
 337 {
 338         WARN("%s: DSI not compiled in\n", __func__);
 339         return -ENODEV;
 340 }
 341 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
 342                 bool is_tft, unsigned long req_pck,
 343                 struct dsi_clock_info *dsi_cinfo,
 344                 struct dispc_clock_info *dispc_cinfo)
 345 {
 346         WARN("%s: DSI not compiled in\n", __func__);
 347         return -ENODEV;
 348 }
 349 static inline int dsi_pll_init(struct platform_device *dsidev,
 350                 bool enable_hsclk, bool enable_hsdiv)
 351 {
 352         WARN("%s: DSI not compiled in\n", __func__);
 353         return -ENODEV;
 354 }
 355 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 356                 bool disconnect_lanes)
 357 {
 358 }
 359 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 360 {
 361 }
 362 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 363 {
 364 }
 365 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 366 {
 367         WARN("%s: DSI not compiled in, returning platform device as NULL\n",
 368                         __func__);
 369         return NULL;
 370 }
 371 #endif
 372
 373 /* DPI */
 374 #ifdef CONFIG_OMAP2_DSS_DPI
 375 int dpi_init(void);
 376 void dpi_exit(void);
 377 int dpi_init_display(struct omap_dss_device *dssdev);
 378 #else
 379 static inline int dpi_init(void)
 380 {
 381         return 0;
 382 }
 383 static inline void dpi_exit(void)
 384 {
 385 }
 386 #endif
 387
 388 /* DISPC */
 389 int dispc_init_platform_driver(void);
 390 void dispc_uninit_platform_driver(void);
 391 void dispc_dump_clocks(struct seq_file *s);
 392 void dispc_dump_irqs(struct seq_file *s);
 393 void dispc_dump_regs(struct seq_file *s);
 394 void dispc_irq_handler(void);
 395 void dispc_fake_vsync_irq(void);
 396
 397 int dispc_runtime_get(void);
 398 void dispc_runtime_put(void);
 399
 400 void dispc_enable_sidle(void);
 401 void dispc_disable_sidle(void);
 402
 403 void dispc_lcd_enable_signal_polarity(bool act_high);
 404 void dispc_lcd_enable_signal(bool enable);
 405 void dispc_pck_free_enable(bool enable);
 406 void dispc_set_digit_size(u16 width, u16 height);
 407 void dispc_enable_fifomerge(bool enable);
 408 void dispc_enable_gamma_table(bool enable);
 409 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 410
 411 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
 412 unsigned long dispc_fclk_rate(void);
 413 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 414                 struct dispc_clock_info *cinfo);
 415 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 416                 struct dispc_clock_info *cinfo);
 417
 418
 419 u32 dispc_ovl_get_fifo_size(enum omap_plane plane);
 420 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 421 u32 dispc_ovl_get_burst_size(enum omap_plane plane);
 422 int dispc_ovl_setup(enum omap_plane plane,
 423                       u32 paddr, u16 screen_width,
 424                       u16 pos_x, u16 pos_y,
 425                       u16 width, u16 height,
 426                       u16 out_width, u16 out_height,
 427                       enum omap_color_mode color_mode,
 428                       bool ilace,
 429                       enum omap_dss_rotation_type rotation_type,
 430                       u8 rotation, bool mirror,
 431                       u8 global_alpha, u8 pre_mult_alpha,
 432                       enum omap_channel channel,
 433                       u32 puv_addr);
 434 int dispc_ovl_enable(enum omap_plane plane, bool enable);
 435 void dispc_ovl_enable_replication(enum omap_plane plane, bool enable);
 436
 437
 438 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable);
 439 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
 440 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable);
 441 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
 442                 struct omap_dss_cpr_coefs *coefs);
 443 bool dispc_mgr_go_busy(enum omap_channel channel);
 444 void dispc_mgr_go(enum omap_channel channel);
 445 void dispc_mgr_enable(enum omap_channel channel, bool enable);
 446 bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
 447 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode);
 448 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
 449 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
 450 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
 451                 enum omap_lcd_display_type type);
 452 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color);
 453 u32 dispc_mgr_get_default_color(enum omap_channel channel);
 454 void dispc_mgr_set_trans_key(enum omap_channel ch,
 455                 enum omap_dss_trans_key_type type,
 456                 u32 trans_key);
 457 void dispc_mgr_get_trans_key(enum omap_channel ch,
 458                 enum omap_dss_trans_key_type *type,
 459                 u32 *trans_key);
 460 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable);
 461 void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable);
 462 bool dispc_mgr_trans_key_enabled(enum omap_channel ch);
 463 bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch);
 464 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
 465                 struct omap_video_timings *timings);
 466 void dispc_mgr_set_pol_freq(enum omap_channel channel,
 467                 enum omap_panel_config config, u8 acbi, u8 acb);
 468 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 469 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 470 int dispc_mgr_set_clock_div(enum omap_channel channel,
 471                 struct dispc_clock_info *cinfo);
 472 int dispc_mgr_get_clock_div(enum omap_channel channel,
 473                 struct dispc_clock_info *cinfo);
 474
 475 /* VENC */
 476 #ifdef CONFIG_OMAP2_DSS_VENC
 477 int venc_init_platform_driver(void);
 478 void venc_uninit_platform_driver(void);
 479 void venc_dump_regs(struct seq_file *s);
 480 int venc_init_display(struct omap_dss_device *display);
 481 #else
 482 static inline int venc_init_platform_driver(void)
 483 {
 484         return 0;
 485 }
 486 static inline void venc_uninit_platform_driver(void)
 487 {
 488 }
 489 #endif
 490
 491 /* HDMI */
 492 #ifdef CONFIG_OMAP4_DSS_HDMI
 493 int hdmi_init_platform_driver(void);
 494 void hdmi_uninit_platform_driver(void);
 495 int hdmi_init_display(struct omap_dss_device *dssdev);
 496 #else
 497 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
 498 {
 499         return 0;
 500 }
 501 static inline int hdmi_init_platform_driver(void)
 502 {
 503         return 0;
 504 }
 505 static inline void hdmi_uninit_platform_driver(void)
 506 {
 507 }
 508 #endif
 509 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
 510 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
 511 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
 512 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 513                                         struct omap_video_timings *timings);
 514 int hdmi_panel_init(void);
 515 void hdmi_panel_exit(void);
 516
 517 /* RFBI */
 518 #ifdef CONFIG_OMAP2_DSS_RFBI
 519 int rfbi_init_platform_driver(void);
 520 void rfbi_uninit_platform_driver(void);
 521 void rfbi_dump_regs(struct seq_file *s);
 522 int rfbi_init_display(struct omap_dss_device *display);
 523 #else
 524 static inline int rfbi_init_platform_driver(void)
 525 {
 526         return 0;
 527 }
 528 static inline void rfbi_uninit_platform_driver(void)
 529 {
 530 }
 531 #endif
 532
 533
 534 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 535 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 536 {
 537         int b;
 538         for (b = 0; b < 32; ++b) {
 539                 if (irqstatus & (1 << b))
 540                         irq_arr[b]++;
 541         }
 542 }
 543 #endif
 544
 545 #endif