drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/err.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/clk.h>
  31
  32 #include <plat/display.h>
  33 #include <plat/clock.h>
  34 #include "dss.h"
  35 #include "dss_features.h"
  36
  37 #define DSS_SZ_REGS                     SZ_512
  38
  39 struct dss_reg {
  40         u16 idx;
  41 };
  42
  43 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  44
  45 #define DSS_REVISION                    DSS_REG(0x0000)
  46 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  47 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  48 #define DSS_IRQSTATUS                   DSS_REG(0x0018)
  49 #define DSS_CONTROL                     DSS_REG(0x0040)
  50 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  51 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  52 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  53
  54 #define REG_GET(idx, start, end) \
  55         FLD_GET(dss_read_reg(idx), start, end)
  56
  57 #define REG_FLD_MOD(idx, val, start, end) \
  58         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  59
  60 static struct {
  61         struct platform_device *pdev;
  62         void __iomem    *base;
  63         int             ctx_id;
  64
  65         struct clk      *dpll4_m4_ck;
  66         struct clk      *dss_ick;
  67         struct clk      *dss_fck;
  68         struct clk      *dss_sys_clk;
  69         struct clk      *dss_tv_fck;
  70         struct clk      *dss_video_fck;
  71         unsigned        num_clks_enabled;
  72
  73         unsigned long   cache_req_pck;
  74         unsigned long   cache_prate;
  75         struct dss_clock_info cache_dss_cinfo;
  76         struct dispc_clock_info cache_dispc_cinfo;
  77
  78         enum dss_clk_source dsi_clk_source;
  79         enum dss_clk_source dispc_clk_source;
  80         enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  81
  82         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  83 } dss;
  84
  85 static const char * const dss_generic_clk_source_names[] = {
  86         [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]       = "DSI_PLL_HSDIV_DISPC",
  87         [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]         = "DSI_PLL_HSDIV_DSI",
  88         [DSS_CLK_SRC_FCK]                       = "DSS_FCK",
  89 };
  90
  91 static void dss_clk_enable_all_no_ctx(void);
  92 static void dss_clk_disable_all_no_ctx(void);
  93 static void dss_clk_enable_no_ctx(enum dss_clock clks);
  94 static void dss_clk_disable_no_ctx(enum dss_clock clks);
  95
  96 static int _omap_dss_wait_reset(void);
  97
  98 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
  99 {
 100         __raw_writel(val, dss.base + idx.idx);
 101 }
 102
 103 static inline u32 dss_read_reg(const struct dss_reg idx)
 104 {
 105         return __raw_readl(dss.base + idx.idx);
 106 }
 107
 108 #define SR(reg) \
 109         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 110 #define RR(reg) \
 111         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 112
 113 void dss_save_context(void)
 114 {
 115         if (cpu_is_omap24xx())
 116                 return;
 117
 118         SR(SYSCONFIG);
 119         SR(CONTROL);
 120
 121         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 122                         OMAP_DISPLAY_TYPE_SDI) {
 123                 SR(SDI_CONTROL);
 124                 SR(PLL_CONTROL);
 125         }
 126 }
 127
 128 void dss_restore_context(void)
 129 {
 130         if (_omap_dss_wait_reset())
 131                 DSSERR("DSS not coming out of reset after sleep\n");
 132
 133         RR(SYSCONFIG);
 134         RR(CONTROL);
 135
 136         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 137                         OMAP_DISPLAY_TYPE_SDI) {
 138                 RR(SDI_CONTROL);
 139                 RR(PLL_CONTROL);
 140         }
 141 }
 142
 143 #undef SR
 144 #undef RR
 145
 146 void dss_sdi_init(u8 datapairs)
 147 {
 148         u32 l;
 149
 150         BUG_ON(datapairs > 3 || datapairs < 1);
 151
 152         l = dss_read_reg(DSS_SDI_CONTROL);
 153         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 154         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 155         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 156         dss_write_reg(DSS_SDI_CONTROL, l);
 157
 158         l = dss_read_reg(DSS_PLL_CONTROL);
 159         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 160         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 161         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 162         dss_write_reg(DSS_PLL_CONTROL, l);
 163 }
 164
 165 int dss_sdi_enable(void)
 166 {
 167         unsigned long timeout;
 168
 169         dispc_pck_free_enable(1);
 170
 171         /* Reset SDI PLL */
 172         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 173         udelay(1);      /* wait 2x PCLK */
 174
 175         /* Lock SDI PLL */
 176         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 177
 178         /* Waiting for PLL lock request to complete */
 179         timeout = jiffies + msecs_to_jiffies(500);
 180         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 181                 if (time_after_eq(jiffies, timeout)) {
 182                         DSSERR("PLL lock request timed out\n");
 183                         goto err1;
 184                 }
 185         }
 186
 187         /* Clearing PLL_GO bit */
 188         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 189
 190         /* Waiting for PLL to lock */
 191         timeout = jiffies + msecs_to_jiffies(500);
 192         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 193                 if (time_after_eq(jiffies, timeout)) {
 194                         DSSERR("PLL lock timed out\n");
 195                         goto err1;
 196                 }
 197         }
 198
 199         dispc_lcd_enable_signal(1);
 200
 201         /* Waiting for SDI reset to complete */
 202         timeout = jiffies + msecs_to_jiffies(500);
 203         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 204                 if (time_after_eq(jiffies, timeout)) {
 205                         DSSERR("SDI reset timed out\n");
 206                         goto err2;
 207                 }
 208         }
 209
 210         return 0;
 211
 212  err2:
 213         dispc_lcd_enable_signal(0);
 214  err1:
 215         /* Reset SDI PLL */
 216         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 217
 218         dispc_pck_free_enable(0);
 219
 220         return -ETIMEDOUT;
 221 }
 222
 223 void dss_sdi_disable(void)
 224 {
 225         dispc_lcd_enable_signal(0);
 226
 227         dispc_pck_free_enable(0);
 228
 229         /* Reset SDI PLL */
 230         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 231 }
 232
 233 const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
 234 {
 235         return dss_generic_clk_source_names[clk_src];
 236 }
 237
 238 void dss_dump_clocks(struct seq_file *s)
 239 {
 240         unsigned long dpll4_ck_rate;
 241         unsigned long dpll4_m4_ck_rate;
 242
 243         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 244
 245         dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 246         dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 247
 248         seq_printf(s, "- DSS -\n");
 249
 250         seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 251
 252         if (cpu_is_omap3630())
 253                 seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
 254                         dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
 255                         dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
 256                         dpll4_ck_rate,
 257                         dpll4_ck_rate / dpll4_m4_ck_rate,
 258                         dss_clk_get_rate(DSS_CLK_FCK));
 259         else
 260                 seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
 261                         dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
 262                         dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
 263                         dpll4_ck_rate,
 264                         dpll4_ck_rate / dpll4_m4_ck_rate,
 265                         dss_clk_get_rate(DSS_CLK_FCK));
 266
 267         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 268 }
 269
 270 void dss_dump_regs(struct seq_file *s)
 271 {
 272 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 273
 274         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 275
 276         DUMPREG(DSS_REVISION);
 277         DUMPREG(DSS_SYSCONFIG);
 278         DUMPREG(DSS_SYSSTATUS);
 279         DUMPREG(DSS_IRQSTATUS);
 280         DUMPREG(DSS_CONTROL);
 281
 282         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 283                         OMAP_DISPLAY_TYPE_SDI) {
 284                 DUMPREG(DSS_SDI_CONTROL);
 285                 DUMPREG(DSS_PLL_CONTROL);
 286                 DUMPREG(DSS_SDI_STATUS);
 287         }
 288
 289         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 290 #undef DUMPREG
 291 }
 292
 293 void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
 294 {
 295         int b;
 296         u8 start, end;
 297
 298         switch (clk_src) {
 299         case DSS_CLK_SRC_FCK:
 300                 b = 0;
 301                 break;
 302         case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 303                 b = 1;
 304                 dsi_wait_pll_hsdiv_dispc_active();
 305                 break;
 306         default:
 307                 BUG();
 308         }
 309
 310         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 311
 312         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 313
 314         dss.dispc_clk_source = clk_src;
 315 }
 316
 317 void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
 318 {
 319         int b;
 320
 321         switch (clk_src) {
 322         case DSS_CLK_SRC_FCK:
 323                 b = 0;
 324                 break;
 325         case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 326                 b = 1;
 327                 dsi_wait_pll_hsdiv_dsi_active();
 328                 break;
 329         default:
 330                 BUG();
 331         }
 332
 333         REG_FLD_MOD(DSS_CONTROL, b, 1, 1);      /* DSI_CLK_SWITCH */
 334
 335         dss.dsi_clk_source = clk_src;
 336 }
 337
 338 void dss_select_lcd_clk_source(enum omap_channel channel,
 339                 enum dss_clk_source clk_src)
 340 {
 341         int b, ix, pos;
 342
 343         if (!dss_has_feature(FEAT_LCD_CLK_SRC))
 344                 return;
 345
 346         switch (clk_src) {
 347         case DSS_CLK_SRC_FCK:
 348                 b = 0;
 349                 break;
 350         case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 351                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 352                 b = 1;
 353                 dsi_wait_pll_hsdiv_dispc_active();
 354                 break;
 355         default:
 356                 BUG();
 357         }
 358
 359         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
 360         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 361
 362         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 363         dss.lcd_clk_source[ix] = clk_src;
 364 }
 365
 366 enum dss_clk_source dss_get_dispc_clk_source(void)
 367 {
 368         return dss.dispc_clk_source;
 369 }
 370
 371 enum dss_clk_source dss_get_dsi_clk_source(void)
 372 {
 373         return dss.dsi_clk_source;
 374 }
 375
 376 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 377 {
 378         int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 379         return dss.lcd_clk_source[ix];
 380 }
 381
 382 /* calculate clock rates using dividers in cinfo */
 383 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 384 {
 385         unsigned long prate;
 386
 387         if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
 388                                                 cinfo->fck_div == 0)
 389                 return -EINVAL;
 390
 391         prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 392
 393         cinfo->fck = prate / cinfo->fck_div;
 394
 395         return 0;
 396 }
 397
 398 int dss_set_clock_div(struct dss_clock_info *cinfo)
 399 {
 400         unsigned long prate;
 401         int r;
 402
 403         if (cpu_is_omap34xx()) {
 404                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 405                 DSSDBG("dpll4_m4 = %ld\n", prate);
 406
 407                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 408                 if (r)
 409                         return r;
 410         }
 411
 412         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 413
 414         return 0;
 415 }
 416
 417 int dss_get_clock_div(struct dss_clock_info *cinfo)
 418 {
 419         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
 420
 421         if (cpu_is_omap34xx()) {
 422                 unsigned long prate;
 423                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 424                 if (cpu_is_omap3630())
 425                         cinfo->fck_div = prate / (cinfo->fck);
 426                 else
 427                         cinfo->fck_div = prate / (cinfo->fck / 2);
 428         } else {
 429                 cinfo->fck_div = 0;
 430         }
 431
 432         return 0;
 433 }
 434
 435 unsigned long dss_get_dpll4_rate(void)
 436 {
 437         if (cpu_is_omap34xx())
 438                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 439         else
 440                 return 0;
 441 }
 442
 443 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 444                 struct dss_clock_info *dss_cinfo,
 445                 struct dispc_clock_info *dispc_cinfo)
 446 {
 447         unsigned long prate;
 448         struct dss_clock_info best_dss;
 449         struct dispc_clock_info best_dispc;
 450
 451         unsigned long fck, max_dss_fck;
 452
 453         u16 fck_div;
 454
 455         int match = 0;
 456         int min_fck_per_pck;
 457
 458         prate = dss_get_dpll4_rate();
 459
 460         max_dss_fck = dss_feat_get_max_dss_fck();
 461
 462         fck = dss_clk_get_rate(DSS_CLK_FCK);
 463         if (req_pck == dss.cache_req_pck &&
 464                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
 465                          dss.cache_dss_cinfo.fck == fck)) {
 466                 DSSDBG("dispc clock info found from cache.\n");
 467                 *dss_cinfo = dss.cache_dss_cinfo;
 468                 *dispc_cinfo = dss.cache_dispc_cinfo;
 469                 return 0;
 470         }
 471
 472         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 473
 474         if (min_fck_per_pck &&
 475                 req_pck * min_fck_per_pck > max_dss_fck) {
 476                 DSSERR("Requested pixel clock not possible with the current "
 477                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 478                                 "the constraint off.\n");
 479                 min_fck_per_pck = 0;
 480         }
 481
 482 retry:
 483         memset(&best_dss, 0, sizeof(best_dss));
 484         memset(&best_dispc, 0, sizeof(best_dispc));
 485
 486         if (cpu_is_omap24xx()) {
 487                 struct dispc_clock_info cur_dispc;
 488                 /* XXX can we change the clock on omap2? */
 489                 fck = dss_clk_get_rate(DSS_CLK_FCK);
 490                 fck_div = 1;
 491
 492                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 493                 match = 1;
 494
 495                 best_dss.fck = fck;
 496                 best_dss.fck_div = fck_div;
 497
 498                 best_dispc = cur_dispc;
 499
 500                 goto found;
 501         } else if (cpu_is_omap34xx()) {
 502                 for (fck_div = (cpu_is_omap3630() ? 32 : 16);
 503                                         fck_div > 0; --fck_div) {
 504                         struct dispc_clock_info cur_dispc;
 505
 506                         if (cpu_is_omap3630())
 507                                 fck = prate / fck_div;
 508                         else
 509                                 fck = prate / fck_div * 2;
 510
 511                         if (fck > max_dss_fck)
 512                                 continue;
 513
 514                         if (min_fck_per_pck &&
 515                                         fck < req_pck * min_fck_per_pck)
 516                                 continue;
 517
 518                         match = 1;
 519
 520                         dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 521
 522                         if (abs(cur_dispc.pck - req_pck) <
 523                                         abs(best_dispc.pck - req_pck)) {
 524
 525                                 best_dss.fck = fck;
 526                                 best_dss.fck_div = fck_div;
 527
 528                                 best_dispc = cur_dispc;
 529
 530                                 if (cur_dispc.pck == req_pck)
 531                                         goto found;
 532                         }
 533                 }
 534         } else {
 535                 BUG();
 536         }
 537
 538 found:
 539         if (!match) {
 540                 if (min_fck_per_pck) {
 541                         DSSERR("Could not find suitable clock settings.\n"
 542                                         "Turning FCK/PCK constraint off and"
 543                                         "trying again.\n");
 544                         min_fck_per_pck = 0;
 545                         goto retry;
 546                 }
 547
 548                 DSSERR("Could not find suitable clock settings.\n");
 549
 550                 return -EINVAL;
 551         }
 552
 553         if (dss_cinfo)
 554                 *dss_cinfo = best_dss;
 555         if (dispc_cinfo)
 556                 *dispc_cinfo = best_dispc;
 557
 558         dss.cache_req_pck = req_pck;
 559         dss.cache_prate = prate;
 560         dss.cache_dss_cinfo = best_dss;
 561         dss.cache_dispc_cinfo = best_dispc;
 562
 563         return 0;
 564 }
 565
 566 static int _omap_dss_wait_reset(void)
 567 {
 568         int t = 0;
 569
 570         while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
 571                 if (++t > 1000) {
 572                         DSSERR("soft reset failed\n");
 573                         return -ENODEV;
 574                 }
 575                 udelay(1);
 576         }
 577
 578         return 0;
 579 }
 580
 581 static int _omap_dss_reset(void)
 582 {
 583         /* Soft reset */
 584         REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
 585         return _omap_dss_wait_reset();
 586 }
 587
 588 void dss_set_venc_output(enum omap_dss_venc_type type)
 589 {
 590         int l = 0;
 591
 592         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 593                 l = 0;
 594         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 595                 l = 1;
 596         else
 597                 BUG();
 598
 599         /* venc out selection. 0 = comp, 1 = svideo */
 600         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 601 }
 602
 603 void dss_set_dac_pwrdn_bgz(bool enable)
 604 {
 605         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 606 }
 607
 608 static int dss_init(void)
 609 {
 610         int r;
 611         u32 rev;
 612         struct resource *dss_mem;
 613
 614         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 615         if (!dss_mem) {
 616                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 617                 r = -EINVAL;
 618                 goto fail0;
 619         }
 620         dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
 621         if (!dss.base) {
 622                 DSSERR("can't ioremap DSS\n");
 623                 r = -ENOMEM;
 624                 goto fail0;
 625         }
 626
 627         /* disable LCD and DIGIT output. This seems to fix the synclost
 628          * problem that we get, if the bootloader starts the DSS and
 629          * the kernel resets it */
 630         omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
 631
 632         /* We need to wait here a bit, otherwise we sometimes start to
 633          * get synclost errors, and after that only power cycle will
 634          * restore DSS functionality. I have no idea why this happens.
 635          * And we have to wait _before_ resetting the DSS, but after
 636          * enabling clocks.
 637          */
 638         msleep(50);
 639
 640         _omap_dss_reset();
 641
 642         /* autoidle */
 643         REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
 644
 645         /* Select DPLL */
 646         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 647
 648 #ifdef CONFIG_OMAP2_DSS_VENC
 649         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 650         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 651         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 652 #endif
 653
 654         if (cpu_is_omap34xx()) {
 655                 dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
 656                 if (IS_ERR(dss.dpll4_m4_ck)) {
 657                         DSSERR("Failed to get dpll4_m4_ck\n");
 658                         r = PTR_ERR(dss.dpll4_m4_ck);
 659                         goto fail1;
 660                 }
 661         }
 662
 663         dss.dsi_clk_source = DSS_CLK_SRC_FCK;
 664         dss.dispc_clk_source = DSS_CLK_SRC_FCK;
 665         dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
 666         dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
 667
 668         dss_save_context();
 669
 670         rev = dss_read_reg(DSS_REVISION);
 671         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 672                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 673
 674         return 0;
 675
 676 fail1:
 677         iounmap(dss.base);
 678 fail0:
 679         return r;
 680 }
 681
 682 static void dss_exit(void)
 683 {
 684         if (cpu_is_omap34xx())
 685                 clk_put(dss.dpll4_m4_ck);
 686
 687         iounmap(dss.base);
 688 }
 689
 690 /* CONTEXT */
 691 static int dss_get_ctx_id(void)
 692 {
 693         struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
 694         int r;
 695
 696         if (!pdata->board_data->get_last_off_on_transaction_id)
 697                 return 0;
 698         r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev);
 699         if (r < 0) {
 700                 dev_err(&dss.pdev->dev, "getting transaction ID failed, "
 701                                 "will force context restore\n");
 702                 r = -1;
 703         }
 704         return r;
 705 }
 706
 707 int dss_need_ctx_restore(void)
 708 {
 709         int id = dss_get_ctx_id();
 710
 711         if (id < 0 || id != dss.ctx_id) {
 712                 DSSDBG("ctx id %d -> id %d\n",
 713                                 dss.ctx_id, id);
 714                 dss.ctx_id = id;
 715                 return 1;
 716         } else {
 717                 return 0;
 718         }
 719 }
 720
 721 static void save_all_ctx(void)
 722 {
 723         DSSDBG("save context\n");
 724
 725         dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
 726
 727         dss_save_context();
 728         dispc_save_context();
 729 #ifdef CONFIG_OMAP2_DSS_DSI
 730         dsi_save_context();
 731 #endif
 732
 733         dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
 734 }
 735
 736 static void restore_all_ctx(void)
 737 {
 738         DSSDBG("restore context\n");
 739
 740         dss_clk_enable_all_no_ctx();
 741
 742         dss_restore_context();
 743         dispc_restore_context();
 744 #ifdef CONFIG_OMAP2_DSS_DSI
 745         dsi_restore_context();
 746 #endif
 747
 748         dss_clk_disable_all_no_ctx();
 749 }
 750
 751 static int dss_get_clock(struct clk **clock, const char *clk_name)
 752 {
 753         struct clk *clk;
 754
 755         clk = clk_get(&dss.pdev->dev, clk_name);
 756
 757         if (IS_ERR(clk)) {
 758                 DSSERR("can't get clock %s", clk_name);
 759                 return PTR_ERR(clk);
 760         }
 761
 762         *clock = clk;
 763
 764         DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
 765
 766         return 0;
 767 }
 768
 769 static int dss_get_clocks(void)
 770 {
 771         int r;
 772         struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
 773
 774         dss.dss_ick = NULL;
 775         dss.dss_fck = NULL;
 776         dss.dss_sys_clk = NULL;
 777         dss.dss_tv_fck = NULL;
 778         dss.dss_video_fck = NULL;
 779
 780         r = dss_get_clock(&dss.dss_ick, "ick");
 781         if (r)
 782                 goto err;
 783
 784         r = dss_get_clock(&dss.dss_fck, "fck");
 785         if (r)
 786                 goto err;
 787
 788         if (!pdata->opt_clock_available) {
 789                 r = -ENODEV;
 790                 goto err;
 791         }
 792
 793         if (pdata->opt_clock_available("sys_clk")) {
 794                 r = dss_get_clock(&dss.dss_sys_clk, "sys_clk");
 795                 if (r)
 796                         goto err;
 797         }
 798
 799         if (pdata->opt_clock_available("tv_clk")) {
 800                 r = dss_get_clock(&dss.dss_tv_fck, "tv_clk");
 801                 if (r)
 802                         goto err;
 803         }
 804
 805         if (pdata->opt_clock_available("video_clk")) {
 806                 r = dss_get_clock(&dss.dss_video_fck, "video_clk");
 807                 if (r)
 808                         goto err;
 809         }
 810
 811         return 0;
 812
 813 err:
 814         if (dss.dss_ick)
 815                 clk_put(dss.dss_ick);
 816         if (dss.dss_fck)
 817                 clk_put(dss.dss_fck);
 818         if (dss.dss_sys_clk)
 819                 clk_put(dss.dss_sys_clk);
 820         if (dss.dss_tv_fck)
 821                 clk_put(dss.dss_tv_fck);
 822         if (dss.dss_video_fck)
 823                 clk_put(dss.dss_video_fck);
 824
 825         return r;
 826 }
 827
 828 static void dss_put_clocks(void)
 829 {
 830         if (dss.dss_video_fck)
 831                 clk_put(dss.dss_video_fck);
 832         if (dss.dss_tv_fck)
 833                 clk_put(dss.dss_tv_fck);
 834         if (dss.dss_sys_clk)
 835                 clk_put(dss.dss_sys_clk);
 836         clk_put(dss.dss_fck);
 837         clk_put(dss.dss_ick);
 838 }
 839
 840 unsigned long dss_clk_get_rate(enum dss_clock clk)
 841 {
 842         switch (clk) {
 843         case DSS_CLK_ICK:
 844                 return clk_get_rate(dss.dss_ick);
 845         case DSS_CLK_FCK:
 846                 return clk_get_rate(dss.dss_fck);
 847         case DSS_CLK_SYSCK:
 848                 return clk_get_rate(dss.dss_sys_clk);
 849         case DSS_CLK_TVFCK:
 850                 return clk_get_rate(dss.dss_tv_fck);
 851         case DSS_CLK_VIDFCK:
 852                 return clk_get_rate(dss.dss_video_fck);
 853         }
 854
 855         BUG();
 856         return 0;
 857 }
 858
 859 static unsigned count_clk_bits(enum dss_clock clks)
 860 {
 861         unsigned num_clks = 0;
 862
 863         if (clks & DSS_CLK_ICK)
 864                 ++num_clks;
 865         if (clks & DSS_CLK_FCK)
 866                 ++num_clks;
 867         if (clks & DSS_CLK_SYSCK)
 868                 ++num_clks;
 869         if (clks & DSS_CLK_TVFCK)
 870                 ++num_clks;
 871         if (clks & DSS_CLK_VIDFCK)
 872                 ++num_clks;
 873
 874         return num_clks;
 875 }
 876
 877 static void dss_clk_enable_no_ctx(enum dss_clock clks)
 878 {
 879         unsigned num_clks = count_clk_bits(clks);
 880
 881         if (clks & DSS_CLK_ICK)
 882                 clk_enable(dss.dss_ick);
 883         if (clks & DSS_CLK_FCK)
 884                 clk_enable(dss.dss_fck);
 885         if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
 886                 clk_enable(dss.dss_sys_clk);
 887         if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
 888                 clk_enable(dss.dss_tv_fck);
 889         if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
 890                 clk_enable(dss.dss_video_fck);
 891
 892         dss.num_clks_enabled += num_clks;
 893 }
 894
 895 void dss_clk_enable(enum dss_clock clks)
 896 {
 897         bool check_ctx = dss.num_clks_enabled == 0;
 898
 899         dss_clk_enable_no_ctx(clks);
 900
 901         /*
 902          * HACK: On omap4 the registers may not be accessible right after
 903          * enabling the clocks. At some point this will be handled by
 904          * pm_runtime, but for the time begin this should make things work.
 905          */
 906         if (cpu_is_omap44xx() && check_ctx)
 907                 udelay(10);
 908
 909         if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
 910                 restore_all_ctx();
 911 }
 912
 913 static void dss_clk_disable_no_ctx(enum dss_clock clks)
 914 {
 915         unsigned num_clks = count_clk_bits(clks);
 916
 917         if (clks & DSS_CLK_ICK)
 918                 clk_disable(dss.dss_ick);
 919         if (clks & DSS_CLK_FCK)
 920                 clk_disable(dss.dss_fck);
 921         if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
 922                 clk_disable(dss.dss_sys_clk);
 923         if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
 924                 clk_disable(dss.dss_tv_fck);
 925         if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
 926                 clk_disable(dss.dss_video_fck);
 927
 928         dss.num_clks_enabled -= num_clks;
 929 }
 930
 931 void dss_clk_disable(enum dss_clock clks)
 932 {
 933         if (cpu_is_omap34xx()) {
 934                 unsigned num_clks = count_clk_bits(clks);
 935
 936                 BUG_ON(dss.num_clks_enabled < num_clks);
 937
 938                 if (dss.num_clks_enabled == num_clks)
 939                         save_all_ctx();
 940         }
 941
 942         dss_clk_disable_no_ctx(clks);
 943 }
 944
 945 static void dss_clk_enable_all_no_ctx(void)
 946 {
 947         enum dss_clock clks;
 948
 949         clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
 950         if (cpu_is_omap34xx())
 951                 clks |= DSS_CLK_VIDFCK;
 952         dss_clk_enable_no_ctx(clks);
 953 }
 954
 955 static void dss_clk_disable_all_no_ctx(void)
 956 {
 957         enum dss_clock clks;
 958
 959         clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
 960         if (cpu_is_omap34xx())
 961                 clks |= DSS_CLK_VIDFCK;
 962         dss_clk_disable_no_ctx(clks);
 963 }
 964
 965 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 966 /* CLOCKS */
 967 static void core_dump_clocks(struct seq_file *s)
 968 {
 969         int i;
 970         struct clk *clocks[5] = {
 971                 dss.dss_ick,
 972                 dss.dss_fck,
 973                 dss.dss_sys_clk,
 974                 dss.dss_tv_fck,
 975                 dss.dss_video_fck
 976         };
 977
 978         seq_printf(s, "- CORE -\n");
 979
 980         seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
 981
 982         for (i = 0; i < 5; i++) {
 983                 if (!clocks[i])
 984                         continue;
 985                 seq_printf(s, "%-15s\t%lu\t%d\n",
 986                                 clocks[i]->name,
 987                                 clk_get_rate(clocks[i]),
 988                                 clocks[i]->usecount);
 989         }
 990 }
 991 #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
 992
 993 /* DEBUGFS */
 994 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 995 void dss_debug_dump_clocks(struct seq_file *s)
 996 {
 997         core_dump_clocks(s);
 998         dss_dump_clocks(s);
 999         dispc_dump_clocks(s);
1000 #ifdef CONFIG_OMAP2_DSS_DSI
1001         dsi_dump_clocks(s);
1002 #endif
1003 }
1004 #endif
1005
1006
1007 /* DSS HW IP initialisation */
1008 static int omap_dsshw_probe(struct platform_device *pdev)
1009 {
1010         int r;
1011
1012         dss.pdev = pdev;
1013
1014         r = dss_get_clocks();
1015         if (r)
1016                 goto err_clocks;
1017
1018         dss_clk_enable_all_no_ctx();
1019
1020         dss.ctx_id = dss_get_ctx_id();
1021         DSSDBG("initial ctx id %u\n", dss.ctx_id);
1022
1023         r = dss_init();
1024         if (r) {
1025                 DSSERR("Failed to initialize DSS\n");
1026                 goto err_dss;
1027         }
1028
1029         r = dpi_init();
1030         if (r) {
1031                 DSSERR("Failed to initialize DPI\n");
1032                 goto err_dpi;
1033         }
1034
1035         r = sdi_init();
1036         if (r) {
1037                 DSSERR("Failed to initialize SDI\n");
1038                 goto err_sdi;
1039         }
1040
1041         dss_clk_disable_all_no_ctx();
1042         return 0;
1043 err_sdi:
1044         dpi_exit();
1045 err_dpi:
1046         dss_exit();
1047 err_dss:
1048         dss_clk_disable_all_no_ctx();
1049         dss_put_clocks();
1050 err_clocks:
1051         return r;
1052 }
1053
1054 static int omap_dsshw_remove(struct platform_device *pdev)
1055 {
1056
1057         dss_exit();
1058
1059         /*
1060          * As part of hwmod changes, DSS is not the only controller of dss
1061          * clocks; hwmod framework itself will also enable clocks during hwmod
1062          * init for dss, and autoidle is set in h/w for DSS. Hence, there's no
1063          * need to disable clocks if their usecounts > 1.
1064          */
1065         WARN_ON(dss.num_clks_enabled > 0);
1066
1067         dss_put_clocks();
1068         return 0;
1069 }
1070
1071 static struct platform_driver omap_dsshw_driver = {
1072         .probe          = omap_dsshw_probe,
1073         .remove         = omap_dsshw_remove,
1074         .driver         = {
1075                 .name   = "omapdss_dss",
1076                 .owner  = THIS_MODULE,
1077         },
1078 };
1079
1080 int dss_init_platform_driver(void)
1081 {
1082         return platform_driver_register(&omap_dsshw_driver);
1083 }
1084
1085 void dss_uninit_platform_driver(void)
1086 {
1087         return platform_driver_unregister(&omap_dsshw_driver);
1088 }