2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
37 #include <plat/display.h>
38 #include <plat/clock.h>
41 #include "dss_features.h"
43 /*#define VERBOSE_IRQ*/
44 #define DSI_CATCH_MISSING_TE
46 struct dsi_reg { u16 idx; };
48 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
50 #define DSI_SZ_REGS SZ_1K
51 /* DSI Protocol Engine */
53 #define DSI_REVISION DSI_REG(0x0000)
54 #define DSI_SYSCONFIG DSI_REG(0x0010)
55 #define DSI_SYSSTATUS DSI_REG(0x0014)
56 #define DSI_IRQSTATUS DSI_REG(0x0018)
57 #define DSI_IRQENABLE DSI_REG(0x001C)
58 #define DSI_CTRL DSI_REG(0x0040)
59 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
60 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
61 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
62 #define DSI_CLK_CTRL DSI_REG(0x0054)
63 #define DSI_TIMING1 DSI_REG(0x0058)
64 #define DSI_TIMING2 DSI_REG(0x005C)
65 #define DSI_VM_TIMING1 DSI_REG(0x0060)
66 #define DSI_VM_TIMING2 DSI_REG(0x0064)
67 #define DSI_VM_TIMING3 DSI_REG(0x0068)
68 #define DSI_CLK_TIMING DSI_REG(0x006C)
69 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
70 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
71 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
72 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
73 #define DSI_VM_TIMING4 DSI_REG(0x0080)
74 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
75 #define DSI_VM_TIMING5 DSI_REG(0x0088)
76 #define DSI_VM_TIMING6 DSI_REG(0x008C)
77 #define DSI_VM_TIMING7 DSI_REG(0x0090)
78 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
79 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
80 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
83 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
84 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
85 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
89 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
90 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
91 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
92 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
94 /* DSI_PLL_CTRL_SCP */
96 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
97 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
98 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
99 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
100 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
102 #define REG_GET(idx, start, end) \
103 FLD_GET(dsi_read_reg(idx), start, end)
105 #define REG_FLD_MOD(idx, val, start, end) \
106 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
108 /* Global interrupts */
109 #define DSI_IRQ_VC0 (1 << 0)
110 #define DSI_IRQ_VC1 (1 << 1)
111 #define DSI_IRQ_VC2 (1 << 2)
112 #define DSI_IRQ_VC3 (1 << 3)
113 #define DSI_IRQ_WAKEUP (1 << 4)
114 #define DSI_IRQ_RESYNC (1 << 5)
115 #define DSI_IRQ_PLL_LOCK (1 << 7)
116 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
117 #define DSI_IRQ_PLL_RECALL (1 << 9)
118 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
119 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
120 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
121 #define DSI_IRQ_TE_TRIGGER (1 << 16)
122 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
123 #define DSI_IRQ_SYNC_LOST (1 << 18)
124 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
125 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
126 #define DSI_IRQ_ERROR_MASK \
127 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
129 #define DSI_IRQ_CHANNEL_MASK 0xf
131 /* Virtual channel interrupts */
132 #define DSI_VC_IRQ_CS (1 << 0)
133 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
134 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
135 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
136 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
137 #define DSI_VC_IRQ_BTA (1 << 5)
138 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
139 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
140 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
141 #define DSI_VC_IRQ_ERROR_MASK \
142 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
143 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
144 DSI_VC_IRQ_FIFO_TX_UDF)
146 /* ComplexIO interrupts */
147 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
148 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
149 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
150 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
151 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
152 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
153 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
154 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
155 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
156 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
157 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
158 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
159 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
160 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
161 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
162 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
163 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
164 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
165 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
166 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
167 #define DSI_CIO_IRQ_ERROR_MASK \
168 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
169 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
170 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
171 DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
172 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
173 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
174 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
176 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
177 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
178 #define DSI_DT_DCS_READ 0x06
179 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
180 #define DSI_DT_NULL_PACKET 0x09
181 #define DSI_DT_DCS_LONG_WRITE 0x39
183 #define DSI_DT_RX_ACK_WITH_ERR 0x02
184 #define DSI_DT_RX_DCS_LONG_READ 0x1c
185 #define DSI_DT_RX_SHORT_READ_1 0x21
186 #define DSI_DT_RX_SHORT_READ_2 0x22
188 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
190 #define DSI_MAX_NR_ISRS 2
192 struct dsi_isr_data {
200 DSI_FIFO_SIZE_32 = 1,
201 DSI_FIFO_SIZE_64 = 2,
202 DSI_FIFO_SIZE_96 = 3,
203 DSI_FIFO_SIZE_128 = 4,
211 struct dsi_update_region {
213 struct omap_dss_device *device;
216 struct dsi_irq_stats {
217 unsigned long last_reset;
219 unsigned dsi_irqs[32];
220 unsigned vc_irqs[4][32];
221 unsigned cio_irqs[32];
224 struct dsi_isr_tables {
225 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
226 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
227 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
232 struct platform_device *pdev;
236 struct dsi_clock_info current_cinfo;
238 struct regulator *vdds_dsi_reg;
241 enum dsi_vc_mode mode;
242 struct omap_dss_device *dssdev;
243 enum fifo_size fifo_size;
248 struct semaphore bus_lock;
252 void (*bta_callback)(void);
255 struct dsi_isr_tables isr_tables;
256 /* space for a copy used by the interrupt handler */
257 struct dsi_isr_tables isr_tables_copy;
260 struct dsi_update_region update_region;
264 struct workqueue_struct *workqueue;
266 void (*framedone_callback)(int, void *);
267 void *framedone_data;
269 struct delayed_work framedone_timeout_work;
271 #ifdef DSI_CATCH_MISSING_TE
272 struct timer_list te_timer;
275 unsigned long cache_req_pck;
276 unsigned long cache_clk_freq;
277 struct dsi_clock_info cache_cinfo;
280 spinlock_t errors_lock;
282 ktime_t perf_setup_time;
283 ktime_t perf_start_time;
288 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
289 spinlock_t irq_stats_lock;
290 struct dsi_irq_stats irq_stats;
292 /* DSI PLL Parameter Ranges */
293 unsigned long regm_max, regn_max;
294 unsigned long regm_dispc_max, regm_dsi_max;
295 unsigned long fint_min, fint_max;
296 unsigned long lpdiv_max;
300 static unsigned int dsi_perf;
301 module_param_named(dsi_perf, dsi_perf, bool, 0644);
304 static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
306 __raw_writel(val, dsi.base + idx.idx);
309 static inline u32 dsi_read_reg(const struct dsi_reg idx)
311 return __raw_readl(dsi.base + idx.idx);
315 void dsi_save_context(void)
319 void dsi_restore_context(void)
323 void dsi_bus_lock(void)
327 EXPORT_SYMBOL(dsi_bus_lock);
329 void dsi_bus_unlock(void)
333 EXPORT_SYMBOL(dsi_bus_unlock);
335 static bool dsi_bus_is_locked(void)
337 return dsi.bus_lock.count == 0;
340 static void dsi_completion_handler(void *data, u32 mask)
342 complete((struct completion *)data);
345 static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
350 while (REG_GET(idx, bitnum, bitnum) != value) {
359 static void dsi_perf_mark_setup(void)
361 dsi.perf_setup_time = ktime_get();
364 static void dsi_perf_mark_start(void)
366 dsi.perf_start_time = ktime_get();
369 static void dsi_perf_show(const char *name)
371 ktime_t t, setup_time, trans_time;
373 u32 setup_us, trans_us, total_us;
380 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
381 setup_us = (u32)ktime_to_us(setup_time);
385 trans_time = ktime_sub(t, dsi.perf_start_time);
386 trans_us = (u32)ktime_to_us(trans_time);
390 total_us = setup_us + trans_us;
392 total_bytes = dsi.update_region.w *
393 dsi.update_region.h *
394 dsi.update_region.device->ctrl.pixel_size / 8;
396 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
397 "%u bytes, %u kbytes/sec\n",
402 1000*1000 / total_us,
404 total_bytes * 1000 / total_us);
407 #define dsi_perf_mark_setup()
408 #define dsi_perf_mark_start()
409 #define dsi_perf_show(x)
412 static void print_irq_status(u32 status)
415 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
418 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
421 if (status & DSI_IRQ_##x) \
447 static void print_irq_status_vc(int channel, u32 status)
450 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
453 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
456 if (status & DSI_VC_IRQ_##x) \
473 static void print_irq_status_cio(u32 status)
475 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
478 if (status & DSI_CIO_IRQ_##x) \
492 PIS(ERRCONTENTIONLP0_1);
493 PIS(ERRCONTENTIONLP1_1);
494 PIS(ERRCONTENTIONLP0_2);
495 PIS(ERRCONTENTIONLP1_2);
496 PIS(ERRCONTENTIONLP0_3);
497 PIS(ERRCONTENTIONLP1_3);
498 PIS(ULPSACTIVENOT_ALL0);
499 PIS(ULPSACTIVENOT_ALL1);
505 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
506 static void dsi_collect_irq_stats(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
510 spin_lock(&dsi.irq_stats_lock);
512 dsi.irq_stats.irq_count++;
513 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
515 for (i = 0; i < 4; ++i)
516 dss_collect_irq_stats(vcstatus[i], dsi.irq_stats.vc_irqs[i]);
518 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
520 spin_unlock(&dsi.irq_stats_lock);
523 #define dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus)
526 static int debug_irq;
528 static void dsi_handle_irq_errors(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
532 if (irqstatus & DSI_IRQ_ERROR_MASK) {
533 DSSERR("DSI error, irqstatus %x\n", irqstatus);
534 print_irq_status(irqstatus);
535 spin_lock(&dsi.errors_lock);
536 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
537 spin_unlock(&dsi.errors_lock);
538 } else if (debug_irq) {
539 print_irq_status(irqstatus);
542 for (i = 0; i < 4; ++i) {
543 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
544 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
546 print_irq_status_vc(i, vcstatus[i]);
547 } else if (debug_irq) {
548 print_irq_status_vc(i, vcstatus[i]);
552 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
553 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
554 print_irq_status_cio(ciostatus);
555 } else if (debug_irq) {
556 print_irq_status_cio(ciostatus);
560 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
561 unsigned isr_array_size, u32 irqstatus)
563 struct dsi_isr_data *isr_data;
566 for (i = 0; i < isr_array_size; i++) {
567 isr_data = &isr_array[i];
568 if (isr_data->isr && isr_data->mask & irqstatus)
569 isr_data->isr(isr_data->arg, irqstatus);
573 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
574 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
578 dsi_call_isrs(isr_tables->isr_table,
579 ARRAY_SIZE(isr_tables->isr_table),
582 for (i = 0; i < 4; ++i) {
583 if (vcstatus[i] == 0)
585 dsi_call_isrs(isr_tables->isr_table_vc[i],
586 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
591 dsi_call_isrs(isr_tables->isr_table_cio,
592 ARRAY_SIZE(isr_tables->isr_table_cio),
596 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
598 u32 irqstatus, vcstatus[4], ciostatus;
601 spin_lock(&dsi.irq_lock);
603 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
605 /* IRQ is not for us */
607 spin_unlock(&dsi.irq_lock);
611 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
612 /* flush posted write */
613 dsi_read_reg(DSI_IRQSTATUS);
615 for (i = 0; i < 4; ++i) {
616 if ((irqstatus & (1 << i)) == 0) {
621 vcstatus[i] = dsi_read_reg(DSI_VC_IRQSTATUS(i));
623 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus[i]);
624 /* flush posted write */
625 dsi_read_reg(DSI_VC_IRQSTATUS(i));
628 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
629 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
631 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
632 /* flush posted write */
633 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
638 #ifdef DSI_CATCH_MISSING_TE
639 if (irqstatus & DSI_IRQ_TE_TRIGGER)
640 del_timer(&dsi.te_timer);
643 for (i = 0; i < 4; ++i) {
644 if (vcstatus[i] == 0)
647 if (vcstatus[i] & DSI_VC_IRQ_BTA) {
648 if (dsi.bta_callback)
653 /* make a copy and unlock, so that isrs can unregister
655 memcpy(&dsi.isr_tables_copy, &dsi.isr_tables, sizeof(dsi.isr_tables));
657 spin_unlock(&dsi.irq_lock);
659 dsi_handle_isrs(&dsi.isr_tables_copy, irqstatus, vcstatus, ciostatus);
661 dsi_handle_irq_errors(irqstatus, vcstatus, ciostatus);
663 dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus);
668 /* dsi.irq_lock has to be locked by the caller */
669 static void _omap_dsi_configure_irqs(struct dsi_isr_data *isr_array,
670 unsigned isr_array_size, u32 default_mask,
671 const struct dsi_reg enable_reg,
672 const struct dsi_reg status_reg)
674 struct dsi_isr_data *isr_data;
681 for (i = 0; i < isr_array_size; i++) {
682 isr_data = &isr_array[i];
684 if (isr_data->isr == NULL)
687 mask |= isr_data->mask;
690 old_mask = dsi_read_reg(enable_reg);
691 /* clear the irqstatus for newly enabled irqs */
692 dsi_write_reg(status_reg, (mask ^ old_mask) & mask);
693 dsi_write_reg(enable_reg, mask);
695 /* flush posted writes */
696 dsi_read_reg(enable_reg);
697 dsi_read_reg(status_reg);
700 /* dsi.irq_lock has to be locked by the caller */
701 static void _omap_dsi_set_irqs(void)
703 u32 mask = DSI_IRQ_ERROR_MASK;
704 #ifdef DSI_CATCH_MISSING_TE
705 mask |= DSI_IRQ_TE_TRIGGER;
707 _omap_dsi_configure_irqs(dsi.isr_tables.isr_table,
708 ARRAY_SIZE(dsi.isr_tables.isr_table), mask,
709 DSI_IRQENABLE, DSI_IRQSTATUS);
712 /* dsi.irq_lock has to be locked by the caller */
713 static void _omap_dsi_set_irqs_vc(int vc)
715 _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_vc[vc],
716 ARRAY_SIZE(dsi.isr_tables.isr_table_vc[vc]),
717 DSI_VC_IRQ_ERROR_MASK,
718 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
721 /* dsi.irq_lock has to be locked by the caller */
722 static void _omap_dsi_set_irqs_cio(void)
724 _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_cio,
725 ARRAY_SIZE(dsi.isr_tables.isr_table_cio),
726 DSI_CIO_IRQ_ERROR_MASK,
727 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
730 static void _dsi_initialize_irq(void)
735 spin_lock_irqsave(&dsi.irq_lock, flags);
737 memset(&dsi.isr_tables, 0, sizeof(dsi.isr_tables));
739 _omap_dsi_set_irqs();
740 for (vc = 0; vc < 4; ++vc)
741 _omap_dsi_set_irqs_vc(vc);
742 _omap_dsi_set_irqs_cio();
744 spin_unlock_irqrestore(&dsi.irq_lock, flags);
747 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
748 struct dsi_isr_data *isr_array, unsigned isr_array_size)
750 struct dsi_isr_data *isr_data;
756 /* check for duplicate entry and find a free slot */
758 for (i = 0; i < isr_array_size; i++) {
759 isr_data = &isr_array[i];
761 if (isr_data->isr == isr && isr_data->arg == arg &&
762 isr_data->mask == mask) {
766 if (isr_data->isr == NULL && free_idx == -1)
773 isr_data = &isr_array[free_idx];
776 isr_data->mask = mask;
781 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
782 struct dsi_isr_data *isr_array, unsigned isr_array_size)
784 struct dsi_isr_data *isr_data;
787 for (i = 0; i < isr_array_size; i++) {
788 isr_data = &isr_array[i];
789 if (isr_data->isr != isr || isr_data->arg != arg ||
790 isr_data->mask != mask)
793 isr_data->isr = NULL;
794 isr_data->arg = NULL;
803 static int dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
808 spin_lock_irqsave(&dsi.irq_lock, flags);
810 r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table,
811 ARRAY_SIZE(dsi.isr_tables.isr_table));
814 _omap_dsi_set_irqs();
816 spin_unlock_irqrestore(&dsi.irq_lock, flags);
821 static int dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
826 spin_lock_irqsave(&dsi.irq_lock, flags);
828 r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table,
829 ARRAY_SIZE(dsi.isr_tables.isr_table));
832 _omap_dsi_set_irqs();
834 spin_unlock_irqrestore(&dsi.irq_lock, flags);
839 static int dsi_register_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
845 spin_lock_irqsave(&dsi.irq_lock, flags);
847 r = _dsi_register_isr(isr, arg, mask,
848 dsi.isr_tables.isr_table_vc[channel],
849 ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
852 _omap_dsi_set_irqs_vc(channel);
854 spin_unlock_irqrestore(&dsi.irq_lock, flags);
859 static int dsi_unregister_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
865 spin_lock_irqsave(&dsi.irq_lock, flags);
867 r = _dsi_unregister_isr(isr, arg, mask,
868 dsi.isr_tables.isr_table_vc[channel],
869 ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
872 _omap_dsi_set_irqs_vc(channel);
874 spin_unlock_irqrestore(&dsi.irq_lock, flags);
879 static int dsi_register_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
884 spin_lock_irqsave(&dsi.irq_lock, flags);
886 r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
887 ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
890 _omap_dsi_set_irqs_cio();
892 spin_unlock_irqrestore(&dsi.irq_lock, flags);
897 static int dsi_unregister_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
902 spin_lock_irqsave(&dsi.irq_lock, flags);
904 r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
905 ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
908 _omap_dsi_set_irqs_cio();
910 spin_unlock_irqrestore(&dsi.irq_lock, flags);
915 static u32 dsi_get_errors(void)
919 spin_lock_irqsave(&dsi.errors_lock, flags);
922 spin_unlock_irqrestore(&dsi.errors_lock, flags);
926 static void dsi_vc_enable_bta_irq(int channel)
930 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
932 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
934 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
937 static void dsi_vc_disable_bta_irq(int channel)
941 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
942 l &= ~DSI_VC_IRQ_BTA;
943 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
946 /* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */
947 static inline void enable_clocks(bool enable)
950 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
952 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
955 /* source clock for DSI PLL. this could also be PCLKFREE */
956 static inline void dsi_enable_pll_clock(bool enable)
959 dss_clk_enable(DSS_CLK_SYSCK);
961 dss_clk_disable(DSS_CLK_SYSCK);
963 if (enable && dsi.pll_locked) {
964 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
965 DSSERR("cannot lock PLL when enabling clocks\n");
970 static void _dsi_print_reset_status(void)
977 /* A dummy read using the SCP interface to any DSIPHY register is
978 * required after DSIPHY reset to complete the reset of the DSI complex
980 l = dsi_read_reg(DSI_DSIPHY_CFG5);
982 printk(KERN_DEBUG "DSI resets: ");
984 l = dsi_read_reg(DSI_PLL_STATUS);
985 printk("PLL (%d) ", FLD_GET(l, 0, 0));
987 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
988 printk("CIO (%d) ", FLD_GET(l, 29, 29));
990 l = dsi_read_reg(DSI_DSIPHY_CFG5);
991 printk("PHY (%x, %d, %d, %d)\n",
998 #define _dsi_print_reset_status()
1001 static inline int dsi_if_enable(bool enable)
1003 DSSDBG("dsi_if_enable(%d)\n", enable);
1005 enable = enable ? 1 : 0;
1006 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
1008 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
1009 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1016 unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
1018 return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk;
1021 static unsigned long dsi_get_pll_hsdiv_dsi_rate(void)
1023 return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk;
1026 static unsigned long dsi_get_txbyteclkhs(void)
1028 return dsi.current_cinfo.clkin4ddr / 16;
1031 static unsigned long dsi_fclk_rate(void)
1035 if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {
1036 /* DSI FCLK source is DSS_CLK_FCK */
1037 r = dss_clk_get_rate(DSS_CLK_FCK);
1039 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1040 r = dsi_get_pll_hsdiv_dsi_rate();
1046 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1048 unsigned long dsi_fclk;
1049 unsigned lp_clk_div;
1050 unsigned long lp_clk;
1052 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
1054 if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max)
1057 dsi_fclk = dsi_fclk_rate();
1059 lp_clk = dsi_fclk / 2 / lp_clk_div;
1061 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1062 dsi.current_cinfo.lp_clk = lp_clk;
1063 dsi.current_cinfo.lp_clk_div = lp_clk_div;
1065 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
1067 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
1068 21, 21); /* LP_RX_SYNCHRO_ENABLE */
1074 enum dsi_pll_power_state {
1075 DSI_PLL_POWER_OFF = 0x0,
1076 DSI_PLL_POWER_ON_HSCLK = 0x1,
1077 DSI_PLL_POWER_ON_ALL = 0x2,
1078 DSI_PLL_POWER_ON_DIV = 0x3,
1081 static int dsi_pll_power(enum dsi_pll_power_state state)
1085 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
1087 /* PLL_PWR_STATUS */
1088 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
1090 DSSERR("Failed to set DSI PLL power mode to %d\n",
1100 /* calculate clock rates using dividers in cinfo */
1101 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1102 struct dsi_clock_info *cinfo)
1104 if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max)
1107 if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max)
1110 if (cinfo->regm_dispc > dsi.regm_dispc_max)
1113 if (cinfo->regm_dsi > dsi.regm_dsi_max)
1116 if (cinfo->use_sys_clk) {
1117 cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
1118 /* XXX it is unclear if highfreq should be used
1119 * with DSS_SYS_CLK source also */
1120 cinfo->highfreq = 0;
1122 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
1124 if (cinfo->clkin < 32000000)
1125 cinfo->highfreq = 0;
1127 cinfo->highfreq = 1;
1130 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1132 if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min)
1135 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1137 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1140 if (cinfo->regm_dispc > 0)
1141 cinfo->dsi_pll_hsdiv_dispc_clk =
1142 cinfo->clkin4ddr / cinfo->regm_dispc;
1144 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1146 if (cinfo->regm_dsi > 0)
1147 cinfo->dsi_pll_hsdiv_dsi_clk =
1148 cinfo->clkin4ddr / cinfo->regm_dsi;
1150 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1155 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
1156 struct dsi_clock_info *dsi_cinfo,
1157 struct dispc_clock_info *dispc_cinfo)
1159 struct dsi_clock_info cur, best;
1160 struct dispc_clock_info best_dispc;
1161 int min_fck_per_pck;
1163 unsigned long dss_sys_clk, max_dss_fck;
1165 dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK);
1167 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1169 if (req_pck == dsi.cache_req_pck &&
1170 dsi.cache_cinfo.clkin == dss_sys_clk) {
1171 DSSDBG("DSI clock info found from cache\n");
1172 *dsi_cinfo = dsi.cache_cinfo;
1173 dispc_find_clk_divs(is_tft, req_pck,
1174 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1178 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1180 if (min_fck_per_pck &&
1181 req_pck * min_fck_per_pck > max_dss_fck) {
1182 DSSERR("Requested pixel clock not possible with the current "
1183 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1184 "the constraint off.\n");
1185 min_fck_per_pck = 0;
1188 DSSDBG("dsi_pll_calc\n");
1191 memset(&best, 0, sizeof(best));
1192 memset(&best_dispc, 0, sizeof(best_dispc));
1194 memset(&cur, 0, sizeof(cur));
1195 cur.clkin = dss_sys_clk;
1196 cur.use_sys_clk = 1;
1199 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1200 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1201 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1202 for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) {
1203 if (cur.highfreq == 0)
1204 cur.fint = cur.clkin / cur.regn;
1206 cur.fint = cur.clkin / (2 * cur.regn);
1208 if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min)
1211 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1212 for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) {
1215 a = 2 * cur.regm * (cur.clkin/1000);
1216 b = cur.regn * (cur.highfreq + 1);
1217 cur.clkin4ddr = a / b * 1000;
1219 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1222 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1223 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1224 for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max;
1226 struct dispc_clock_info cur_dispc;
1227 cur.dsi_pll_hsdiv_dispc_clk =
1228 cur.clkin4ddr / cur.regm_dispc;
1230 /* this will narrow down the search a bit,
1231 * but still give pixclocks below what was
1233 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1236 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1239 if (min_fck_per_pck &&
1240 cur.dsi_pll_hsdiv_dispc_clk <
1241 req_pck * min_fck_per_pck)
1246 dispc_find_clk_divs(is_tft, req_pck,
1247 cur.dsi_pll_hsdiv_dispc_clk,
1250 if (abs(cur_dispc.pck - req_pck) <
1251 abs(best_dispc.pck - req_pck)) {
1253 best_dispc = cur_dispc;
1255 if (cur_dispc.pck == req_pck)
1263 if (min_fck_per_pck) {
1264 DSSERR("Could not find suitable clock settings.\n"
1265 "Turning FCK/PCK constraint off and"
1267 min_fck_per_pck = 0;
1271 DSSERR("Could not find suitable clock settings.\n");
1276 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1278 best.dsi_pll_hsdiv_dsi_clk = 0;
1283 *dispc_cinfo = best_dispc;
1285 dsi.cache_req_pck = req_pck;
1286 dsi.cache_clk_freq = 0;
1287 dsi.cache_cinfo = best;
1292 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
1297 u8 regn_start, regn_end, regm_start, regm_end;
1298 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1302 dsi.current_cinfo.fint = cinfo->fint;
1303 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1304 dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk =
1305 cinfo->dsi_pll_hsdiv_dispc_clk;
1306 dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk =
1307 cinfo->dsi_pll_hsdiv_dsi_clk;
1309 dsi.current_cinfo.regn = cinfo->regn;
1310 dsi.current_cinfo.regm = cinfo->regm;
1311 dsi.current_cinfo.regm_dispc = cinfo->regm_dispc;
1312 dsi.current_cinfo.regm_dsi = cinfo->regm_dsi;
1314 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1316 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1317 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1321 /* DSIPHY == CLKIN4DDR */
1322 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1326 cinfo->highfreq + 1,
1329 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1330 cinfo->clkin4ddr / 1000 / 1000 / 2);
1332 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1334 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1335 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1336 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1337 cinfo->dsi_pll_hsdiv_dispc_clk);
1338 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1339 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1340 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1341 cinfo->dsi_pll_hsdiv_dsi_clk);
1343 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1344 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1345 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1347 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1350 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1352 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1353 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1355 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1357 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1359 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1360 regm_dispc_start, regm_dispc_end);
1361 /* DSIPROTO_CLOCK_DIV */
1362 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1363 regm_dsi_start, regm_dsi_end);
1364 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1366 BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max);
1367 if (cinfo->fint < 1000000)
1369 else if (cinfo->fint < 1250000)
1371 else if (cinfo->fint < 1500000)
1373 else if (cinfo->fint < 1750000)
1378 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1379 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1380 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1381 11, 11); /* DSI_PLL_CLKSEL */
1382 l = FLD_MOD(l, cinfo->highfreq,
1383 12, 12); /* DSI_PLL_HIGHFREQ */
1384 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1385 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1386 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1387 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1389 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1391 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1392 DSSERR("dsi pll go bit not going down.\n");
1397 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1398 DSSERR("cannot lock PLL\n");
1405 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1406 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1407 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1408 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1409 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1410 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1411 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1412 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1413 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1414 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1415 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1416 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1417 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1418 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1419 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1420 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1422 DSSDBG("PLL config done\n");
1427 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1431 enum dsi_pll_power_state pwstate;
1433 DSSDBG("PLL init\n");
1435 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
1437 * HACK: this is just a quick hack to get the USE_DSI_PLL
1438 * option working. USE_DSI_PLL is itself a big hack, and
1439 * should be removed.
1441 if (dsi.vdds_dsi_reg == NULL) {
1442 struct regulator *vdds_dsi;
1444 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
1446 if (IS_ERR(vdds_dsi)) {
1447 DSSERR("can't get VDDS_DSI regulator\n");
1448 return PTR_ERR(vdds_dsi);
1451 dsi.vdds_dsi_reg = vdds_dsi;
1456 dsi_enable_pll_clock(1);
1458 r = regulator_enable(dsi.vdds_dsi_reg);
1462 /* XXX PLL does not come out of reset without this... */
1463 dispc_pck_free_enable(1);
1465 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1466 DSSERR("PLL not coming out of reset.\n");
1468 dispc_pck_free_enable(0);
1472 /* XXX ... but if left on, we get problems when planes do not
1473 * fill the whole display. No idea about this */
1474 dispc_pck_free_enable(0);
1476 if (enable_hsclk && enable_hsdiv)
1477 pwstate = DSI_PLL_POWER_ON_ALL;
1478 else if (enable_hsclk)
1479 pwstate = DSI_PLL_POWER_ON_HSCLK;
1480 else if (enable_hsdiv)
1481 pwstate = DSI_PLL_POWER_ON_DIV;
1483 pwstate = DSI_PLL_POWER_OFF;
1485 r = dsi_pll_power(pwstate);
1490 DSSDBG("PLL init done\n");
1494 regulator_disable(dsi.vdds_dsi_reg);
1497 dsi_enable_pll_clock(0);
1501 void dsi_pll_uninit(void)
1504 dsi_enable_pll_clock(0);
1507 dsi_pll_power(DSI_PLL_POWER_OFF);
1508 regulator_disable(dsi.vdds_dsi_reg);
1509 DSSDBG("PLL uninit done\n");
1512 void dsi_dump_clocks(struct seq_file *s)
1515 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1516 enum dss_clk_source dispc_clk_src, dsi_clk_src;
1518 dispc_clk_src = dss_get_dispc_clk_source();
1519 dsi_clk_src = dss_get_dsi_clk_source();
1523 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1525 seq_printf(s, "- DSI PLL -\n");
1527 seq_printf(s, "dsi pll source = %s\n",
1529 "dss_sys_clk" : "pclkfree");
1531 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1533 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1534 cinfo->clkin4ddr, cinfo->regm);
1536 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1537 dss_get_generic_clk_source_name(dispc_clk_src),
1538 dss_feat_get_clk_source_name(dispc_clk_src),
1539 cinfo->dsi_pll_hsdiv_dispc_clk,
1541 dispc_clk_src == DSS_CLK_SRC_FCK ?
1544 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1545 dss_get_generic_clk_source_name(dsi_clk_src),
1546 dss_feat_get_clk_source_name(dsi_clk_src),
1547 cinfo->dsi_pll_hsdiv_dsi_clk,
1549 dsi_clk_src == DSS_CLK_SRC_FCK ?
1552 seq_printf(s, "- DSI -\n");
1554 seq_printf(s, "dsi fclk source = %s (%s)\n",
1555 dss_get_generic_clk_source_name(dsi_clk_src),
1556 dss_feat_get_clk_source_name(dsi_clk_src));
1558 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1560 seq_printf(s, "DDR_CLK\t\t%lu\n",
1561 cinfo->clkin4ddr / 4);
1563 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1565 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1567 seq_printf(s, "VP_CLK\t\t%lu\n"
1569 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
1570 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
1575 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1576 void dsi_dump_irqs(struct seq_file *s)
1578 unsigned long flags;
1579 struct dsi_irq_stats stats;
1581 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1583 stats = dsi.irq_stats;
1584 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1585 dsi.irq_stats.last_reset = jiffies;
1587 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1589 seq_printf(s, "period %u ms\n",
1590 jiffies_to_msecs(jiffies - stats.last_reset));
1592 seq_printf(s, "irqs %d\n", stats.irq_count);
1594 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1596 seq_printf(s, "-- DSI interrupts --\n");
1612 PIS(LDO_POWER_GOOD);
1617 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1618 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1619 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1620 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1621 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1623 seq_printf(s, "-- VC interrupts --\n");
1632 PIS(PP_BUSY_CHANGE);
1636 seq_printf(s, "%-20s %10d\n", #x, \
1637 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1639 seq_printf(s, "-- CIO interrupts --\n");
1652 PIS(ERRCONTENTIONLP0_1);
1653 PIS(ERRCONTENTIONLP1_1);
1654 PIS(ERRCONTENTIONLP0_2);
1655 PIS(ERRCONTENTIONLP1_2);
1656 PIS(ERRCONTENTIONLP0_3);
1657 PIS(ERRCONTENTIONLP1_3);
1658 PIS(ULPSACTIVENOT_ALL0);
1659 PIS(ULPSACTIVENOT_ALL1);
1664 void dsi_dump_regs(struct seq_file *s)
1666 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1668 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
1670 DUMPREG(DSI_REVISION);
1671 DUMPREG(DSI_SYSCONFIG);
1672 DUMPREG(DSI_SYSSTATUS);
1673 DUMPREG(DSI_IRQSTATUS);
1674 DUMPREG(DSI_IRQENABLE);
1676 DUMPREG(DSI_COMPLEXIO_CFG1);
1677 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1678 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1679 DUMPREG(DSI_CLK_CTRL);
1680 DUMPREG(DSI_TIMING1);
1681 DUMPREG(DSI_TIMING2);
1682 DUMPREG(DSI_VM_TIMING1);
1683 DUMPREG(DSI_VM_TIMING2);
1684 DUMPREG(DSI_VM_TIMING3);
1685 DUMPREG(DSI_CLK_TIMING);
1686 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1687 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1688 DUMPREG(DSI_COMPLEXIO_CFG2);
1689 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1690 DUMPREG(DSI_VM_TIMING4);
1691 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1692 DUMPREG(DSI_VM_TIMING5);
1693 DUMPREG(DSI_VM_TIMING6);
1694 DUMPREG(DSI_VM_TIMING7);
1695 DUMPREG(DSI_STOPCLK_TIMING);
1697 DUMPREG(DSI_VC_CTRL(0));
1698 DUMPREG(DSI_VC_TE(0));
1699 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1700 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1701 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1702 DUMPREG(DSI_VC_IRQSTATUS(0));
1703 DUMPREG(DSI_VC_IRQENABLE(0));
1705 DUMPREG(DSI_VC_CTRL(1));
1706 DUMPREG(DSI_VC_TE(1));
1707 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1708 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1709 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1710 DUMPREG(DSI_VC_IRQSTATUS(1));
1711 DUMPREG(DSI_VC_IRQENABLE(1));
1713 DUMPREG(DSI_VC_CTRL(2));
1714 DUMPREG(DSI_VC_TE(2));
1715 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1716 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1717 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1718 DUMPREG(DSI_VC_IRQSTATUS(2));
1719 DUMPREG(DSI_VC_IRQENABLE(2));
1721 DUMPREG(DSI_VC_CTRL(3));
1722 DUMPREG(DSI_VC_TE(3));
1723 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1724 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1725 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1726 DUMPREG(DSI_VC_IRQSTATUS(3));
1727 DUMPREG(DSI_VC_IRQENABLE(3));
1729 DUMPREG(DSI_DSIPHY_CFG0);
1730 DUMPREG(DSI_DSIPHY_CFG1);
1731 DUMPREG(DSI_DSIPHY_CFG2);
1732 DUMPREG(DSI_DSIPHY_CFG5);
1734 DUMPREG(DSI_PLL_CONTROL);
1735 DUMPREG(DSI_PLL_STATUS);
1736 DUMPREG(DSI_PLL_GO);
1737 DUMPREG(DSI_PLL_CONFIGURATION1);
1738 DUMPREG(DSI_PLL_CONFIGURATION2);
1740 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
1744 enum dsi_complexio_power_state {
1745 DSI_COMPLEXIO_POWER_OFF = 0x0,
1746 DSI_COMPLEXIO_POWER_ON = 0x1,
1747 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1750 static int dsi_complexio_power(enum dsi_complexio_power_state state)
1755 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1758 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
1760 DSSERR("failed to set complexio power state to "
1770 static void dsi_complexio_config(struct omap_dss_device *dssdev)
1774 int clk_lane = dssdev->phy.dsi.clk_lane;
1775 int data1_lane = dssdev->phy.dsi.data1_lane;
1776 int data2_lane = dssdev->phy.dsi.data2_lane;
1777 int clk_pol = dssdev->phy.dsi.clk_pol;
1778 int data1_pol = dssdev->phy.dsi.data1_pol;
1779 int data2_pol = dssdev->phy.dsi.data2_pol;
1781 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1782 r = FLD_MOD(r, clk_lane, 2, 0);
1783 r = FLD_MOD(r, clk_pol, 3, 3);
1784 r = FLD_MOD(r, data1_lane, 6, 4);
1785 r = FLD_MOD(r, data1_pol, 7, 7);
1786 r = FLD_MOD(r, data2_lane, 10, 8);
1787 r = FLD_MOD(r, data2_pol, 11, 11);
1788 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1790 /* The configuration of the DSI complex I/O (number of data lanes,
1791 position, differential order) should not be changed while
1792 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1793 the hardware to take into account a new configuration of the complex
1794 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1795 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1796 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1797 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1798 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1799 DSI complex I/O configuration is unknown. */
1802 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1803 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1804 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1805 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1809 static inline unsigned ns2ddr(unsigned ns)
1811 /* convert time in ns to ddr ticks, rounding up */
1812 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1813 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1816 static inline unsigned ddr2ns(unsigned ddr)
1818 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1819 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1822 static void dsi_complexio_timings(void)
1825 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1826 u32 tlpx_half, tclk_trail, tclk_zero;
1829 /* calculate timings */
1831 /* 1 * DDR_CLK = 2 * UI */
1833 /* min 40ns + 4*UI max 85ns + 6*UI */
1834 ths_prepare = ns2ddr(70) + 2;
1836 /* min 145ns + 10*UI */
1837 ths_prepare_ths_zero = ns2ddr(175) + 2;
1839 /* min max(8*UI, 60ns+4*UI) */
1840 ths_trail = ns2ddr(60) + 5;
1843 ths_exit = ns2ddr(145);
1846 tlpx_half = ns2ddr(25);
1849 tclk_trail = ns2ddr(60) + 2;
1851 /* min 38ns, max 95ns */
1852 tclk_prepare = ns2ddr(65);
1854 /* min tclk-prepare + tclk-zero = 300ns */
1855 tclk_zero = ns2ddr(260);
1857 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1858 ths_prepare, ddr2ns(ths_prepare),
1859 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1860 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1861 ths_trail, ddr2ns(ths_trail),
1862 ths_exit, ddr2ns(ths_exit));
1864 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1865 "tclk_zero %u (%uns)\n",
1866 tlpx_half, ddr2ns(tlpx_half),
1867 tclk_trail, ddr2ns(tclk_trail),
1868 tclk_zero, ddr2ns(tclk_zero));
1869 DSSDBG("tclk_prepare %u (%uns)\n",
1870 tclk_prepare, ddr2ns(tclk_prepare));
1872 /* program timings */
1874 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1875 r = FLD_MOD(r, ths_prepare, 31, 24);
1876 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1877 r = FLD_MOD(r, ths_trail, 15, 8);
1878 r = FLD_MOD(r, ths_exit, 7, 0);
1879 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1881 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1882 r = FLD_MOD(r, tlpx_half, 22, 16);
1883 r = FLD_MOD(r, tclk_trail, 15, 8);
1884 r = FLD_MOD(r, tclk_zero, 7, 0);
1885 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1887 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1888 r = FLD_MOD(r, tclk_prepare, 7, 0);
1889 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1893 static int dsi_complexio_init(struct omap_dss_device *dssdev)
1897 DSSDBG("dsi_complexio_init\n");
1899 /* CIO_CLK_ICG, enable L3 clk to CIO */
1900 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1902 /* A dummy read using the SCP interface to any DSIPHY register is
1903 * required after DSIPHY reset to complete the reset of the DSI complex
1905 dsi_read_reg(DSI_DSIPHY_CFG5);
1907 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1908 DSSERR("ComplexIO PHY not coming out of reset.\n");
1913 dsi_complexio_config(dssdev);
1915 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1920 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1921 DSSERR("ComplexIO not coming out of reset.\n");
1926 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1927 DSSERR("ComplexIO LDO power down.\n");
1932 dsi_complexio_timings();
1935 The configuration of the DSI complex I/O (number of data lanes,
1936 position, differential order) should not be changed while
1937 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1938 hardware to recognize a new configuration of the complex I/O (done
1939 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1940 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1941 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1942 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1943 bit to 1. If the sequence is not followed, the DSi complex I/O
1944 configuration is undetermined.
1948 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1952 DSSDBG("CIO init done\n");
1957 static void dsi_complexio_uninit(void)
1959 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1962 static int _dsi_wait_reset(void)
1966 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
1968 DSSERR("soft reset failed\n");
1977 static int _dsi_reset(void)
1980 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1981 return _dsi_wait_reset();
1984 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1985 enum fifo_size size3, enum fifo_size size4)
1991 dsi.vc[0].fifo_size = size1;
1992 dsi.vc[1].fifo_size = size2;
1993 dsi.vc[2].fifo_size = size3;
1994 dsi.vc[3].fifo_size = size4;
1996 for (i = 0; i < 4; i++) {
1998 int size = dsi.vc[i].fifo_size;
2000 if (add + size > 4) {
2001 DSSERR("Illegal FIFO configuration\n");
2005 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2007 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2011 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
2014 static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
2015 enum fifo_size size3, enum fifo_size size4)
2021 dsi.vc[0].fifo_size = size1;
2022 dsi.vc[1].fifo_size = size2;
2023 dsi.vc[2].fifo_size = size3;
2024 dsi.vc[3].fifo_size = size4;
2026 for (i = 0; i < 4; i++) {
2028 int size = dsi.vc[i].fifo_size;
2030 if (add + size > 4) {
2031 DSSERR("Illegal FIFO configuration\n");
2035 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2037 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2041 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
2044 static int dsi_force_tx_stop_mode_io(void)
2048 r = dsi_read_reg(DSI_TIMING1);
2049 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2050 dsi_write_reg(DSI_TIMING1, r);
2052 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
2053 DSSERR("TX_STOP bit not going down\n");
2060 static int dsi_vc_enable(int channel, bool enable)
2062 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2065 enable = enable ? 1 : 0;
2067 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
2069 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
2070 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2077 static void dsi_vc_initial_config(int channel)
2081 DSSDBGF("%d", channel);
2083 r = dsi_read_reg(DSI_VC_CTRL(channel));
2085 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2086 DSSERR("VC(%d) busy when trying to configure it!\n",
2089 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2090 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2091 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2092 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2093 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2094 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2095 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2097 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2098 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2100 dsi_write_reg(DSI_VC_CTRL(channel), r);
2103 static int dsi_vc_config_l4(int channel)
2105 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
2108 DSSDBGF("%d", channel);
2110 dsi_vc_enable(channel, 0);
2113 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
2114 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
2118 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
2120 dsi_vc_enable(channel, 1);
2122 dsi.vc[channel].mode = DSI_VC_MODE_L4;
2127 static int dsi_vc_config_vp(int channel)
2129 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
2132 DSSDBGF("%d", channel);
2134 dsi_vc_enable(channel, 0);
2137 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
2138 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2142 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
2144 dsi_vc_enable(channel, 1);
2146 dsi.vc[channel].mode = DSI_VC_MODE_VP;
2152 void omapdss_dsi_vc_enable_hs(int channel, bool enable)
2154 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2156 WARN_ON(!dsi_bus_is_locked());
2158 dsi_vc_enable(channel, 0);
2161 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
2163 dsi_vc_enable(channel, 1);
2166 dsi_force_tx_stop_mode_io();
2168 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2170 static void dsi_vc_flush_long_data(int channel)
2172 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2174 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2175 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2179 (val >> 24) & 0xff);
2183 static void dsi_show_rx_ack_with_err(u16 err)
2185 DSSERR("\tACK with ERROR (%#x):\n", err);
2187 DSSERR("\t\tSoT Error\n");
2189 DSSERR("\t\tSoT Sync Error\n");
2191 DSSERR("\t\tEoT Sync Error\n");
2193 DSSERR("\t\tEscape Mode Entry Command Error\n");
2195 DSSERR("\t\tLP Transmit Sync Error\n");
2197 DSSERR("\t\tHS Receive Timeout Error\n");
2199 DSSERR("\t\tFalse Control Error\n");
2201 DSSERR("\t\t(reserved7)\n");
2203 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2205 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2206 if (err & (1 << 10))
2207 DSSERR("\t\tChecksum Error\n");
2208 if (err & (1 << 11))
2209 DSSERR("\t\tData type not recognized\n");
2210 if (err & (1 << 12))
2211 DSSERR("\t\tInvalid VC ID\n");
2212 if (err & (1 << 13))
2213 DSSERR("\t\tInvalid Transmission Length\n");
2214 if (err & (1 << 14))
2215 DSSERR("\t\t(reserved14)\n");
2216 if (err & (1 << 15))
2217 DSSERR("\t\tDSI Protocol Violation\n");
2220 static u16 dsi_vc_flush_receive_data(int channel)
2222 /* RX_FIFO_NOT_EMPTY */
2223 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2226 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2227 DSSERR("\trawval %#08x\n", val);
2228 dt = FLD_GET(val, 5, 0);
2229 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2230 u16 err = FLD_GET(val, 23, 8);
2231 dsi_show_rx_ack_with_err(err);
2232 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2233 DSSERR("\tDCS short response, 1 byte: %#x\n",
2234 FLD_GET(val, 23, 8));
2235 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2236 DSSERR("\tDCS short response, 2 byte: %#x\n",
2237 FLD_GET(val, 23, 8));
2238 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2239 DSSERR("\tDCS long response, len %d\n",
2240 FLD_GET(val, 23, 8));
2241 dsi_vc_flush_long_data(channel);
2243 DSSERR("\tunknown datatype 0x%02x\n", dt);
2249 static int dsi_vc_send_bta(int channel)
2251 if (dsi.debug_write || dsi.debug_read)
2252 DSSDBG("dsi_vc_send_bta %d\n", channel);
2254 WARN_ON(!dsi_bus_is_locked());
2256 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2257 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2258 dsi_vc_flush_receive_data(channel);
2261 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2266 int dsi_vc_send_bta_sync(int channel)
2268 DECLARE_COMPLETION_ONSTACK(completion);
2272 r = dsi_register_isr_vc(channel, dsi_completion_handler,
2273 &completion, DSI_VC_IRQ_BTA);
2277 r = dsi_vc_send_bta(channel);
2281 if (wait_for_completion_timeout(&completion,
2282 msecs_to_jiffies(500)) == 0) {
2283 DSSERR("Failed to receive BTA\n");
2288 err = dsi_get_errors();
2290 DSSERR("Error while sending BTA: %x\n", err);
2296 dsi_unregister_isr_vc(channel, dsi_completion_handler,
2297 &completion, DSI_VC_IRQ_BTA);
2301 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2303 static inline void dsi_vc_write_long_header(int channel, u8 data_type,
2309 WARN_ON(!dsi_bus_is_locked());
2311 data_id = data_type | dsi.vc[channel].vc_id << 6;
2313 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2314 FLD_VAL(ecc, 31, 24);
2316 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
2319 static inline void dsi_vc_write_long_payload(int channel,
2320 u8 b1, u8 b2, u8 b3, u8 b4)
2324 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2326 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2327 b1, b2, b3, b4, val); */
2329 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2332 static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
2341 if (dsi.debug_write)
2342 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2345 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
2346 DSSERR("unable to send long packet: packet too long.\n");
2350 dsi_vc_config_l4(channel);
2352 dsi_vc_write_long_header(channel, data_type, len, ecc);
2355 for (i = 0; i < len >> 2; i++) {
2356 if (dsi.debug_write)
2357 DSSDBG("\tsending full packet %d\n", i);
2364 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2369 b1 = 0; b2 = 0; b3 = 0;
2371 if (dsi.debug_write)
2372 DSSDBG("\tsending remainder bytes %d\n", i);
2389 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2395 static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2400 WARN_ON(!dsi_bus_is_locked());
2402 if (dsi.debug_write)
2403 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2405 data_type, data & 0xff, (data >> 8) & 0xff);
2407 dsi_vc_config_l4(channel);
2409 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2410 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2414 data_id = data_type | dsi.vc[channel].vc_id << 6;
2416 r = (data_id << 0) | (data << 8) | (ecc << 24);
2418 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2423 int dsi_vc_send_null(int channel)
2425 u8 nullpkg[] = {0, 0, 0, 0};
2426 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
2428 EXPORT_SYMBOL(dsi_vc_send_null);
2430 int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2437 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2439 } else if (len == 2) {
2440 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2441 data[0] | (data[1] << 8), 0);
2443 /* 0x39 = DCS Long Write */
2444 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2450 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2452 int dsi_vc_dcs_write(int channel, u8 *data, int len)
2456 r = dsi_vc_dcs_write_nosync(channel, data, len);
2460 r = dsi_vc_send_bta_sync(channel);
2464 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2465 DSSERR("rx fifo not empty after write, dumping data:\n");
2466 dsi_vc_flush_receive_data(channel);
2473 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2474 channel, data[0], len);
2477 EXPORT_SYMBOL(dsi_vc_dcs_write);
2479 int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2481 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2483 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2485 int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2490 return dsi_vc_dcs_write(channel, buf, 2);
2492 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2494 int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2501 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
2503 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2507 r = dsi_vc_send_bta_sync(channel);
2511 /* RX_FIFO_NOT_EMPTY */
2512 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2513 DSSERR("RX fifo empty when trying to read.\n");
2518 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2520 DSSDBG("\theader: %08x\n", val);
2521 dt = FLD_GET(val, 5, 0);
2522 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2523 u16 err = FLD_GET(val, 23, 8);
2524 dsi_show_rx_ack_with_err(err);
2528 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2529 u8 data = FLD_GET(val, 15, 8);
2531 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2541 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2542 u16 data = FLD_GET(val, 23, 8);
2544 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2551 buf[0] = data & 0xff;
2552 buf[1] = (data >> 8) & 0xff;
2555 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2557 int len = FLD_GET(val, 23, 8);
2559 DSSDBG("\tDCS long response, len %d\n", len);
2566 /* two byte checksum ends the packet, not included in len */
2567 for (w = 0; w < len + 2;) {
2569 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2571 DSSDBG("\t\t%02x %02x %02x %02x\n",
2575 (val >> 24) & 0xff);
2577 for (b = 0; b < 4; ++b) {
2579 buf[w] = (val >> (b * 8)) & 0xff;
2580 /* we discard the 2 byte checksum */
2587 DSSERR("\tunknown datatype 0x%02x\n", dt);
2594 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2599 EXPORT_SYMBOL(dsi_vc_dcs_read);
2601 int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2605 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2615 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
2617 int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
2622 r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
2635 EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2637 int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2639 return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2642 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2644 static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
2647 unsigned long total_ticks;
2650 BUG_ON(ticks > 0x1fff);
2652 /* ticks in DSI_FCK */
2653 fck = dsi_fclk_rate();
2655 r = dsi_read_reg(DSI_TIMING2);
2656 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2657 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2658 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
2659 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2660 dsi_write_reg(DSI_TIMING2, r);
2662 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2664 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2666 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2667 (total_ticks * 1000) / (fck / 1000 / 1000));
2670 static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
2673 unsigned long total_ticks;
2676 BUG_ON(ticks > 0x1fff);
2678 /* ticks in DSI_FCK */
2679 fck = dsi_fclk_rate();
2681 r = dsi_read_reg(DSI_TIMING1);
2682 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2683 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
2684 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
2685 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2686 dsi_write_reg(DSI_TIMING1, r);
2688 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
2690 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2692 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
2693 (total_ticks * 1000) / (fck / 1000 / 1000));
2696 static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
2699 unsigned long total_ticks;
2702 BUG_ON(ticks > 0x1fff);
2704 /* ticks in DSI_FCK */
2705 fck = dsi_fclk_rate();
2707 r = dsi_read_reg(DSI_TIMING1);
2708 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2709 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2710 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
2711 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2712 dsi_write_reg(DSI_TIMING1, r);
2714 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2716 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2718 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2719 (total_ticks * 1000) / (fck / 1000 / 1000));
2722 static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
2725 unsigned long total_ticks;
2728 BUG_ON(ticks > 0x1fff);
2730 /* ticks in TxByteClkHS */
2731 fck = dsi_get_txbyteclkhs();
2733 r = dsi_read_reg(DSI_TIMING2);
2734 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2735 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2736 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
2737 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2738 dsi_write_reg(DSI_TIMING2, r);
2740 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2742 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2744 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2745 (total_ticks * 1000) / (fck / 1000 / 1000));
2747 static int dsi_proto_config(struct omap_dss_device *dssdev)
2752 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2757 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2762 /* XXX what values for the timeouts? */
2763 dsi_set_stop_state_counter(0x1000, false, false);
2764 dsi_set_ta_timeout(0x1fff, true, true);
2765 dsi_set_lp_rx_timeout(0x1fff, true, true);
2766 dsi_set_hs_tx_timeout(0x1fff, true, true);
2768 switch (dssdev->ctrl.pixel_size) {
2782 r = dsi_read_reg(DSI_CTRL);
2783 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2784 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2785 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2786 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2787 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2788 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2789 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2790 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2791 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2792 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2793 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2795 dsi_write_reg(DSI_CTRL, r);
2797 dsi_vc_initial_config(0);
2798 dsi_vc_initial_config(1);
2799 dsi_vc_initial_config(2);
2800 dsi_vc_initial_config(3);
2805 static void dsi_proto_timings(struct omap_dss_device *dssdev)
2807 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2808 unsigned tclk_pre, tclk_post;
2809 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2810 unsigned ths_trail, ths_exit;
2811 unsigned ddr_clk_pre, ddr_clk_post;
2812 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2816 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2817 ths_prepare = FLD_GET(r, 31, 24);
2818 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2819 ths_zero = ths_prepare_ths_zero - ths_prepare;
2820 ths_trail = FLD_GET(r, 15, 8);
2821 ths_exit = FLD_GET(r, 7, 0);
2823 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2824 tlpx = FLD_GET(r, 22, 16) * 2;
2825 tclk_trail = FLD_GET(r, 15, 8);
2826 tclk_zero = FLD_GET(r, 7, 0);
2828 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2829 tclk_prepare = FLD_GET(r, 7, 0);
2833 /* min 60ns + 52*UI */
2834 tclk_post = ns2ddr(60) + 26;
2836 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2837 if (dssdev->phy.dsi.data1_lane != 0 &&
2838 dssdev->phy.dsi.data2_lane != 0)
2843 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2845 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2847 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2848 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2850 r = dsi_read_reg(DSI_CLK_TIMING);
2851 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2852 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2853 dsi_write_reg(DSI_CLK_TIMING, r);
2855 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2859 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2860 DIV_ROUND_UP(ths_prepare, 4) +
2861 DIV_ROUND_UP(ths_zero + 3, 4);
2863 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2865 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2866 FLD_VAL(exit_hs_mode_lat, 15, 0);
2867 dsi_write_reg(DSI_VM_TIMING7, r);
2869 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2870 enter_hs_mode_lat, exit_hs_mode_lat);
2874 #define DSI_DECL_VARS \
2875 int __dsi_cb = 0; u32 __dsi_cv = 0;
2877 #define DSI_FLUSH(ch) \
2878 if (__dsi_cb > 0) { \
2879 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2880 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2881 __dsi_cb = __dsi_cv = 0; \
2884 #define DSI_PUSH(ch, data) \
2886 __dsi_cv |= (data) << (__dsi_cb * 8); \
2887 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2888 if (++__dsi_cb > 3) \
2892 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2893 int x, int y, int w, int h)
2895 /* Note: supports only 24bit colors in 32bit container */
2897 int fifo_stalls = 0;
2898 int max_dsi_packet_size;
2899 int max_data_per_packet;
2900 int max_pixels_per_packet;
2902 int bytespp = dssdev->ctrl.pixel_size / 8;
2908 struct omap_overlay *ovl;
2912 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2915 ovl = dssdev->manager->overlays[0];
2917 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2920 if (dssdev->ctrl.pixel_size != 24)
2923 scr_width = ovl->info.screen_width;
2924 data = ovl->info.vaddr;
2926 start_offset = scr_width * y + x;
2927 horiz_inc = scr_width - w;
2930 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2933 /* When using CPU, max long packet size is TX buffer size */
2934 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2936 /* we seem to get better perf if we divide the tx fifo to half,
2937 and while the other half is being sent, we fill the other half
2938 max_dsi_packet_size /= 2; */
2940 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2942 max_pixels_per_packet = max_data_per_packet / bytespp;
2944 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2946 pixels_left = w * h;
2948 DSSDBG("total pixels %d\n", pixels_left);
2950 data += start_offset;
2952 while (pixels_left > 0) {
2953 /* 0x2c = write_memory_start */
2954 /* 0x3c = write_memory_continue */
2955 u8 dcs_cmd = first ? 0x2c : 0x3c;
2961 /* using fifo not empty */
2962 /* TX_FIFO_NOT_EMPTY */
2963 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
2965 if (fifo_stalls > 0xfffff) {
2966 DSSERR("fifo stalls overflow, pixels left %d\n",
2974 /* using fifo emptiness */
2975 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2976 max_dsi_packet_size) {
2978 if (fifo_stalls > 0xfffff) {
2979 DSSERR("fifo stalls overflow, pixels left %d\n",
2986 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2988 if (fifo_stalls > 0xfffff) {
2989 DSSERR("fifo stalls overflow, pixels left %d\n",
2996 pixels = min(max_pixels_per_packet, pixels_left);
2998 pixels_left -= pixels;
3000 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
3001 1 + pixels * bytespp, 0);
3003 DSI_PUSH(0, dcs_cmd);
3005 while (pixels-- > 0) {
3006 u32 pix = __raw_readl(data++);
3008 DSI_PUSH(0, (pix >> 16) & 0xff);
3009 DSI_PUSH(0, (pix >> 8) & 0xff);
3010 DSI_PUSH(0, (pix >> 0) & 0xff);
3013 if (current_x == x+w) {
3025 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
3026 u16 x, u16 y, u16 w, u16 h)
3032 unsigned packet_payload;
3033 unsigned packet_len;
3036 const unsigned channel = dsi.update_channel;
3037 /* line buffer is 1024 x 24bits */
3038 /* XXX: for some reason using full buffer size causes considerable TX
3039 * slowdown with update sizes that fill the whole buffer */
3040 const unsigned line_buf_size = 1023 * 3;
3042 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
3045 dsi_vc_config_vp(channel);
3047 bytespp = dssdev->ctrl.pixel_size / 8;
3048 bytespl = w * bytespp;
3049 bytespf = bytespl * h;
3051 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3052 * number of lines in a packet. See errata about VP_CLK_RATIO */
3054 if (bytespf < line_buf_size)
3055 packet_payload = bytespf;
3057 packet_payload = (line_buf_size) / bytespl * bytespl;
3059 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3060 total_len = (bytespf / packet_payload) * packet_len;
3062 if (bytespf % packet_payload)
3063 total_len += (bytespf % packet_payload) + 1;
3065 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3066 dsi_write_reg(DSI_VC_TE(channel), l);
3068 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
3071 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3073 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3074 dsi_write_reg(DSI_VC_TE(channel), l);
3076 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3077 * because DSS interrupts are not capable of waking up the CPU and the
3078 * framedone interrupt could be delayed for quite a long time. I think
3079 * the same goes for any DSS interrupts, but for some reason I have not
3080 * seen the problem anywhere else than here.
3082 dispc_disable_sidle();
3084 dsi_perf_mark_start();
3086 r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
3087 msecs_to_jiffies(250));
3090 dss_start_update(dssdev);
3092 if (dsi.te_enabled) {
3093 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3094 * for TE is longer than the timer allows */
3095 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3097 dsi_vc_send_bta(channel);
3099 #ifdef DSI_CATCH_MISSING_TE
3100 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
3105 #ifdef DSI_CATCH_MISSING_TE
3106 static void dsi_te_timeout(unsigned long arg)
3108 DSSERR("TE not received for 250ms!\n");
3112 static void dsi_handle_framedone(int error)
3114 const int channel = dsi.update_channel;
3116 cancel_delayed_work(&dsi.framedone_timeout_work);
3118 dsi_vc_disable_bta_irq(channel);
3120 /* SIDLEMODE back to smart-idle */
3121 dispc_enable_sidle();
3123 dsi.bta_callback = NULL;
3125 if (dsi.te_enabled) {
3126 /* enable LP_RX_TO again after the TE */
3127 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3130 /* RX_FIFO_NOT_EMPTY */
3131 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
3132 DSSERR("Received error during frame transfer:\n");
3133 dsi_vc_flush_receive_data(channel);
3138 dsi.framedone_callback(error, dsi.framedone_data);
3141 dsi_perf_show("DISPC");
3144 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3146 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3147 * 250ms which would conflict with this timeout work. What should be
3148 * done is first cancel the transfer on the HW, and then cancel the
3149 * possibly scheduled framedone work. However, cancelling the transfer
3150 * on the HW is buggy, and would probably require resetting the whole
3153 DSSERR("Framedone not received for 250ms!\n");
3155 dsi_handle_framedone(-ETIMEDOUT);
3158 static void dsi_framedone_bta_callback(void)
3160 dsi_handle_framedone(0);
3162 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3163 dispc_fake_vsync_irq();
3167 static void dsi_framedone_irq_callback(void *data, u32 mask)
3169 const int channel = dsi.update_channel;
3172 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3173 * turns itself off. However, DSI still has the pixels in its buffers,
3174 * and is sending the data.
3177 if (dsi.te_enabled) {
3178 /* enable LP_RX_TO again after the TE */
3179 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3182 /* Send BTA after the frame. We need this for the TE to work, as TE
3183 * trigger is only sent for BTAs without preceding packet. Thus we need
3184 * to BTA after the pixel packets so that next BTA will cause TE
3187 * This is not needed when TE is not in use, but we do it anyway to
3188 * make sure that the transfer has been completed. It would be more
3189 * optimal, but more complex, to wait only just before starting next
3192 * Also, as there's no interrupt telling when the transfer has been
3193 * done and the channel could be reconfigured, the only way is to
3194 * busyloop until TE_SIZE is zero. With BTA we can do this
3198 dsi.bta_callback = dsi_framedone_bta_callback;
3202 dsi_vc_enable_bta_irq(channel);
3204 r = dsi_vc_send_bta(channel);
3206 DSSERR("BTA after framedone failed\n");
3207 dsi_handle_framedone(-EIO);
3211 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
3212 u16 *x, u16 *y, u16 *w, u16 *h,
3213 bool enlarge_update_area)
3217 dssdev->driver->get_resolution(dssdev, &dw, &dh);
3219 if (*x > dw || *y > dh)
3231 if (*w == 0 || *h == 0)
3234 dsi_perf_mark_setup();
3236 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3237 dss_setup_partial_planes(dssdev, x, y, w, h,
3238 enlarge_update_area);
3239 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
3244 EXPORT_SYMBOL(omap_dsi_prepare_update);
3246 int omap_dsi_update(struct omap_dss_device *dssdev,
3248 u16 x, u16 y, u16 w, u16 h,
3249 void (*callback)(int, void *), void *data)
3251 dsi.update_channel = channel;
3253 /* OMAP DSS cannot send updates of odd widths.
3254 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
3255 * here to make sure we catch erroneous updates. Otherwise we'll only
3256 * see rather obscure HW error happening, as DSS halts. */
3259 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3260 dsi.framedone_callback = callback;
3261 dsi.framedone_data = data;
3263 dsi.update_region.x = x;
3264 dsi.update_region.y = y;
3265 dsi.update_region.w = w;
3266 dsi.update_region.h = h;
3267 dsi.update_region.device = dssdev;
3269 dsi_update_screen_dispc(dssdev, x, y, w, h);
3273 r = dsi_update_screen_l4(dssdev, x, y, w, h);
3277 dsi_perf_show("L4");
3283 EXPORT_SYMBOL(omap_dsi_update);
3287 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
3291 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
3292 DISPC_IRQ_FRAMEDONE);
3294 DSSERR("can't get FRAMEDONE irq\n");
3298 dispc_set_lcd_display_type(dssdev->manager->id,
3299 OMAP_DSS_LCD_DISPLAY_TFT);
3301 dispc_set_parallel_interface_mode(dssdev->manager->id,
3302 OMAP_DSS_PARALLELMODE_DSI);
3303 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
3305 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
3308 struct omap_video_timings timings = {
3317 dispc_set_lcd_timings(dssdev->manager->id, &timings);
3323 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
3325 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
3326 DISPC_IRQ_FRAMEDONE);
3329 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
3331 struct dsi_clock_info cinfo;
3334 /* we always use DSS_CLK_SYSCK as input clock */
3335 cinfo.use_sys_clk = true;
3336 cinfo.regn = dssdev->phy.dsi.div.regn;
3337 cinfo.regm = dssdev->phy.dsi.div.regm;
3338 cinfo.regm_dispc = dssdev->phy.dsi.div.regm_dispc;
3339 cinfo.regm_dsi = dssdev->phy.dsi.div.regm_dsi;
3340 r = dsi_calc_clock_rates(dssdev, &cinfo);
3342 DSSERR("Failed to calc dsi clocks\n");
3346 r = dsi_pll_set_clock_div(&cinfo);
3348 DSSERR("Failed to set dsi clocks\n");
3355 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3357 struct dispc_clock_info dispc_cinfo;
3359 unsigned long long fck;
3361 fck = dsi_get_pll_hsdiv_dispc_rate();
3363 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3364 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3366 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3368 DSSERR("Failed to calc dispc clocks\n");
3372 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
3374 DSSERR("Failed to set dispc clocks\n");
3381 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3385 _dsi_print_reset_status();
3387 r = dsi_pll_init(dssdev, true, true);
3391 r = dsi_configure_dsi_clocks(dssdev);
3395 dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
3396 dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);
3400 r = dsi_configure_dispc_clocks(dssdev);
3404 r = dsi_complexio_init(dssdev);
3408 _dsi_print_reset_status();
3410 dsi_proto_timings(dssdev);
3411 dsi_set_lp_clk_divisor(dssdev);
3414 _dsi_print_reset_status();
3416 r = dsi_proto_config(dssdev);
3420 /* enable interface */
3421 dsi_vc_enable(0, 1);
3422 dsi_vc_enable(1, 1);
3423 dsi_vc_enable(2, 1);
3424 dsi_vc_enable(3, 1);
3426 dsi_force_tx_stop_mode_io();
3430 dsi_complexio_uninit();
3432 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
3433 dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
3440 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3442 /* disable interface */
3444 dsi_vc_enable(0, 0);
3445 dsi_vc_enable(1, 0);
3446 dsi_vc_enable(2, 0);
3447 dsi_vc_enable(3, 0);
3449 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
3450 dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
3451 dsi_complexio_uninit();
3455 static int dsi_core_init(void)
3458 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3461 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3463 /* SIDLEMODE smart-idle */
3464 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3466 _dsi_initialize_irq();
3471 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
3475 DSSDBG("dsi_display_enable\n");
3477 WARN_ON(!dsi_bus_is_locked());
3479 mutex_lock(&dsi.lock);
3481 r = omap_dss_start_device(dssdev);
3483 DSSERR("failed to start device\n");
3488 dsi_enable_pll_clock(1);
3496 r = dsi_display_init_dispc(dssdev);
3500 r = dsi_display_init_dsi(dssdev);
3504 mutex_unlock(&dsi.lock);
3509 dsi_display_uninit_dispc(dssdev);
3512 dsi_enable_pll_clock(0);
3513 omap_dss_stop_device(dssdev);
3515 mutex_unlock(&dsi.lock);
3516 DSSDBG("dsi_display_enable FAILED\n");
3519 EXPORT_SYMBOL(omapdss_dsi_display_enable);
3521 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
3523 DSSDBG("dsi_display_disable\n");
3525 WARN_ON(!dsi_bus_is_locked());
3527 mutex_lock(&dsi.lock);
3529 dsi_display_uninit_dispc(dssdev);
3531 dsi_display_uninit_dsi(dssdev);
3534 dsi_enable_pll_clock(0);
3536 omap_dss_stop_device(dssdev);
3538 mutex_unlock(&dsi.lock);
3540 EXPORT_SYMBOL(omapdss_dsi_display_disable);
3542 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
3544 dsi.te_enabled = enable;
3547 EXPORT_SYMBOL(omapdss_dsi_enable_te);
3549 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3550 u32 fifo_size, enum omap_burst_size *burst_size,
3551 u32 *fifo_low, u32 *fifo_high)
3553 unsigned burst_size_bytes;
3555 *burst_size = OMAP_DSS_BURST_16x32;
3556 burst_size_bytes = 16 * 32 / 8;
3558 *fifo_high = fifo_size - burst_size_bytes;
3559 *fifo_low = fifo_size - burst_size_bytes * 2;
3562 int dsi_init_display(struct omap_dss_device *dssdev)
3564 DSSDBG("DSI init\n");
3566 /* XXX these should be figured out dynamically */
3567 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3568 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3570 if (dsi.vdds_dsi_reg == NULL) {
3571 struct regulator *vdds_dsi;
3573 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
3575 if (IS_ERR(vdds_dsi)) {
3576 DSSERR("can't get VDDS_DSI regulator\n");
3577 return PTR_ERR(vdds_dsi);
3580 dsi.vdds_dsi_reg = vdds_dsi;
3586 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
3590 for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
3591 if (!dsi.vc[i].dssdev) {
3592 dsi.vc[i].dssdev = dssdev;
3598 DSSERR("cannot get VC for display %s", dssdev->name);
3601 EXPORT_SYMBOL(omap_dsi_request_vc);
3603 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
3605 if (vc_id < 0 || vc_id > 3) {
3606 DSSERR("VC ID out of range\n");
3610 if (channel < 0 || channel > 3) {
3611 DSSERR("Virtual Channel out of range\n");
3615 if (dsi.vc[channel].dssdev != dssdev) {
3616 DSSERR("Virtual Channel not allocated to display %s\n",
3621 dsi.vc[channel].vc_id = vc_id;
3625 EXPORT_SYMBOL(omap_dsi_set_vc_id);
3627 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
3629 if ((channel >= 0 && channel <= 3) &&
3630 dsi.vc[channel].dssdev == dssdev) {
3631 dsi.vc[channel].dssdev = NULL;
3632 dsi.vc[channel].vc_id = 0;
3635 EXPORT_SYMBOL(omap_dsi_release_vc);
3637 void dsi_wait_pll_hsdiv_dispc_active(void)
3639 if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
3640 DSSERR("%s (%s) not active\n",
3641 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
3642 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
3645 void dsi_wait_pll_hsdiv_dsi_active(void)
3647 if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
3648 DSSERR("%s (%s) not active\n",
3649 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
3650 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
3653 static void dsi_calc_clock_param_ranges(void)
3655 dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
3656 dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
3657 dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
3658 dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
3659 dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
3660 dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
3661 dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
3664 static int dsi_init(struct platform_device *pdev)
3668 struct resource *dsi_mem;
3670 spin_lock_init(&dsi.irq_lock);
3671 spin_lock_init(&dsi.errors_lock);
3674 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3675 spin_lock_init(&dsi.irq_stats_lock);
3676 dsi.irq_stats.last_reset = jiffies;
3679 mutex_init(&dsi.lock);
3680 sema_init(&dsi.bus_lock, 1);
3682 dsi.workqueue = create_singlethread_workqueue("dsi");
3683 if (dsi.workqueue == NULL)
3686 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3687 dsi_framedone_timeout_work_callback);
3689 #ifdef DSI_CATCH_MISSING_TE
3690 init_timer(&dsi.te_timer);
3691 dsi.te_timer.function = dsi_te_timeout;
3692 dsi.te_timer.data = 0;
3694 dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0);
3696 DSSERR("can't get IORESOURCE_MEM DSI\n");
3700 dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem));
3702 DSSERR("can't ioremap DSI\n");
3706 dsi.irq = platform_get_irq(dsi.pdev, 0);
3708 DSSERR("platform_get_irq failed\n");
3713 r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED,
3714 "OMAP DSI1", dsi.pdev);
3716 DSSERR("request_irq failed\n");
3720 /* DSI VCs initialization */
3721 for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
3722 dsi.vc[i].mode = DSI_VC_MODE_L4;
3723 dsi.vc[i].dssdev = NULL;
3724 dsi.vc[i].vc_id = 0;
3727 dsi_calc_clock_param_ranges();
3731 rev = dsi_read_reg(DSI_REVISION);
3732 dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n",
3733 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3741 destroy_workqueue(dsi.workqueue);
3745 static void dsi_exit(void)
3747 if (dsi.vdds_dsi_reg != NULL) {
3748 regulator_put(dsi.vdds_dsi_reg);
3749 dsi.vdds_dsi_reg = NULL;
3752 free_irq(dsi.irq, dsi.pdev);
3755 destroy_workqueue(dsi.workqueue);
3757 DSSDBG("omap_dsi_exit\n");
3760 /* DSI1 HW IP initialisation */
3761 static int omap_dsi1hw_probe(struct platform_device *pdev)
3767 DSSERR("Failed to initialize DSI\n");
3774 static int omap_dsi1hw_remove(struct platform_device *pdev)
3780 static struct platform_driver omap_dsi1hw_driver = {
3781 .probe = omap_dsi1hw_probe,
3782 .remove = omap_dsi1hw_remove,
3784 .name = "omapdss_dsi1",
3785 .owner = THIS_MODULE,
3789 int dsi_init_platform_driver(void)
3791 return platform_driver_register(&omap_dsi1hw_driver);
3794 void dsi_uninit_platform_driver(void)
3796 return platform_driver_unregister(&omap_dsi1hw_driver);