2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/clk.h>
30 #include <linux/jiffies.h>
31 #include <linux/seq_file.h>
32 #include <linux/delay.h>
33 #include <linux/workqueue.h>
35 #include <mach/sram.h>
36 #include <mach/board.h>
37 #include <mach/clock.h>
39 #include <mach/display.h>
44 #define DISPC_BASE 0x48050400
46 #define DISPC_SZ_REGS SZ_1K
48 struct dispc_reg { u16 idx; };
50 #define DISPC_REG(idx) ((const struct dispc_reg) { idx })
53 #define DISPC_REVISION DISPC_REG(0x0000)
54 #define DISPC_SYSCONFIG DISPC_REG(0x0010)
55 #define DISPC_SYSSTATUS DISPC_REG(0x0014)
56 #define DISPC_IRQSTATUS DISPC_REG(0x0018)
57 #define DISPC_IRQENABLE DISPC_REG(0x001C)
58 #define DISPC_CONTROL DISPC_REG(0x0040)
59 #define DISPC_CONFIG DISPC_REG(0x0044)
60 #define DISPC_CAPABLE DISPC_REG(0x0048)
61 #define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
62 #define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
63 #define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
64 #define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
65 #define DISPC_LINE_STATUS DISPC_REG(0x005C)
66 #define DISPC_LINE_NUMBER DISPC_REG(0x0060)
67 #define DISPC_TIMING_H DISPC_REG(0x0064)
68 #define DISPC_TIMING_V DISPC_REG(0x0068)
69 #define DISPC_POL_FREQ DISPC_REG(0x006C)
70 #define DISPC_DIVISOR DISPC_REG(0x0070)
71 #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
72 #define DISPC_SIZE_DIG DISPC_REG(0x0078)
73 #define DISPC_SIZE_LCD DISPC_REG(0x007C)
76 #define DISPC_GFX_BA0 DISPC_REG(0x0080)
77 #define DISPC_GFX_BA1 DISPC_REG(0x0084)
78 #define DISPC_GFX_POSITION DISPC_REG(0x0088)
79 #define DISPC_GFX_SIZE DISPC_REG(0x008C)
80 #define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
81 #define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
82 #define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
83 #define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
84 #define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
85 #define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
86 #define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
88 #define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
89 #define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
90 #define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
92 #define DISPC_CPR_COEF_R DISPC_REG(0x0220)
93 #define DISPC_CPR_COEF_G DISPC_REG(0x0224)
94 #define DISPC_CPR_COEF_B DISPC_REG(0x0228)
96 #define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
99 #define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
101 #define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
102 #define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
103 #define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
104 #define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
105 #define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
106 #define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
107 #define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
108 #define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
109 #define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
110 #define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
111 #define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
112 #define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
113 #define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
116 #define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
118 #define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
119 /* coef index i = {0, 1, 2, 3, 4} */
120 #define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
122 #define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
124 #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
127 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
128 DISPC_IRQ_OCP_ERR | \
129 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
130 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
131 DISPC_IRQ_SYNC_LOST | \
132 DISPC_IRQ_SYNC_LOST_DIGIT)
134 #define DISPC_MAX_NR_ISRS 8
136 struct omap_dispc_isr_data {
137 omap_dispc_isr_t isr;
142 #define REG_GET(idx, start, end) \
143 FLD_GET(dispc_read_reg(idx), start, end)
145 #define REG_FLD_MOD(idx, val, start, end) \
146 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
149 DISPC_VID_ATTRIBUTES(0),
150 DISPC_VID_ATTRIBUTES(1) };
155 struct clk *dpll4_m4_ck;
159 unsigned long cache_req_pck;
160 unsigned long cache_prate;
161 struct dispc_clock_info cache_cinfo;
164 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
166 spinlock_t error_lock;
168 struct work_struct error_work;
170 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
173 static void omap_dispc_set_irqs(void);
175 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
177 __raw_writel(val, dispc.base + idx.idx);
180 static inline u32 dispc_read_reg(const struct dispc_reg idx)
182 return __raw_readl(dispc.base + idx.idx);
186 dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
188 dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
190 void dispc_save_context(void)
192 if (cpu_is_omap24xx())
217 SR(GFX_FIFO_THRESHOLD);
238 SR(VID_ATTRIBUTES(0));
239 SR(VID_FIFO_THRESHOLD(0));
241 SR(VID_PIXEL_INC(0));
243 SR(VID_PICTURE_SIZE(0));
247 SR(VID_FIR_COEF_H(0, 0));
248 SR(VID_FIR_COEF_H(0, 1));
249 SR(VID_FIR_COEF_H(0, 2));
250 SR(VID_FIR_COEF_H(0, 3));
251 SR(VID_FIR_COEF_H(0, 4));
252 SR(VID_FIR_COEF_H(0, 5));
253 SR(VID_FIR_COEF_H(0, 6));
254 SR(VID_FIR_COEF_H(0, 7));
256 SR(VID_FIR_COEF_HV(0, 0));
257 SR(VID_FIR_COEF_HV(0, 1));
258 SR(VID_FIR_COEF_HV(0, 2));
259 SR(VID_FIR_COEF_HV(0, 3));
260 SR(VID_FIR_COEF_HV(0, 4));
261 SR(VID_FIR_COEF_HV(0, 5));
262 SR(VID_FIR_COEF_HV(0, 6));
263 SR(VID_FIR_COEF_HV(0, 7));
265 SR(VID_CONV_COEF(0, 0));
266 SR(VID_CONV_COEF(0, 1));
267 SR(VID_CONV_COEF(0, 2));
268 SR(VID_CONV_COEF(0, 3));
269 SR(VID_CONV_COEF(0, 4));
271 SR(VID_FIR_COEF_V(0, 0));
272 SR(VID_FIR_COEF_V(0, 1));
273 SR(VID_FIR_COEF_V(0, 2));
274 SR(VID_FIR_COEF_V(0, 3));
275 SR(VID_FIR_COEF_V(0, 4));
276 SR(VID_FIR_COEF_V(0, 5));
277 SR(VID_FIR_COEF_V(0, 6));
278 SR(VID_FIR_COEF_V(0, 7));
287 SR(VID_ATTRIBUTES(1));
288 SR(VID_FIFO_THRESHOLD(1));
290 SR(VID_PIXEL_INC(1));
292 SR(VID_PICTURE_SIZE(1));
296 SR(VID_FIR_COEF_H(1, 0));
297 SR(VID_FIR_COEF_H(1, 1));
298 SR(VID_FIR_COEF_H(1, 2));
299 SR(VID_FIR_COEF_H(1, 3));
300 SR(VID_FIR_COEF_H(1, 4));
301 SR(VID_FIR_COEF_H(1, 5));
302 SR(VID_FIR_COEF_H(1, 6));
303 SR(VID_FIR_COEF_H(1, 7));
305 SR(VID_FIR_COEF_HV(1, 0));
306 SR(VID_FIR_COEF_HV(1, 1));
307 SR(VID_FIR_COEF_HV(1, 2));
308 SR(VID_FIR_COEF_HV(1, 3));
309 SR(VID_FIR_COEF_HV(1, 4));
310 SR(VID_FIR_COEF_HV(1, 5));
311 SR(VID_FIR_COEF_HV(1, 6));
312 SR(VID_FIR_COEF_HV(1, 7));
314 SR(VID_CONV_COEF(1, 0));
315 SR(VID_CONV_COEF(1, 1));
316 SR(VID_CONV_COEF(1, 2));
317 SR(VID_CONV_COEF(1, 3));
318 SR(VID_CONV_COEF(1, 4));
320 SR(VID_FIR_COEF_V(1, 0));
321 SR(VID_FIR_COEF_V(1, 1));
322 SR(VID_FIR_COEF_V(1, 2));
323 SR(VID_FIR_COEF_V(1, 3));
324 SR(VID_FIR_COEF_V(1, 4));
325 SR(VID_FIR_COEF_V(1, 5));
326 SR(VID_FIR_COEF_V(1, 6));
327 SR(VID_FIR_COEF_V(1, 7));
332 void dispc_restore_context(void)
356 RR(GFX_FIFO_THRESHOLD);
377 RR(VID_ATTRIBUTES(0));
378 RR(VID_FIFO_THRESHOLD(0));
380 RR(VID_PIXEL_INC(0));
382 RR(VID_PICTURE_SIZE(0));
386 RR(VID_FIR_COEF_H(0, 0));
387 RR(VID_FIR_COEF_H(0, 1));
388 RR(VID_FIR_COEF_H(0, 2));
389 RR(VID_FIR_COEF_H(0, 3));
390 RR(VID_FIR_COEF_H(0, 4));
391 RR(VID_FIR_COEF_H(0, 5));
392 RR(VID_FIR_COEF_H(0, 6));
393 RR(VID_FIR_COEF_H(0, 7));
395 RR(VID_FIR_COEF_HV(0, 0));
396 RR(VID_FIR_COEF_HV(0, 1));
397 RR(VID_FIR_COEF_HV(0, 2));
398 RR(VID_FIR_COEF_HV(0, 3));
399 RR(VID_FIR_COEF_HV(0, 4));
400 RR(VID_FIR_COEF_HV(0, 5));
401 RR(VID_FIR_COEF_HV(0, 6));
402 RR(VID_FIR_COEF_HV(0, 7));
404 RR(VID_CONV_COEF(0, 0));
405 RR(VID_CONV_COEF(0, 1));
406 RR(VID_CONV_COEF(0, 2));
407 RR(VID_CONV_COEF(0, 3));
408 RR(VID_CONV_COEF(0, 4));
410 RR(VID_FIR_COEF_V(0, 0));
411 RR(VID_FIR_COEF_V(0, 1));
412 RR(VID_FIR_COEF_V(0, 2));
413 RR(VID_FIR_COEF_V(0, 3));
414 RR(VID_FIR_COEF_V(0, 4));
415 RR(VID_FIR_COEF_V(0, 5));
416 RR(VID_FIR_COEF_V(0, 6));
417 RR(VID_FIR_COEF_V(0, 7));
426 RR(VID_ATTRIBUTES(1));
427 RR(VID_FIFO_THRESHOLD(1));
429 RR(VID_PIXEL_INC(1));
431 RR(VID_PICTURE_SIZE(1));
435 RR(VID_FIR_COEF_H(1, 0));
436 RR(VID_FIR_COEF_H(1, 1));
437 RR(VID_FIR_COEF_H(1, 2));
438 RR(VID_FIR_COEF_H(1, 3));
439 RR(VID_FIR_COEF_H(1, 4));
440 RR(VID_FIR_COEF_H(1, 5));
441 RR(VID_FIR_COEF_H(1, 6));
442 RR(VID_FIR_COEF_H(1, 7));
444 RR(VID_FIR_COEF_HV(1, 0));
445 RR(VID_FIR_COEF_HV(1, 1));
446 RR(VID_FIR_COEF_HV(1, 2));
447 RR(VID_FIR_COEF_HV(1, 3));
448 RR(VID_FIR_COEF_HV(1, 4));
449 RR(VID_FIR_COEF_HV(1, 5));
450 RR(VID_FIR_COEF_HV(1, 6));
451 RR(VID_FIR_COEF_HV(1, 7));
453 RR(VID_CONV_COEF(1, 0));
454 RR(VID_CONV_COEF(1, 1));
455 RR(VID_CONV_COEF(1, 2));
456 RR(VID_CONV_COEF(1, 3));
457 RR(VID_CONV_COEF(1, 4));
459 RR(VID_FIR_COEF_V(1, 0));
460 RR(VID_FIR_COEF_V(1, 1));
461 RR(VID_FIR_COEF_V(1, 2));
462 RR(VID_FIR_COEF_V(1, 3));
463 RR(VID_FIR_COEF_V(1, 4));
464 RR(VID_FIR_COEF_V(1, 5));
465 RR(VID_FIR_COEF_V(1, 6));
466 RR(VID_FIR_COEF_V(1, 7));
470 /* enable last, because LCD & DIGIT enable are here */
477 static inline void enable_clocks(bool enable)
480 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
482 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
485 void dispc_go(enum omap_channel channel)
492 if (channel == OMAP_DSS_CHANNEL_LCD)
493 bit = 0; /* LCDENABLE */
495 bit = 1; /* DIGITALENABLE */
497 /* if the channel is not enabled, we don't need GO */
498 if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
501 if (channel == OMAP_DSS_CHANNEL_LCD)
504 bit = 6; /* GODIGIT */
506 tmo = jiffies + msecs_to_jiffies(200);
507 while (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
508 if (time_after(jiffies, tmo)) {
509 DSSERR("timeout waiting GO flag\n");
515 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
517 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
522 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
524 BUG_ON(plane == OMAP_DSS_GFX);
526 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
529 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
531 BUG_ON(plane == OMAP_DSS_GFX);
533 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
536 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
538 BUG_ON(plane == OMAP_DSS_GFX);
540 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
543 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
544 int vscaleup, int five_taps)
546 /* Coefficients for horizontal up-sampling */
547 static const u32 coef_hup[8] = {
558 /* Coefficients for horizontal down-sampling */
559 static const u32 coef_hdown[8] = {
570 /* Coefficients for horizontal and vertical up-sampling */
571 static const u32 coef_hvup[2][8] = {
594 /* Coefficients for horizontal and vertical down-sampling */
595 static const u32 coef_hvdown[2][8] = {
618 /* Coefficients for vertical up-sampling */
619 static const u32 coef_vup[8] = {
631 /* Coefficients for vertical down-sampling */
632 static const u32 coef_vdown[8] = {
645 const u32 *hv_coef_mod;
655 hv_coef = coef_hvup[five_taps];
661 hv_coef_mod = coef_hvdown[five_taps];
663 hv_coef = coef_hvdown[five_taps];
667 hv_coef_mod = coef_hvup[five_taps];
672 for (i = 0; i < 8; i++) {
681 hv |= (hv_coef_mod[i] & 0xff);
684 _dispc_write_firh_reg(plane, i, h);
685 _dispc_write_firhv_reg(plane, i, hv);
691 for (i = 0; i < 8; i++) {
694 _dispc_write_firv_reg(plane, i, v);
698 static void _dispc_setup_color_conv_coef(void)
700 const struct color_conv_coef {
701 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
704 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
707 const struct color_conv_coef *ct;
709 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
713 dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
714 dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
715 dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
716 dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
717 dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
719 dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
720 dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
721 dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
722 dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
723 dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
727 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
728 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
732 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
734 const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
738 dispc_write_reg(ba0_reg[plane], paddr);
741 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
743 const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
747 dispc_write_reg(ba1_reg[plane], paddr);
750 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
752 const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
753 DISPC_VID_POSITION(0),
754 DISPC_VID_POSITION(1) };
756 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
757 dispc_write_reg(pos_reg[plane], val);
760 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
762 const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
763 DISPC_VID_PICTURE_SIZE(0),
764 DISPC_VID_PICTURE_SIZE(1) };
765 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
766 dispc_write_reg(siz_reg[plane], val);
769 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
772 const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
775 BUG_ON(plane == OMAP_DSS_GFX);
777 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
778 dispc_write_reg(vsi_reg[plane-1], val);
781 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
783 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
784 DISPC_VID_PIXEL_INC(0),
785 DISPC_VID_PIXEL_INC(1) };
787 dispc_write_reg(ri_reg[plane], inc);
790 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
792 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
793 DISPC_VID_ROW_INC(0),
794 DISPC_VID_ROW_INC(1) };
796 dispc_write_reg(ri_reg[plane], inc);
799 static void _dispc_set_color_mode(enum omap_plane plane,
800 enum omap_color_mode color_mode)
804 switch (color_mode) {
805 case OMAP_DSS_COLOR_CLUT1:
807 case OMAP_DSS_COLOR_CLUT2:
809 case OMAP_DSS_COLOR_CLUT4:
811 case OMAP_DSS_COLOR_CLUT8:
813 case OMAP_DSS_COLOR_RGB12U:
815 case OMAP_DSS_COLOR_ARGB16:
817 case OMAP_DSS_COLOR_RGB16:
819 case OMAP_DSS_COLOR_RGB24U:
821 case OMAP_DSS_COLOR_RGB24P:
823 case OMAP_DSS_COLOR_YUV2:
825 case OMAP_DSS_COLOR_UYVY:
827 case OMAP_DSS_COLOR_ARGB32:
829 case OMAP_DSS_COLOR_RGBA32:
831 case OMAP_DSS_COLOR_RGBX32:
837 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
840 static void _dispc_set_channel_out(enum omap_plane plane,
841 enum omap_channel channel)
850 case OMAP_DSS_VIDEO1:
851 case OMAP_DSS_VIDEO2:
859 val = dispc_read_reg(dispc_reg_att[plane]);
860 val = FLD_MOD(val, channel, shift, shift);
861 dispc_write_reg(dispc_reg_att[plane], val);
864 void dispc_set_burst_size(enum omap_plane plane,
865 enum omap_burst_size burst_size)
876 case OMAP_DSS_VIDEO1:
877 case OMAP_DSS_VIDEO2:
885 val = dispc_read_reg(dispc_reg_att[plane]);
886 val = FLD_MOD(val, burst_size, shift+1, shift);
887 dispc_write_reg(dispc_reg_att[plane], val);
892 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
896 BUG_ON(plane == OMAP_DSS_GFX);
898 val = dispc_read_reg(dispc_reg_att[plane]);
899 val = FLD_MOD(val, enable, 9, 9);
900 dispc_write_reg(dispc_reg_att[plane], val);
903 void dispc_set_lcd_size(u16 width, u16 height)
906 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
907 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
909 dispc_write_reg(DISPC_SIZE_LCD, val);
913 void dispc_set_digit_size(u16 width, u16 height)
916 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
917 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
919 dispc_write_reg(DISPC_SIZE_DIG, val);
923 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
925 const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
926 DISPC_VID_FIFO_SIZE_STATUS(0),
927 DISPC_VID_FIFO_SIZE_STATUS(1) };
932 if (cpu_is_omap24xx())
933 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
934 else if (cpu_is_omap34xx())
935 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
939 if (cpu_is_omap34xx()) {
941 if (REG_GET(DISPC_CONFIG, 14, 14))
950 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
952 const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
953 DISPC_VID_FIFO_THRESHOLD(0),
954 DISPC_VID_FIFO_THRESHOLD(1) };
959 size = dispc_get_plane_fifo_size(plane);
961 BUG_ON(low > size || high > size);
963 DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n",
965 REG_GET(ftrs_reg[plane], 11, 0),
966 REG_GET(ftrs_reg[plane], 27, 16),
969 if (cpu_is_omap24xx())
970 dispc_write_reg(ftrs_reg[plane],
971 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
973 dispc_write_reg(ftrs_reg[plane],
974 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
979 void dispc_enable_fifomerge(bool enable)
983 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
984 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
989 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
992 const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
995 BUG_ON(plane == OMAP_DSS_GFX);
997 if (cpu_is_omap24xx())
998 val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
1000 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1001 dispc_write_reg(fir_reg[plane-1], val);
1004 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1007 const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1008 DISPC_VID_ACCU0(1) };
1010 BUG_ON(plane == OMAP_DSS_GFX);
1012 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1013 dispc_write_reg(ac0_reg[plane-1], val);
1016 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1019 const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1020 DISPC_VID_ACCU1(1) };
1022 BUG_ON(plane == OMAP_DSS_GFX);
1024 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1025 dispc_write_reg(ac1_reg[plane-1], val);
1029 static void _dispc_set_scaling(enum omap_plane plane,
1030 u16 orig_width, u16 orig_height,
1031 u16 out_width, u16 out_height,
1032 bool ilace, bool five_taps,
1037 int hscaleup, vscaleup;
1042 BUG_ON(plane == OMAP_DSS_GFX);
1044 hscaleup = orig_width <= out_width;
1045 vscaleup = orig_height <= out_height;
1047 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1049 if (!orig_width || orig_width == out_width)
1052 fir_hinc = 1024 * orig_width / out_width;
1054 if (!orig_height || orig_height == out_height)
1057 fir_vinc = 1024 * orig_height / out_height;
1059 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1061 l = dispc_read_reg(dispc_reg_att[plane]);
1062 l &= ~((0x0f << 5) | (0x3 << 21));
1064 l |= fir_hinc ? (1 << 5) : 0;
1065 l |= fir_vinc ? (1 << 6) : 0;
1067 l |= hscaleup ? 0 : (1 << 7);
1068 l |= vscaleup ? 0 : (1 << 8);
1070 l |= five_taps ? (1 << 21) : 0;
1071 l |= five_taps ? (1 << 22) : 0;
1073 dispc_write_reg(dispc_reg_att[plane], l);
1076 * field 0 = even field = bottom field
1077 * field 1 = odd field = top field
1079 if (ilace && !fieldmode) {
1081 accu0 = fir_vinc / 2;
1082 if (accu0 >= 1024/2) {
1088 _dispc_set_vid_accu0(plane, 0, accu0);
1089 _dispc_set_vid_accu1(plane, 0, accu1);
1092 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1093 bool mirroring, enum omap_color_mode color_mode)
1095 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1096 color_mode == OMAP_DSS_COLOR_UYVY) {
1101 case 0: vidrot = 2; break;
1102 case 1: vidrot = 3; break;
1103 case 2: vidrot = 0; break;
1104 case 3: vidrot = 1; break;
1108 case 0: vidrot = 0; break;
1109 case 1: vidrot = 1; break;
1110 case 2: vidrot = 2; break;
1111 case 3: vidrot = 3; break;
1115 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1117 if (rotation == 1 || rotation == 3)
1118 REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1120 REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1122 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1123 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1127 static s32 pixinc(int pixels, u8 ps)
1131 else if (pixels > 1)
1132 return 1 + (pixels - 1) * ps;
1133 else if (pixels < 0)
1134 return 1 - (-pixels + 1) * ps;
1139 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1141 u16 width, u16 height,
1142 enum omap_color_mode color_mode, bool fieldmode,
1143 unsigned *offset0, unsigned *offset1,
1144 s32 *row_inc, s32 *pix_inc)
1148 switch (color_mode) {
1149 case OMAP_DSS_COLOR_RGB16:
1150 case OMAP_DSS_COLOR_ARGB16:
1154 case OMAP_DSS_COLOR_RGB24P:
1158 case OMAP_DSS_COLOR_RGB24U:
1159 case OMAP_DSS_COLOR_ARGB32:
1160 case OMAP_DSS_COLOR_RGBA32:
1161 case OMAP_DSS_COLOR_RGBX32:
1162 case OMAP_DSS_COLOR_YUV2:
1163 case OMAP_DSS_COLOR_UYVY:
1172 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1174 switch (rotation + mirror * 4) {
1178 * If the pixel format is YUV or UYVY divide the width
1179 * of the image by 2 for 0 and 180 degree rotation.
1181 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1182 color_mode == OMAP_DSS_COLOR_UYVY)
1188 *offset1 = screen_width * ps;
1192 *row_inc = pixinc(1 + (screen_width - width) +
1193 (fieldmode ? screen_width : 0),
1195 *pix_inc = pixinc(1, ps);
1200 /* If the pixel format is YUV or UYVY divide the width
1201 * of the image by 2 for 0 degree and 180 degree
1203 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1204 color_mode == OMAP_DSS_COLOR_UYVY)
1210 *offset1 = screen_width * ps;
1213 *row_inc = pixinc(1 - (screen_width + width) -
1214 (fieldmode ? screen_width : 0),
1216 *pix_inc = pixinc(1, ps);
1224 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1226 u16 width, u16 height,
1227 enum omap_color_mode color_mode, bool fieldmode,
1228 unsigned *offset0, unsigned *offset1,
1229 s32 *row_inc, s32 *pix_inc)
1234 switch (color_mode) {
1235 case OMAP_DSS_COLOR_RGB16:
1236 case OMAP_DSS_COLOR_ARGB16:
1240 case OMAP_DSS_COLOR_RGB24P:
1244 case OMAP_DSS_COLOR_RGB24U:
1245 case OMAP_DSS_COLOR_ARGB32:
1246 case OMAP_DSS_COLOR_RGBA32:
1247 case OMAP_DSS_COLOR_RGBX32:
1251 case OMAP_DSS_COLOR_YUV2:
1252 case OMAP_DSS_COLOR_UYVY:
1260 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1263 /* width & height are overlay sizes, convert to fb sizes */
1265 if (rotation == 0 || rotation == 2) {
1274 * field 0 = even field = bottom field
1275 * field 1 = odd field = top field
1277 switch (rotation + mirror * 4) {
1281 *offset0 = screen_width * ps;
1284 *row_inc = pixinc(1 + (screen_width - fbw) +
1285 (fieldmode ? screen_width : 0),
1287 *pix_inc = pixinc(1, ps);
1290 *offset1 = screen_width * (fbh - 1) * ps;
1292 *offset0 = *offset1 + ps;
1294 *offset0 = *offset1;
1295 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1296 (fieldmode ? 1 : 0), ps);
1297 *pix_inc = pixinc(-screen_width, ps);
1300 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1302 *offset0 = *offset1 - screen_width * ps;
1304 *offset0 = *offset1;
1305 *row_inc = pixinc(-1 -
1306 (screen_width - fbw) -
1307 (fieldmode ? screen_width : 0),
1309 *pix_inc = pixinc(-1, ps);
1312 *offset1 = (fbw - 1) * ps;
1314 *offset0 = *offset1 - ps;
1316 *offset0 = *offset1;
1317 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1318 (fieldmode ? 1 : 0), ps);
1319 *pix_inc = pixinc(screen_width, ps);
1324 *offset1 = (fbw - 1) * ps;
1326 *offset0 = *offset1 + screen_width * ps;
1328 *offset0 = *offset1;
1329 *row_inc = pixinc(screen_width * 2 - 1 +
1330 (fieldmode ? screen_width : 0),
1332 *pix_inc = pixinc(-1, ps);
1338 *offset0 = *offset1 + screen_width * ps;
1340 *offset0 = *offset1;
1341 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1342 (fieldmode ? 1 : 0),
1344 *pix_inc = pixinc(screen_width, ps);
1348 *offset1 = screen_width * (fbh - 1) * ps;
1350 *offset0 = *offset1 + screen_width * ps;
1352 *offset0 = *offset1;
1353 *row_inc = pixinc(1 - screen_width * 2 -
1354 (fieldmode ? screen_width : 0),
1356 *pix_inc = pixinc(1, ps);
1360 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1362 *offset0 = *offset1 + screen_width * ps;
1364 *offset0 = *offset1;
1365 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1366 (fieldmode ? 1 : 0),
1368 *pix_inc = pixinc(-screen_width, ps);
1376 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1377 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1380 /* FIXME venc pclk? */
1381 u64 tmp, pclk = dispc_pclk_rate();
1383 if (height > out_height) {
1384 /* FIXME get real display PPL */
1385 unsigned int ppl = 800;
1387 tmp = pclk * height * out_width;
1388 do_div(tmp, 2 * out_height * ppl);
1391 if (height > 2 * out_height) {
1392 tmp = pclk * (height - 2 * out_height) * out_width;
1393 do_div(tmp, 2 * out_height * (ppl - out_width));
1394 fclk = max(fclk, (u32) tmp);
1398 if (width > out_width) {
1400 do_div(tmp, out_width);
1401 fclk = max(fclk, (u32) tmp);
1403 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1410 static unsigned long calc_fclk(u16 width, u16 height,
1411 u16 out_width, u16 out_height)
1413 unsigned int hf, vf;
1416 * FIXME how to determine the 'A' factor
1417 * for the no downscaling case ?
1420 if (width > 3 * out_width)
1422 else if (width > 2 * out_width)
1424 else if (width > out_width)
1429 if (height > out_height)
1434 /* FIXME venc pclk? */
1435 return dispc_pclk_rate() * vf * hf;
1438 static int _dispc_setup_plane(enum omap_plane plane,
1439 enum omap_channel channel_out,
1440 u32 paddr, u16 screen_width,
1441 u16 pos_x, u16 pos_y,
1442 u16 width, u16 height,
1443 u16 out_width, u16 out_height,
1444 enum omap_color_mode color_mode,
1446 enum omap_dss_rotation_type rotation_type,
1447 u8 rotation, int mirror)
1449 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1453 unsigned offset0, offset1;
1456 u16 frame_height = height;
1461 if (ilace && height == out_height)
1470 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1472 height, pos_y, out_height);
1475 if (plane == OMAP_DSS_GFX) {
1476 if (width != out_width || height != out_height)
1479 switch (color_mode) {
1480 case OMAP_DSS_COLOR_ARGB16:
1481 case OMAP_DSS_COLOR_RGB16:
1482 case OMAP_DSS_COLOR_RGB24P:
1483 case OMAP_DSS_COLOR_RGB24U:
1484 case OMAP_DSS_COLOR_ARGB32:
1485 case OMAP_DSS_COLOR_RGBA32:
1486 case OMAP_DSS_COLOR_RGBX32:
1495 unsigned long fclk = 0;
1497 if (out_width < width / maxdownscale ||
1498 out_width > width * 8)
1501 if (out_height < height / maxdownscale ||
1502 out_height > height * 8)
1505 switch (color_mode) {
1506 case OMAP_DSS_COLOR_RGB16:
1507 case OMAP_DSS_COLOR_RGB24P:
1508 case OMAP_DSS_COLOR_RGB24U:
1509 case OMAP_DSS_COLOR_RGBX32:
1512 case OMAP_DSS_COLOR_ARGB16:
1513 case OMAP_DSS_COLOR_ARGB32:
1514 case OMAP_DSS_COLOR_RGBA32:
1515 if (plane == OMAP_DSS_VIDEO1)
1519 case OMAP_DSS_COLOR_YUV2:
1520 case OMAP_DSS_COLOR_UYVY:
1528 /* Must use 5-tap filter? */
1529 five_taps = height > out_height * 2;
1532 fclk = calc_fclk(width, height,
1533 out_width, out_height);
1535 /* Try 5-tap filter if 3-tap fclk is too high */
1536 if (cpu_is_omap34xx() && height > out_height &&
1537 fclk > dispc_fclk_rate())
1541 if (width > (2048 >> five_taps))
1545 fclk = calc_fclk_five_taps(width, height,
1546 out_width, out_height, color_mode);
1548 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1549 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1551 if (fclk > dispc_fclk_rate())
1555 if (rotation_type == OMAP_DSS_ROT_DMA)
1556 calc_dma_rotation_offset(rotation, mirror,
1557 screen_width, width, frame_height, color_mode,
1559 &offset0, &offset1, &row_inc, &pix_inc);
1561 calc_vrfb_rotation_offset(rotation, mirror,
1562 screen_width, width, frame_height, color_mode,
1564 &offset0, &offset1, &row_inc, &pix_inc);
1566 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1567 offset0, offset1, row_inc, pix_inc);
1569 _dispc_set_channel_out(plane, channel_out);
1570 _dispc_set_color_mode(plane, color_mode);
1572 _dispc_set_plane_ba0(plane, paddr + offset0);
1573 _dispc_set_plane_ba1(plane, paddr + offset1);
1575 _dispc_set_row_inc(plane, row_inc);
1576 _dispc_set_pix_inc(plane, pix_inc);
1578 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1579 out_width, out_height);
1581 _dispc_set_plane_pos(plane, pos_x, pos_y);
1583 _dispc_set_pic_size(plane, width, height);
1585 if (plane != OMAP_DSS_GFX) {
1586 _dispc_set_scaling(plane, width, height,
1587 out_width, out_height,
1588 ilace, five_taps, fieldmode);
1589 _dispc_set_vid_size(plane, out_width, out_height);
1590 _dispc_set_vid_color_conv(plane, cconv);
1593 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1598 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1600 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1603 static void dispc_disable_isr(void *data, u32 mask)
1605 struct completion *compl = data;
1609 static void _enable_lcd_out(bool enable)
1611 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1614 void dispc_enable_lcd_out(bool enable)
1616 struct completion frame_done_completion;
1622 /* When we disable LCD output, we need to wait until frame is done.
1623 * Otherwise the DSS is still working, and turning off the clocks
1624 * prevents DSS from going to OFF mode */
1625 is_on = REG_GET(DISPC_CONTROL, 0, 0);
1627 if (!enable && is_on) {
1628 init_completion(&frame_done_completion);
1630 r = omap_dispc_register_isr(dispc_disable_isr,
1631 &frame_done_completion,
1632 DISPC_IRQ_FRAMEDONE);
1635 DSSERR("failed to register FRAMEDONE isr\n");
1638 _enable_lcd_out(enable);
1640 if (!enable && is_on) {
1641 if (!wait_for_completion_timeout(&frame_done_completion,
1642 msecs_to_jiffies(100)))
1643 DSSERR("timeout waiting for FRAME DONE\n");
1645 r = omap_dispc_unregister_isr(dispc_disable_isr,
1646 &frame_done_completion,
1647 DISPC_IRQ_FRAMEDONE);
1650 DSSERR("failed to unregister FRAMEDONE isr\n");
1656 static void _enable_digit_out(bool enable)
1658 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1661 void dispc_enable_digit_out(bool enable)
1663 struct completion frame_done_completion;
1668 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1674 /* When we enable digit output, we'll get an extra digit
1675 * sync lost interrupt, that we need to ignore */
1676 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1677 omap_dispc_set_irqs();
1680 /* When we disable digit output, we need to wait until fields are done.
1681 * Otherwise the DSS is still working, and turning off the clocks
1682 * prevents DSS from going to OFF mode. And when enabling, we need to
1683 * wait for the extra sync losts */
1684 init_completion(&frame_done_completion);
1686 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1687 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1689 DSSERR("failed to register EVSYNC isr\n");
1691 _enable_digit_out(enable);
1693 /* XXX I understand from TRM that we should only wait for the
1694 * current field to complete. But it seems we have to wait
1695 * for both fields */
1696 if (!wait_for_completion_timeout(&frame_done_completion,
1697 msecs_to_jiffies(100)))
1698 DSSERR("timeout waiting for EVSYNC\n");
1700 if (!wait_for_completion_timeout(&frame_done_completion,
1701 msecs_to_jiffies(100)))
1702 DSSERR("timeout waiting for EVSYNC\n");
1704 r = omap_dispc_unregister_isr(dispc_disable_isr,
1705 &frame_done_completion,
1706 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1708 DSSERR("failed to unregister EVSYNC isr\n");
1711 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1712 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1713 omap_dispc_set_irqs();
1719 void dispc_lcd_enable_signal_polarity(bool act_high)
1722 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1726 void dispc_lcd_enable_signal(bool enable)
1729 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1733 void dispc_pck_free_enable(bool enable)
1736 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1740 void dispc_enable_fifohandcheck(bool enable)
1743 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1748 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1753 case OMAP_DSS_LCD_DISPLAY_STN:
1757 case OMAP_DSS_LCD_DISPLAY_TFT:
1767 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1771 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1774 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1779 void dispc_set_default_color(enum omap_channel channel, u32 color)
1781 const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1782 DISPC_DEFAULT_COLOR1 };
1785 dispc_write_reg(def_reg[channel], color);
1789 u32 dispc_get_default_color(enum omap_channel channel)
1791 const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1792 DISPC_DEFAULT_COLOR1 };
1795 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1796 channel != OMAP_DSS_CHANNEL_LCD);
1799 l = dispc_read_reg(def_reg[channel]);
1805 void dispc_set_trans_key(enum omap_channel ch,
1806 enum omap_dss_color_key_type type,
1809 const struct dispc_reg tr_reg[] = {
1810 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1813 if (ch == OMAP_DSS_CHANNEL_LCD)
1814 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1815 else /* OMAP_DSS_CHANNEL_DIGIT */
1816 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1818 dispc_write_reg(tr_reg[ch], trans_key);
1822 void dispc_get_trans_key(enum omap_channel ch,
1823 enum omap_dss_color_key_type *type,
1826 const struct dispc_reg tr_reg[] = {
1827 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1831 if (ch == OMAP_DSS_CHANNEL_LCD)
1832 *type = REG_GET(DISPC_CONFIG, 11, 11);
1833 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1834 *type = REG_GET(DISPC_CONFIG, 13, 13);
1840 *trans_key = dispc_read_reg(tr_reg[ch]);
1844 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1847 if (ch == OMAP_DSS_CHANNEL_LCD)
1848 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1849 else /* OMAP_DSS_CHANNEL_DIGIT */
1850 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1853 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1856 if (ch == OMAP_DSS_CHANNEL_LCD)
1857 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
1858 else /* OMAP_DSS_CHANNEL_DIGIT */
1859 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
1862 bool dispc_alpha_blending_enabled(enum omap_channel ch)
1867 if (ch == OMAP_DSS_CHANNEL_LCD)
1868 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1869 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1870 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1880 bool dispc_trans_key_enabled(enum omap_channel ch)
1885 if (ch == OMAP_DSS_CHANNEL_LCD)
1886 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1887 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1888 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1896 void dispc_set_tft_data_lines(u8 data_lines)
1900 switch (data_lines) {
1919 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
1923 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
1931 case OMAP_DSS_PARALLELMODE_BYPASS:
1936 case OMAP_DSS_PARALLELMODE_RFBI:
1941 case OMAP_DSS_PARALLELMODE_DSI:
1953 l = dispc_read_reg(DISPC_CONTROL);
1955 l = FLD_MOD(l, stallmode, 11, 11);
1956 l = FLD_MOD(l, gpout0, 15, 15);
1957 l = FLD_MOD(l, gpout1, 16, 16);
1959 dispc_write_reg(DISPC_CONTROL, l);
1964 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
1965 int vsw, int vfp, int vbp)
1967 u32 timing_h, timing_v;
1969 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
1970 BUG_ON(hsw < 1 || hsw > 64);
1971 BUG_ON(hfp < 1 || hfp > 256);
1972 BUG_ON(hbp < 1 || hbp > 256);
1974 BUG_ON(vsw < 1 || vsw > 64);
1975 BUG_ON(vfp < 0 || vfp > 255);
1976 BUG_ON(vbp < 0 || vbp > 255);
1978 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
1979 FLD_VAL(hbp-1, 27, 20);
1981 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
1982 FLD_VAL(vbp, 27, 20);
1984 BUG_ON(hsw < 1 || hsw > 256);
1985 BUG_ON(hfp < 1 || hfp > 4096);
1986 BUG_ON(hbp < 1 || hbp > 4096);
1988 BUG_ON(vsw < 1 || vsw > 256);
1989 BUG_ON(vfp < 0 || vfp > 4095);
1990 BUG_ON(vbp < 0 || vbp > 4095);
1992 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
1993 FLD_VAL(hbp-1, 31, 20);
1995 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
1996 FLD_VAL(vbp, 31, 20);
2000 dispc_write_reg(DISPC_TIMING_H, timing_h);
2001 dispc_write_reg(DISPC_TIMING_V, timing_v);
2005 /* change name to mode? */
2006 void dispc_set_lcd_timings(struct omap_video_timings *timings)
2008 unsigned xtot, ytot;
2009 unsigned long ht, vt;
2011 _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2012 timings->vsw, timings->vfp, timings->vbp);
2014 dispc_set_lcd_size(timings->x_res, timings->y_res);
2016 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2017 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2019 ht = (timings->pixel_clock * 1000) / xtot;
2020 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2022 DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2023 DSSDBG("pck %u\n", timings->pixel_clock);
2024 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2025 timings->hsw, timings->hfp, timings->hbp,
2026 timings->vsw, timings->vfp, timings->vbp);
2028 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2031 void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2033 BUG_ON(lck_div < 1);
2034 BUG_ON(pck_div < 2);
2037 dispc_write_reg(DISPC_DIVISOR,
2038 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2042 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2045 l = dispc_read_reg(DISPC_DIVISOR);
2046 *lck_div = FLD_GET(l, 23, 16);
2047 *pck_div = FLD_GET(l, 7, 0);
2050 unsigned long dispc_fclk_rate(void)
2052 unsigned long r = 0;
2054 if (dss_get_dispc_clk_source() == 0)
2055 r = dss_clk_get_rate(DSS_CLK_FCK1);
2057 #ifdef CONFIG_OMAP2_DSS_DSI
2058 r = dsi_get_dsi1_pll_rate();
2065 unsigned long dispc_lclk_rate(void)
2071 l = dispc_read_reg(DISPC_DIVISOR);
2073 lcd = FLD_GET(l, 23, 16);
2075 r = dispc_fclk_rate();
2080 unsigned long dispc_pclk_rate(void)
2086 l = dispc_read_reg(DISPC_DIVISOR);
2088 lcd = FLD_GET(l, 23, 16);
2089 pcd = FLD_GET(l, 7, 0);
2091 r = dispc_fclk_rate();
2093 return r / lcd / pcd;
2096 void dispc_dump_clocks(struct seq_file *s)
2102 dispc_get_lcd_divisor(&lcd, &pcd);
2104 seq_printf(s, "- dispc -\n");
2106 seq_printf(s, "dispc fclk source = %s\n",
2107 dss_get_dispc_clk_source() == 0 ?
2108 "dss1_alwon_fclk" : "dsi1_pll_fclk");
2110 seq_printf(s, "pixel clk = %lu / %d / %d = %lu\n",
2118 void dispc_dump_regs(struct seq_file *s)
2120 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2122 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2124 DUMPREG(DISPC_REVISION);
2125 DUMPREG(DISPC_SYSCONFIG);
2126 DUMPREG(DISPC_SYSSTATUS);
2127 DUMPREG(DISPC_IRQSTATUS);
2128 DUMPREG(DISPC_IRQENABLE);
2129 DUMPREG(DISPC_CONTROL);
2130 DUMPREG(DISPC_CONFIG);
2131 DUMPREG(DISPC_CAPABLE);
2132 DUMPREG(DISPC_DEFAULT_COLOR0);
2133 DUMPREG(DISPC_DEFAULT_COLOR1);
2134 DUMPREG(DISPC_TRANS_COLOR0);
2135 DUMPREG(DISPC_TRANS_COLOR1);
2136 DUMPREG(DISPC_LINE_STATUS);
2137 DUMPREG(DISPC_LINE_NUMBER);
2138 DUMPREG(DISPC_TIMING_H);
2139 DUMPREG(DISPC_TIMING_V);
2140 DUMPREG(DISPC_POL_FREQ);
2141 DUMPREG(DISPC_DIVISOR);
2142 DUMPREG(DISPC_GLOBAL_ALPHA);
2143 DUMPREG(DISPC_SIZE_DIG);
2144 DUMPREG(DISPC_SIZE_LCD);
2146 DUMPREG(DISPC_GFX_BA0);
2147 DUMPREG(DISPC_GFX_BA1);
2148 DUMPREG(DISPC_GFX_POSITION);
2149 DUMPREG(DISPC_GFX_SIZE);
2150 DUMPREG(DISPC_GFX_ATTRIBUTES);
2151 DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2152 DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2153 DUMPREG(DISPC_GFX_ROW_INC);
2154 DUMPREG(DISPC_GFX_PIXEL_INC);
2155 DUMPREG(DISPC_GFX_WINDOW_SKIP);
2156 DUMPREG(DISPC_GFX_TABLE_BA);
2158 DUMPREG(DISPC_DATA_CYCLE1);
2159 DUMPREG(DISPC_DATA_CYCLE2);
2160 DUMPREG(DISPC_DATA_CYCLE3);
2162 DUMPREG(DISPC_CPR_COEF_R);
2163 DUMPREG(DISPC_CPR_COEF_G);
2164 DUMPREG(DISPC_CPR_COEF_B);
2166 DUMPREG(DISPC_GFX_PRELOAD);
2168 DUMPREG(DISPC_VID_BA0(0));
2169 DUMPREG(DISPC_VID_BA1(0));
2170 DUMPREG(DISPC_VID_POSITION(0));
2171 DUMPREG(DISPC_VID_SIZE(0));
2172 DUMPREG(DISPC_VID_ATTRIBUTES(0));
2173 DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2174 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2175 DUMPREG(DISPC_VID_ROW_INC(0));
2176 DUMPREG(DISPC_VID_PIXEL_INC(0));
2177 DUMPREG(DISPC_VID_FIR(0));
2178 DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2179 DUMPREG(DISPC_VID_ACCU0(0));
2180 DUMPREG(DISPC_VID_ACCU1(0));
2182 DUMPREG(DISPC_VID_BA0(1));
2183 DUMPREG(DISPC_VID_BA1(1));
2184 DUMPREG(DISPC_VID_POSITION(1));
2185 DUMPREG(DISPC_VID_SIZE(1));
2186 DUMPREG(DISPC_VID_ATTRIBUTES(1));
2187 DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2188 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2189 DUMPREG(DISPC_VID_ROW_INC(1));
2190 DUMPREG(DISPC_VID_PIXEL_INC(1));
2191 DUMPREG(DISPC_VID_FIR(1));
2192 DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2193 DUMPREG(DISPC_VID_ACCU0(1));
2194 DUMPREG(DISPC_VID_ACCU1(1));
2196 DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2197 DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2198 DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2199 DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2200 DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2201 DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2202 DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2203 DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2204 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2205 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2206 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2207 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2208 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2209 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2210 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2211 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2212 DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2213 DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2214 DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2215 DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2216 DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2217 DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2218 DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2219 DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2220 DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2221 DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2222 DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2223 DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2224 DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2226 DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2227 DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2228 DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2229 DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2230 DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2231 DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2232 DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2233 DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2234 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2235 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2236 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2237 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2238 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2239 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2240 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2241 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2242 DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2243 DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2244 DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2245 DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2246 DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2247 DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2248 DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2249 DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2250 DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2251 DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2252 DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2253 DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2254 DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2256 DUMPREG(DISPC_VID_PRELOAD(0));
2257 DUMPREG(DISPC_VID_PRELOAD(1));
2259 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2263 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2264 bool ihs, bool ivs, u8 acbi, u8 acb)
2268 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2269 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2271 l |= FLD_VAL(onoff, 17, 17);
2272 l |= FLD_VAL(rf, 16, 16);
2273 l |= FLD_VAL(ieo, 15, 15);
2274 l |= FLD_VAL(ipc, 14, 14);
2275 l |= FLD_VAL(ihs, 13, 13);
2276 l |= FLD_VAL(ivs, 12, 12);
2277 l |= FLD_VAL(acbi, 11, 8);
2278 l |= FLD_VAL(acb, 7, 0);
2281 dispc_write_reg(DISPC_POL_FREQ, l);
2285 void dispc_set_pol_freq(struct omap_panel *panel)
2287 _dispc_set_pol_freq((panel->config & OMAP_DSS_LCD_ONOFF) != 0,
2288 (panel->config & OMAP_DSS_LCD_RF) != 0,
2289 (panel->config & OMAP_DSS_LCD_IEO) != 0,
2290 (panel->config & OMAP_DSS_LCD_IPC) != 0,
2291 (panel->config & OMAP_DSS_LCD_IHS) != 0,
2292 (panel->config & OMAP_DSS_LCD_IVS) != 0,
2293 panel->acbi, panel->acb);
2296 void find_lck_pck_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2297 u16 *lck_div, u16 *pck_div)
2299 u16 pcd_min = is_tft ? 2 : 3;
2300 unsigned long best_pck;
2301 u16 best_ld, cur_ld;
2302 u16 best_pd, cur_pd;
2308 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2309 unsigned long lck = fck / cur_ld;
2311 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2312 unsigned long pck = lck / cur_pd;
2313 long old_delta = abs(best_pck - req_pck);
2314 long new_delta = abs(pck - req_pck);
2316 if (best_pck == 0 || new_delta < old_delta) {
2329 if (lck / pcd_min < req_pck)
2338 int dispc_calc_clock_div(bool is_tft, unsigned long req_pck,
2339 struct dispc_clock_info *cinfo)
2341 unsigned long prate;
2342 struct dispc_clock_info cur, best;
2344 int min_fck_per_pck;
2345 unsigned long fck_rate = dss_clk_get_rate(DSS_CLK_FCK1);
2347 if (cpu_is_omap34xx())
2348 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2352 if (req_pck == dispc.cache_req_pck &&
2353 ((cpu_is_omap34xx() && prate == dispc.cache_prate) ||
2354 dispc.cache_cinfo.fck == fck_rate)) {
2355 DSSDBG("dispc clock info found from cache.\n");
2356 *cinfo = dispc.cache_cinfo;
2360 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
2362 if (min_fck_per_pck &&
2363 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
2364 DSSERR("Requested pixel clock not possible with the current "
2365 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
2366 "the constraint off.\n");
2367 min_fck_per_pck = 0;
2371 memset(&cur, 0, sizeof(cur));
2372 memset(&best, 0, sizeof(best));
2374 if (cpu_is_omap24xx()) {
2375 /* XXX can we change the clock on omap2? */
2376 cur.fck = dss_clk_get_rate(DSS_CLK_FCK1);
2381 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2382 &cur.lck_div, &cur.pck_div);
2384 cur.lck = cur.fck / cur.lck_div;
2385 cur.pck = cur.lck / cur.pck_div;
2390 } else if (cpu_is_omap34xx()) {
2391 for (cur.fck_div = 16; cur.fck_div > 0; --cur.fck_div) {
2392 cur.fck = prate / cur.fck_div * 2;
2394 if (cur.fck > DISPC_MAX_FCK)
2397 if (min_fck_per_pck &&
2398 cur.fck < req_pck * min_fck_per_pck)
2403 find_lck_pck_divs(is_tft, req_pck, cur.fck,
2404 &cur.lck_div, &cur.pck_div);
2406 cur.lck = cur.fck / cur.lck_div;
2407 cur.pck = cur.lck / cur.pck_div;
2409 if (abs(cur.pck - req_pck) < abs(best.pck - req_pck)) {
2412 if (cur.pck == req_pck)
2422 if (min_fck_per_pck) {
2423 DSSERR("Could not find suitable clock settings.\n"
2424 "Turning FCK/PCK constraint off and"
2426 min_fck_per_pck = 0;
2430 DSSERR("Could not find suitable clock settings.\n");
2438 dispc.cache_req_pck = req_pck;
2439 dispc.cache_prate = prate;
2440 dispc.cache_cinfo = best;
2445 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2447 unsigned long prate;
2450 if (cpu_is_omap34xx()) {
2451 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2452 DSSDBG("dpll4_m4 = %ld\n", prate);
2455 DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
2456 DSSDBG("lck = %ld (%d)\n", cinfo->lck, cinfo->lck_div);
2457 DSSDBG("pck = %ld (%d)\n", cinfo->pck, cinfo->pck_div);
2459 if (cpu_is_omap34xx()) {
2460 r = clk_set_rate(dispc.dpll4_m4_ck, prate / cinfo->fck_div);
2465 dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2470 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2472 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1);
2474 if (cpu_is_omap34xx()) {
2475 unsigned long prate;
2476 prate = clk_get_rate(clk_get_parent(dispc.dpll4_m4_ck));
2477 cinfo->fck_div = prate / (cinfo->fck / 2);
2482 cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2483 cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2485 cinfo->lck = cinfo->fck / cinfo->lck_div;
2486 cinfo->pck = cinfo->lck / cinfo->pck_div;
2491 static void omap_dispc_set_irqs(void)
2493 unsigned long flags;
2494 u32 mask = dispc.irq_error_mask;
2496 struct omap_dispc_isr_data *isr_data;
2498 spin_lock_irqsave(&dispc.irq_lock, flags);
2500 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2501 isr_data = &dispc.registered_isr[i];
2503 if (isr_data->isr == NULL)
2506 mask |= isr_data->mask;
2510 dispc_write_reg(DISPC_IRQENABLE, mask);
2513 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2516 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2520 unsigned long flags;
2521 struct omap_dispc_isr_data *isr_data;
2526 spin_lock_irqsave(&dispc.irq_lock, flags);
2528 /* check for duplicate entry */
2529 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2530 isr_data = &dispc.registered_isr[i];
2531 if (isr_data->isr == isr && isr_data->arg == arg &&
2532 isr_data->mask == mask) {
2541 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2542 isr_data = &dispc.registered_isr[i];
2544 if (isr_data->isr != NULL)
2547 isr_data->isr = isr;
2548 isr_data->arg = arg;
2549 isr_data->mask = mask;
2555 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2558 omap_dispc_set_irqs();
2562 EXPORT_SYMBOL(omap_dispc_register_isr);
2564 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2567 unsigned long flags;
2569 struct omap_dispc_isr_data *isr_data;
2571 spin_lock_irqsave(&dispc.irq_lock, flags);
2573 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2574 isr_data = &dispc.registered_isr[i];
2575 if (isr_data->isr != isr || isr_data->arg != arg ||
2576 isr_data->mask != mask)
2579 /* found the correct isr */
2581 isr_data->isr = NULL;
2582 isr_data->arg = NULL;
2589 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2592 omap_dispc_set_irqs();
2596 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2599 static void print_irq_status(u32 status)
2601 if ((status & dispc.irq_error_mask) == 0)
2604 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2607 if (status & DISPC_IRQ_##x) \
2609 PIS(GFX_FIFO_UNDERFLOW);
2611 PIS(VID1_FIFO_UNDERFLOW);
2612 PIS(VID2_FIFO_UNDERFLOW);
2614 PIS(SYNC_LOST_DIGIT);
2621 /* Called from dss.c. Note that we don't touch clocks here,
2622 * but we presume they are on because we got an IRQ. However,
2623 * an irq handler may turn the clocks off, so we may not have
2624 * clock later in the function. */
2625 void dispc_irq_handler(void)
2628 u32 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2629 u32 handledirqs = 0;
2630 u32 unhandled_errors;
2631 struct omap_dispc_isr_data *isr_data;
2635 print_irq_status(irqstatus);
2637 /* Ack the interrupt. Do it here before clocks are possibly turned
2639 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2641 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2642 isr_data = &dispc.registered_isr[i];
2647 if (isr_data->mask & irqstatus) {
2648 isr_data->isr(isr_data->arg, irqstatus);
2649 handledirqs |= isr_data->mask;
2653 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2655 if (unhandled_errors) {
2656 spin_lock(&dispc.error_lock);
2657 dispc.error_irqs |= unhandled_errors;
2658 spin_unlock(&dispc.error_lock);
2660 dispc.irq_error_mask &= ~unhandled_errors;
2661 omap_dispc_set_irqs();
2663 schedule_work(&dispc.error_work);
2667 static void dispc_error_worker(struct work_struct *work)
2671 unsigned long flags;
2673 spin_lock_irqsave(&dispc.error_lock, flags);
2674 errors = dispc.error_irqs;
2675 dispc.error_irqs = 0;
2676 spin_unlock_irqrestore(&dispc.error_lock, flags);
2678 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2679 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2680 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2681 struct omap_overlay *ovl;
2682 ovl = omap_dss_get_overlay(i);
2684 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2688 dispc_enable_plane(ovl->id, 0);
2689 dispc_go(ovl->manager->id);
2696 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2697 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2698 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2699 struct omap_overlay *ovl;
2700 ovl = omap_dss_get_overlay(i);
2702 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2706 dispc_enable_plane(ovl->id, 0);
2707 dispc_go(ovl->manager->id);
2714 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2715 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2716 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2717 struct omap_overlay *ovl;
2718 ovl = omap_dss_get_overlay(i);
2720 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2724 dispc_enable_plane(ovl->id, 0);
2725 dispc_go(ovl->manager->id);
2732 if (errors & DISPC_IRQ_SYNC_LOST) {
2733 struct omap_overlay_manager *manager = NULL;
2734 bool enable = false;
2736 DSSERR("SYNC_LOST, disabling LCD\n");
2738 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2739 struct omap_overlay_manager *mgr;
2740 mgr = omap_dss_get_overlay_manager(i);
2742 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2744 enable = mgr->display->state ==
2745 OMAP_DSS_DISPLAY_ACTIVE;
2746 mgr->display->disable(mgr->display);
2752 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2753 struct omap_overlay *ovl;
2754 ovl = omap_dss_get_overlay(i);
2756 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2759 if (ovl->id != 0 && ovl->manager == manager)
2760 dispc_enable_plane(ovl->id, 0);
2763 dispc_go(manager->id);
2766 manager->display->enable(manager->display);
2770 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2771 struct omap_overlay_manager *manager = NULL;
2772 bool enable = false;
2774 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2776 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2777 struct omap_overlay_manager *mgr;
2778 mgr = omap_dss_get_overlay_manager(i);
2780 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2782 enable = mgr->display->state ==
2783 OMAP_DSS_DISPLAY_ACTIVE;
2784 mgr->display->disable(mgr->display);
2790 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2791 struct omap_overlay *ovl;
2792 ovl = omap_dss_get_overlay(i);
2794 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2797 if (ovl->id != 0 && ovl->manager == manager)
2798 dispc_enable_plane(ovl->id, 0);
2801 dispc_go(manager->id);
2804 manager->display->enable(manager->display);
2808 if (errors & DISPC_IRQ_OCP_ERR) {
2809 DSSERR("OCP_ERR\n");
2810 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2811 struct omap_overlay_manager *mgr;
2812 mgr = omap_dss_get_overlay_manager(i);
2814 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2815 mgr->display->disable(mgr->display);
2819 dispc.irq_error_mask |= errors;
2820 omap_dispc_set_irqs();
2823 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2825 void dispc_irq_wait_handler(void *data, u32 mask)
2827 complete((struct completion *)data);
2831 DECLARE_COMPLETION_ONSTACK(completion);
2833 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2839 timeout = wait_for_completion_timeout(&completion, timeout);
2841 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2846 if (timeout == -ERESTARTSYS)
2847 return -ERESTARTSYS;
2852 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2853 unsigned long timeout)
2855 void dispc_irq_wait_handler(void *data, u32 mask)
2857 complete((struct completion *)data);
2861 DECLARE_COMPLETION_ONSTACK(completion);
2863 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2869 timeout = wait_for_completion_interruptible_timeout(&completion,
2872 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2877 if (timeout == -ERESTARTSYS)
2878 return -ERESTARTSYS;
2883 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2884 void dispc_fake_vsync_irq(void)
2886 u32 irqstatus = DISPC_IRQ_VSYNC;
2889 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2890 struct omap_dispc_isr_data *isr_data;
2891 isr_data = &dispc.registered_isr[i];
2896 if (isr_data->mask & irqstatus)
2897 isr_data->isr(isr_data->arg, irqstatus);
2902 static void _omap_dispc_initialize_irq(void)
2904 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
2906 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2908 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
2910 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
2912 omap_dispc_set_irqs();
2915 void dispc_enable_sidle(void)
2917 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
2920 void dispc_disable_sidle(void)
2922 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
2925 static void _omap_dispc_initial_config(void)
2929 l = dispc_read_reg(DISPC_SYSCONFIG);
2930 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
2931 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
2932 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
2933 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
2934 dispc_write_reg(DISPC_SYSCONFIG, l);
2937 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
2939 /* L3 firewall setting: enable access to OCM RAM */
2940 if (cpu_is_omap24xx())
2941 __raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
2943 _dispc_setup_color_conv_coef();
2945 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
2948 int dispc_init(void)
2952 spin_lock_init(&dispc.irq_lock);
2953 spin_lock_init(&dispc.error_lock);
2955 INIT_WORK(&dispc.error_work, dispc_error_worker);
2957 dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
2959 DSSERR("can't ioremap DISPC\n");
2963 if (cpu_is_omap34xx()) {
2964 dispc.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
2965 if (IS_ERR(dispc.dpll4_m4_ck)) {
2966 DSSERR("Failed to get dpll4_m4_ck\n");
2973 _omap_dispc_initial_config();
2975 _omap_dispc_initialize_irq();
2977 dispc_save_context();
2979 rev = dispc_read_reg(DISPC_REVISION);
2980 printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
2981 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
2988 void dispc_exit(void)
2990 if (cpu_is_omap34xx())
2991 clk_put(dispc.dpll4_m4_ck);
2992 iounmap(dispc.base);
2995 int dispc_enable_plane(enum omap_plane plane, bool enable)
2997 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3000 _dispc_enable_plane(plane, enable);
3006 int dispc_setup_plane(enum omap_plane plane, enum omap_channel channel_out,
3007 u32 paddr, u16 screen_width,
3008 u16 pos_x, u16 pos_y,
3009 u16 width, u16 height,
3010 u16 out_width, u16 out_height,
3011 enum omap_color_mode color_mode,
3013 enum omap_dss_rotation_type rotation_type,
3014 u8 rotation, bool mirror)
3018 DSSDBG("dispc_setup_plane %d, ch %d, pa %x, sw %d, %d,%d, %dx%d -> "
3019 "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3020 plane, channel_out, paddr, screen_width, pos_x, pos_y,
3022 out_width, out_height,
3028 r = _dispc_setup_plane(plane, channel_out,
3029 paddr, screen_width,
3032 out_width, out_height,
3042 static int dispc_is_intersecting(int x1, int y1, int w1, int h1,
3043 int x2, int y2, int w2, int h2)
3060 static int dispc_is_overlay_scaled(struct omap_overlay_info *pi)
3062 if (pi->width != pi->out_width)
3065 if (pi->height != pi->out_height)
3071 /* returns the area that needs updating */
3072 void dispc_setup_partial_planes(struct omap_display *display,
3073 u16 *xi, u16 *yi, u16 *wi, u16 *hi)
3075 struct omap_overlay_manager *mgr;
3085 DSSDBG("dispc_setup_partial_planes %d,%d %dx%d\n",
3086 *xi, *yi, *wi, *hi);
3089 mgr = display->manager;
3092 DSSDBG("no manager\n");
3096 for (i = 0; i < mgr->num_overlays; i++) {
3097 struct omap_overlay *ovl;
3098 struct omap_overlay_info *pi;
3099 ovl = mgr->overlays[i];
3101 if (ovl->manager != mgr)
3104 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
3112 * If the plane is intersecting and scaled, we
3113 * enlarge the update region to accomodate the
3117 if (dispc_is_intersecting(x, y, w, h,
3118 pi->pos_x, pi->pos_y,
3119 pi->out_width, pi->out_height)) {
3120 if (dispc_is_overlay_scaled(pi)) {
3134 if ((x + w) < (pi->pos_x + pi->out_width))
3135 x2 = pi->pos_x + pi->out_width;
3139 if ((y + h) < (pi->pos_y + pi->out_height))
3140 y2 = pi->pos_y + pi->out_height;
3149 DSSDBG("Update area after enlarge due to "
3150 "scaling %d, %d %dx%d\n",
3156 for (i = 0; i < mgr->num_overlays; i++) {
3157 struct omap_overlay *ovl = mgr->overlays[i];
3158 struct omap_overlay_info *pi = &ovl->info;
3163 int ph = pi->height;
3164 int pow = pi->out_width;
3165 int poh = pi->out_height;
3167 int psw = pi->screen_width;
3170 if (ovl->manager != mgr)
3174 * If plane is not enabled or the update region
3175 * does not intersect with the plane in question,
3176 * we really disable the plane from hardware
3180 !dispc_is_intersecting(x, y, w, h,
3181 px, py, pow, poh)) {
3182 dispc_enable_plane(ovl->id, 0);
3186 switch (pi->color_mode) {
3187 case OMAP_DSS_COLOR_RGB16:
3188 case OMAP_DSS_COLOR_ARGB16:
3189 case OMAP_DSS_COLOR_YUV2:
3190 case OMAP_DSS_COLOR_UYVY:
3194 case OMAP_DSS_COLOR_RGB24P:
3198 case OMAP_DSS_COLOR_RGB24U:
3199 case OMAP_DSS_COLOR_ARGB32:
3200 case OMAP_DSS_COLOR_RGBA32:
3201 case OMAP_DSS_COLOR_RGBX32:
3210 if (x > pi->pos_x) {
3212 pw -= (x - pi->pos_x);
3213 pa += (x - pi->pos_x) * bpp / 8;
3218 if (y > pi->pos_y) {
3220 ph -= (y - pi->pos_y);
3221 pa += (y - pi->pos_y) * psw * bpp / 8;
3227 pw -= (px+pw) - (w);
3230 ph -= (py+ph) - (h);
3232 /* Can't scale the GFX plane */
3233 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0 ||
3234 dispc_is_overlay_scaled(pi) == 0) {
3239 DSSDBG("calc plane %d, %x, sw %d, %d,%d, %dx%d -> %dx%d\n",
3240 ovl->id, pa, psw, px, py, pw, ph, pow, poh);
3242 dispc_setup_plane(ovl->id, mgr->id,
3252 dispc_enable_plane(ovl->id, 1);