2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/gfp.h>
24 #include <asm/unaligned.h>
28 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
29 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
30 PORT_RC | PORT_PLC | PORT_PE)
32 /* usb 1.1 root hub device descriptor */
33 static u8 usb_bos_descriptor [] = {
34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
35 USB_DT_BOS, /* __u8 bDescriptorType */
36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
37 0x1, /* __u8 bNumDeviceCaps */
38 /* First device capability */
39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
42 0x00, /* bmAttributes, LTM off by default */
43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
44 0x03, /* bFunctionalitySupport,
46 0x00, /* bU1DevExitLat, set later. */
47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
51 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
52 struct usb_hub_descriptor *desc, int ports)
56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
57 desc->bHubContrCurrent = 0;
59 desc->bNbrPorts = ports;
60 /* Ugh, these should be #defines, FIXME */
61 /* Using table 11-13 in USB 2.0 spec. */
63 /* Bits 1:0 - support port power switching, or power always on */
64 if (HCC_PPC(xhci->hcc_params))
68 /* Bit 2 - root hubs are not part of a compound device */
69 /* Bits 4:3 - individual port over current protection */
71 /* Bits 6:5 - no TTs in root ports */
72 /* Bit 7 - no port indicators */
73 desc->wHubCharacteristics = cpu_to_le16(temp);
76 /* Fill in the USB 2.0 roothub descriptor */
77 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
78 struct usb_hub_descriptor *desc)
82 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
86 ports = xhci->num_usb2_ports;
88 xhci_common_hub_descriptor(xhci, desc, ports);
89 desc->bDescriptorType = 0x29;
90 temp = 1 + (ports / 8);
91 desc->bDescLength = 7 + 2 * temp;
93 /* The Device Removable bits are reported on a byte granularity.
94 * If the port doesn't exist within that byte, the bit is set to 0.
96 memset(port_removable, 0, sizeof(port_removable));
97 for (i = 0; i < ports; i++) {
98 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
99 /* If a device is removable, PORTSC reports a 0, same as in the
100 * hub descriptor DeviceRemovable bits.
102 if (portsc & PORT_DEV_REMOVE)
103 /* This math is hairy because bit 0 of DeviceRemovable
104 * is reserved, and bit 1 is for port 1, etc.
106 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
109 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
110 * ports on it. The USB 2.0 specification says that there are two
111 * variable length fields at the end of the hub descriptor:
112 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
113 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
114 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
115 * 0xFF, so we initialize the both arrays (DeviceRemovable and
116 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
117 * set of ports that actually exist.
119 memset(desc->u.hs.DeviceRemovable, 0xff,
120 sizeof(desc->u.hs.DeviceRemovable));
121 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
122 sizeof(desc->u.hs.PortPwrCtrlMask));
124 for (i = 0; i < (ports + 1 + 7) / 8; i++)
125 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
129 /* Fill in the USB 3.0 roothub descriptor */
130 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
131 struct usb_hub_descriptor *desc)
138 ports = xhci->num_usb3_ports;
139 xhci_common_hub_descriptor(xhci, desc, ports);
140 desc->bDescriptorType = 0x2a;
141 desc->bDescLength = 12;
143 /* header decode latency should be zero for roothubs,
144 * see section 4.23.5.2.
146 desc->u.ss.bHubHdrDecLat = 0;
147 desc->u.ss.wHubDelay = 0;
150 /* bit 0 is reserved, bit 1 is for port 1, etc. */
151 for (i = 0; i < ports; i++) {
152 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
153 if (portsc & PORT_DEV_REMOVE)
154 port_removable |= 1 << (i + 1);
156 memset(&desc->u.ss.DeviceRemovable,
157 (__force __u16) cpu_to_le16(port_removable),
161 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
162 struct usb_hub_descriptor *desc)
165 if (hcd->speed == HCD_USB3)
166 xhci_usb3_hub_descriptor(hcd, xhci, desc);
168 xhci_usb2_hub_descriptor(hcd, xhci, desc);
172 static unsigned int xhci_port_speed(unsigned int port_status)
174 if (DEV_LOWSPEED(port_status))
175 return USB_PORT_STAT_LOW_SPEED;
176 if (DEV_HIGHSPEED(port_status))
177 return USB_PORT_STAT_HIGH_SPEED;
179 * FIXME: Yes, we should check for full speed, but the core uses that as
180 * a default in portspeed() in usb/core/hub.c (which is the only place
181 * USB_PORT_STAT_*_SPEED is used).
187 * These bits are Read Only (RO) and should be saved and written to the
188 * registers: 0, 3, 10:13, 30
189 * connect status, over-current status, port speed, and device removable.
190 * connect status and port speed are also sticky - meaning they're in
191 * the AUX well and they aren't changed by a hot, warm, or cold reset.
193 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
195 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
196 * bits 5:8, 9, 14:15, 25:27
197 * link state, port power, port indicator state, "wake on" enable state
199 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
201 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
204 #define XHCI_PORT_RW1S ((1<<4))
206 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
207 * bits 1, 17, 18, 19, 20, 21, 22, 23
208 * port enable/disable, and
209 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
210 * over-current, reset, link state, and L1 change
212 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
214 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
217 #define XHCI_PORT_RW ((1<<16))
219 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
222 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
225 * Given a port state, this function returns a value that would result in the
226 * port being in the same state, if the value was written to the port status
228 * Save Read Only (RO) bits and save read/write bits where
229 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
230 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
232 u32 xhci_port_state_to_neutral(u32 state)
234 /* Save read-only status and port state */
235 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
239 * find slot id based on port number.
240 * @port: The one-based port number from one of the two split roothubs.
242 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
247 enum usb_device_speed speed;
250 for (i = 0; i < MAX_HC_SLOTS; i++) {
253 speed = xhci->devs[i]->udev->speed;
254 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
255 && xhci->devs[i]->fake_port == port) {
266 * It issues stop endpoint command for EP 0 to 30. And wait the last command
268 * suspend will set to 1, if suspend bit need to set in command.
270 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
272 struct xhci_virt_device *virt_dev;
273 struct xhci_command *cmd;
280 virt_dev = xhci->devs[slot_id];
284 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
286 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
290 spin_lock_irqsave(&xhci->lock, flags);
291 for (i = LAST_EP_INDEX; i > 0; i--) {
292 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
293 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
295 cmd->command_trb = xhci->cmd_ring->enqueue;
296 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
297 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
298 xhci_ring_cmd_db(xhci);
299 spin_unlock_irqrestore(&xhci->lock, flags);
301 /* Wait for last stop endpoint command to finish */
302 timeleft = wait_for_completion_interruptible_timeout(
304 USB_CTRL_SET_TIMEOUT);
306 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
307 timeleft == 0 ? "Timeout" : "Signal");
308 spin_lock_irqsave(&xhci->lock, flags);
309 /* The timeout might have raced with the event ring handler, so
310 * only delete from the list if the item isn't poisoned.
312 if (cmd->cmd_list.next != LIST_POISON1)
313 list_del(&cmd->cmd_list);
314 spin_unlock_irqrestore(&xhci->lock, flags);
316 goto command_cleanup;
320 xhci_free_command(xhci, cmd);
325 * Ring device, it rings the all doorbells unconditionally.
327 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
331 for (i = 0; i < LAST_EP_INDEX + 1; i++)
332 if (xhci->devs[slot_id]->eps[i].ring &&
333 xhci->devs[slot_id]->eps[i].ring->dequeue)
334 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
339 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
340 u16 wIndex, __le32 __iomem *addr, u32 port_status)
342 /* Don't allow the USB core to disable SuperSpeed ports. */
343 if (hcd->speed == HCD_USB3) {
344 xhci_dbg(xhci, "Ignoring request to disable "
345 "SuperSpeed port.\n");
349 /* Write 1 to disable the port */
350 xhci_writel(xhci, port_status | PORT_PE, addr);
351 port_status = xhci_readl(xhci, addr);
352 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
353 wIndex, port_status);
356 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
357 u16 wIndex, __le32 __iomem *addr, u32 port_status)
359 char *port_change_bit;
363 case USB_PORT_FEAT_C_RESET:
365 port_change_bit = "reset";
367 case USB_PORT_FEAT_C_BH_PORT_RESET:
369 port_change_bit = "warm(BH) reset";
371 case USB_PORT_FEAT_C_CONNECTION:
373 port_change_bit = "connect";
375 case USB_PORT_FEAT_C_OVER_CURRENT:
377 port_change_bit = "over-current";
379 case USB_PORT_FEAT_C_ENABLE:
381 port_change_bit = "enable/disable";
383 case USB_PORT_FEAT_C_SUSPEND:
385 port_change_bit = "suspend/resume";
387 case USB_PORT_FEAT_C_PORT_LINK_STATE:
389 port_change_bit = "link state";
391 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
393 port_change_bit = "config error";
396 /* Should never happen */
399 /* Change bits are all write 1 to clear */
400 xhci_writel(xhci, port_status | status, addr);
401 port_status = xhci_readl(xhci, addr);
402 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
403 port_change_bit, wIndex, port_status);
406 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
409 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
411 if (hcd->speed == HCD_USB3) {
412 max_ports = xhci->num_usb3_ports;
413 *port_array = xhci->usb3_ports;
415 max_ports = xhci->num_usb2_ports;
416 *port_array = xhci->usb2_ports;
422 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
423 int port_id, u32 link_state)
427 temp = xhci_readl(xhci, port_array[port_id]);
428 temp = xhci_port_state_to_neutral(temp);
429 temp &= ~PORT_PLS_MASK;
430 temp |= PORT_LINK_STROBE | link_state;
431 xhci_writel(xhci, temp, port_array[port_id]);
434 /* Test and clear port RWC bit */
435 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
436 int port_id, u32 port_bit)
440 temp = xhci_readl(xhci, port_array[port_id]);
441 if (temp & port_bit) {
442 temp = xhci_port_state_to_neutral(temp);
444 xhci_writel(xhci, temp, port_array[port_id]);
448 /* Updates Link Status for super Speed port */
449 static void xhci_hub_report_link_state(struct xhci_hcd *xhci,
450 u32 *status, u32 status_reg)
452 u32 pls = status_reg & PORT_PLS_MASK;
454 /* resume state is a xHCI internal state.
455 * Do not report it to usb core, instead, pretend to be U3,
456 * thus usb core knows it's not ready for transfer
458 if (pls == XDEV_RESUME) {
459 *status |= USB_SS_PORT_LS_U3;
463 /* When the CAS bit is set then warm reset
464 * should be performed on port
466 if (status_reg & PORT_CAS) {
467 /* The CAS bit can be set while the port is
469 * Only roothubs have CAS bit, so we
470 * pretend to be in compliance mode
471 * unless we're already in compliance
472 * or the inactive state.
474 if (pls != USB_SS_PORT_LS_COMP_MOD &&
475 pls != USB_SS_PORT_LS_SS_INACTIVE) {
476 pls = USB_SS_PORT_LS_COMP_MOD;
478 /* Return also connection bit -
479 * hub state machine resets port
480 * when this bit is set.
482 pls |= USB_PORT_STAT_CONNECTION;
485 * If CAS bit isn't set but the Port is already at
486 * Compliance Mode, fake a connection so the USB core
487 * notices the Compliance state and resets the port.
488 * This resolves an issue generated by the SN65LVPE502CP
489 * in which sometimes the port enters compliance mode
490 * caused by a delay on the host-device negotiation.
492 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
493 (pls == USB_SS_PORT_LS_COMP_MOD))
494 pls |= USB_PORT_STAT_CONNECTION;
497 /* update status field */
502 * Function for Compliance Mode Quirk.
504 * This Function verifies if all xhc USB3 ports have entered U0, if so,
505 * the compliance mode timer is deleted. A port won't enter
506 * compliance mode if it has previously entered U0.
508 void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
510 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
511 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
513 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
516 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
517 xhci->port_status_u0 |= 1 << wIndex;
518 if (xhci->port_status_u0 == all_ports_seen_u0) {
519 del_timer_sync(&xhci->comp_mode_recovery_timer);
520 xhci_dbg(xhci, "All USB3 ports have entered U0 already!\n");
521 xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted.\n");
526 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
527 u16 wIndex, char *buf, u16 wLength)
529 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
534 __le32 __iomem **port_array;
536 struct xhci_bus_state *bus_state;
539 max_ports = xhci_get_ports(hcd, &port_array);
540 bus_state = &xhci->bus_state[hcd_index(hcd)];
542 spin_lock_irqsave(&xhci->lock, flags);
545 /* No power source, over-current reported per port */
548 case GetHubDescriptor:
549 /* Check to make sure userspace is asking for the USB 3.0 hub
550 * descriptor for the USB 3.0 roothub. If not, we stall the
551 * endpoint, like external hubs do.
553 if (hcd->speed == HCD_USB3 &&
554 (wLength < USB_DT_SS_HUB_SIZE ||
555 wValue != (USB_DT_SS_HUB << 8))) {
556 xhci_dbg(xhci, "Wrong hub descriptor type for "
557 "USB 3.0 roothub.\n");
560 xhci_hub_descriptor(hcd, xhci,
561 (struct usb_hub_descriptor *) buf);
563 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
564 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
567 if (hcd->speed != HCD_USB3)
570 memcpy(buf, &usb_bos_descriptor,
571 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
572 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
573 buf[12] = HCS_U1_LATENCY(temp);
574 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
576 spin_unlock_irqrestore(&xhci->lock, flags);
577 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
579 if (!wIndex || wIndex > max_ports)
583 temp = xhci_readl(xhci, port_array[wIndex]);
584 if (temp == 0xffffffff) {
588 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
590 /* wPortChange bits */
592 status |= USB_PORT_STAT_C_CONNECTION << 16;
594 status |= USB_PORT_STAT_C_ENABLE << 16;
595 if ((temp & PORT_OCC))
596 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
597 if ((temp & PORT_RC))
598 status |= USB_PORT_STAT_C_RESET << 16;
600 if (hcd->speed == HCD_USB3) {
601 /* Port link change with port in resume state should not be
602 * reported to usbcore, as this is an internal state to be
603 * handled by xhci driver. Reporting PLC to usbcore may
604 * cause usbcore clearing PLC first and port change event
605 * irq won't be generated.
607 if ((temp & PORT_PLC) &&
608 (temp & PORT_PLS_MASK) != XDEV_RESUME)
609 status |= USB_PORT_STAT_C_LINK_STATE << 16;
610 if ((temp & PORT_WRC))
611 status |= USB_PORT_STAT_C_BH_RESET << 16;
612 if ((temp & PORT_CEC))
613 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
616 if (hcd->speed != HCD_USB3) {
617 if ((temp & PORT_PLS_MASK) == XDEV_U3
618 && (temp & PORT_POWER))
619 status |= USB_PORT_STAT_SUSPEND;
621 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
622 !DEV_SUPERSPEED(temp)) {
623 if ((temp & PORT_RESET) || !(temp & PORT_PE))
625 if (time_after_eq(jiffies,
626 bus_state->resume_done[wIndex])) {
627 xhci_dbg(xhci, "Resume USB2 port %d\n",
629 bus_state->resume_done[wIndex] = 0;
630 xhci_set_link_state(xhci, port_array, wIndex,
632 xhci_dbg(xhci, "set port %d resume\n",
634 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
637 xhci_dbg(xhci, "slot_id is zero\n");
640 xhci_ring_device(xhci, slot_id);
641 bus_state->port_c_suspend |= 1 << wIndex;
642 bus_state->suspended_ports &= ~(1 << wIndex);
645 * The resume has been signaling for less than
646 * 20ms. Report the port status as SUSPEND,
647 * let the usbcore check port status again
648 * and clear resume signaling later.
650 status |= USB_PORT_STAT_SUSPEND;
653 if ((temp & PORT_PLS_MASK) == XDEV_U0
654 && (temp & PORT_POWER)
655 && (bus_state->suspended_ports & (1 << wIndex))) {
656 bus_state->suspended_ports &= ~(1 << wIndex);
657 if (hcd->speed != HCD_USB3)
658 bus_state->port_c_suspend |= 1 << wIndex;
660 if (temp & PORT_CONNECT) {
661 status |= USB_PORT_STAT_CONNECTION;
662 status |= xhci_port_speed(temp);
665 status |= USB_PORT_STAT_ENABLE;
667 status |= USB_PORT_STAT_OVERCURRENT;
668 if (temp & PORT_RESET)
669 status |= USB_PORT_STAT_RESET;
670 if (temp & PORT_POWER) {
671 if (hcd->speed == HCD_USB3)
672 status |= USB_SS_PORT_STAT_POWER;
674 status |= USB_PORT_STAT_POWER;
676 /* Update Port Link State for super speed ports*/
677 if (hcd->speed == HCD_USB3) {
678 xhci_hub_report_link_state(xhci, &status, temp);
680 * Verify if all USB3 Ports Have entered U0 already.
681 * Delete Compliance Mode Timer if so.
683 xhci_del_comp_mod_timer(xhci, temp, wIndex);
685 if (bus_state->port_c_suspend & (1 << wIndex))
686 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
687 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
688 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
691 if (wValue == USB_PORT_FEAT_LINK_STATE)
692 link_state = (wIndex & 0xff00) >> 3;
694 if (!wIndex || wIndex > max_ports)
697 temp = xhci_readl(xhci, port_array[wIndex]);
698 if (temp == 0xffffffff) {
702 temp = xhci_port_state_to_neutral(temp);
703 /* FIXME: What new port features do we need to support? */
705 case USB_PORT_FEAT_SUSPEND:
706 temp = xhci_readl(xhci, port_array[wIndex]);
707 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
708 /* Resume the port to U0 first */
709 xhci_set_link_state(xhci, port_array, wIndex,
711 spin_unlock_irqrestore(&xhci->lock, flags);
713 spin_lock_irqsave(&xhci->lock, flags);
715 /* In spec software should not attempt to suspend
716 * a port unless the port reports that it is in the
717 * enabled (PED = ‘1’,PLS < ‘3’) state.
719 temp = xhci_readl(xhci, port_array[wIndex]);
720 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
721 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
722 xhci_warn(xhci, "USB core suspending device "
723 "not in U0/U1/U2.\n");
727 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
730 xhci_warn(xhci, "slot_id is zero\n");
733 /* unlock to execute stop endpoint commands */
734 spin_unlock_irqrestore(&xhci->lock, flags);
735 xhci_stop_device(xhci, slot_id, 1);
736 spin_lock_irqsave(&xhci->lock, flags);
738 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
740 spin_unlock_irqrestore(&xhci->lock, flags);
741 msleep(10); /* wait device to enter */
742 spin_lock_irqsave(&xhci->lock, flags);
744 temp = xhci_readl(xhci, port_array[wIndex]);
745 bus_state->suspended_ports |= 1 << wIndex;
747 case USB_PORT_FEAT_LINK_STATE:
748 temp = xhci_readl(xhci, port_array[wIndex]);
751 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
752 xhci_dbg(xhci, "Disable port %d\n", wIndex);
753 temp = xhci_port_state_to_neutral(temp);
755 * Clear all change bits, so that we get a new
758 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
759 PORT_OCC | PORT_RC | PORT_PLC |
761 xhci_writel(xhci, temp | PORT_PE,
763 temp = xhci_readl(xhci, port_array[wIndex]);
767 /* Put link in RxDetect (enable port) */
768 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
769 xhci_dbg(xhci, "Enable port %d\n", wIndex);
770 xhci_set_link_state(xhci, port_array, wIndex,
772 temp = xhci_readl(xhci, port_array[wIndex]);
776 /* Software should not attempt to set
777 * port link state above '3' (U3) and the port
780 if ((temp & PORT_PE) == 0 ||
781 (link_state > USB_SS_PORT_LS_U3)) {
782 xhci_warn(xhci, "Cannot set link state.\n");
786 if (link_state == USB_SS_PORT_LS_U3) {
787 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
790 /* unlock to execute stop endpoint
792 spin_unlock_irqrestore(&xhci->lock,
794 xhci_stop_device(xhci, slot_id, 1);
795 spin_lock_irqsave(&xhci->lock, flags);
799 xhci_set_link_state(xhci, port_array, wIndex,
802 spin_unlock_irqrestore(&xhci->lock, flags);
803 msleep(20); /* wait device to enter */
804 spin_lock_irqsave(&xhci->lock, flags);
806 temp = xhci_readl(xhci, port_array[wIndex]);
807 if (link_state == USB_SS_PORT_LS_U3)
808 bus_state->suspended_ports |= 1 << wIndex;
810 case USB_PORT_FEAT_POWER:
812 * Turn on ports, even if there isn't per-port switching.
813 * HC will report connect events even before this is set.
814 * However, khubd will ignore the roothub events until
815 * the roothub is registered.
817 xhci_writel(xhci, temp | PORT_POWER,
820 temp = xhci_readl(xhci, port_array[wIndex]);
821 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
823 case USB_PORT_FEAT_RESET:
824 temp = (temp | PORT_RESET);
825 xhci_writel(xhci, temp, port_array[wIndex]);
827 temp = xhci_readl(xhci, port_array[wIndex]);
828 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
830 case USB_PORT_FEAT_BH_PORT_RESET:
832 xhci_writel(xhci, temp, port_array[wIndex]);
834 temp = xhci_readl(xhci, port_array[wIndex]);
839 /* unblock any posted writes */
840 temp = xhci_readl(xhci, port_array[wIndex]);
842 case ClearPortFeature:
843 if (!wIndex || wIndex > max_ports)
846 temp = xhci_readl(xhci, port_array[wIndex]);
847 if (temp == 0xffffffff) {
851 /* FIXME: What new port features do we need to support? */
852 temp = xhci_port_state_to_neutral(temp);
854 case USB_PORT_FEAT_SUSPEND:
855 temp = xhci_readl(xhci, port_array[wIndex]);
856 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
857 xhci_dbg(xhci, "PORTSC %04x\n", temp);
858 if (temp & PORT_RESET)
860 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
861 if ((temp & PORT_PE) == 0)
864 xhci_set_link_state(xhci, port_array, wIndex,
866 spin_unlock_irqrestore(&xhci->lock, flags);
868 spin_lock_irqsave(&xhci->lock, flags);
869 xhci_set_link_state(xhci, port_array, wIndex,
872 bus_state->port_c_suspend |= 1 << wIndex;
874 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
877 xhci_dbg(xhci, "slot_id is zero\n");
880 xhci_ring_device(xhci, slot_id);
882 case USB_PORT_FEAT_C_SUSPEND:
883 bus_state->port_c_suspend &= ~(1 << wIndex);
884 case USB_PORT_FEAT_C_RESET:
885 case USB_PORT_FEAT_C_BH_PORT_RESET:
886 case USB_PORT_FEAT_C_CONNECTION:
887 case USB_PORT_FEAT_C_OVER_CURRENT:
888 case USB_PORT_FEAT_C_ENABLE:
889 case USB_PORT_FEAT_C_PORT_LINK_STATE:
890 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
891 xhci_clear_port_change_bit(xhci, wValue, wIndex,
892 port_array[wIndex], temp);
894 case USB_PORT_FEAT_ENABLE:
895 xhci_disable_port(hcd, xhci, wIndex,
896 port_array[wIndex], temp);
904 /* "stall" on error */
907 spin_unlock_irqrestore(&xhci->lock, flags);
912 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
913 * Ports are 0-indexed from the HCD point of view,
914 * and 1-indexed from the USB core pointer of view.
916 * Note that the status change bits will be cleared as soon as a port status
917 * change event is generated, so we use the saved status from that event.
919 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
925 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
927 __le32 __iomem **port_array;
928 struct xhci_bus_state *bus_state;
929 bool reset_change = false;
931 max_ports = xhci_get_ports(hcd, &port_array);
932 bus_state = &xhci->bus_state[hcd_index(hcd)];
934 /* Initial status is no changes */
935 retval = (max_ports + 8) / 8;
936 memset(buf, 0, retval);
939 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
941 spin_lock_irqsave(&xhci->lock, flags);
942 /* For each port, did anything change? If so, set that bit in buf. */
943 for (i = 0; i < max_ports; i++) {
944 temp = xhci_readl(xhci, port_array[i]);
945 if (temp == 0xffffffff) {
949 if ((temp & mask) != 0 ||
950 (bus_state->port_c_suspend & 1 << i) ||
951 (bus_state->resume_done[i] && time_after_eq(
952 jiffies, bus_state->resume_done[i]))) {
953 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
956 if ((temp & PORT_RC))
959 if (!status && !reset_change) {
960 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
961 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
963 spin_unlock_irqrestore(&xhci->lock, flags);
964 return status ? retval : 0;
969 int xhci_bus_suspend(struct usb_hcd *hcd)
971 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
972 int max_ports, port_index;
973 __le32 __iomem **port_array;
974 struct xhci_bus_state *bus_state;
977 max_ports = xhci_get_ports(hcd, &port_array);
978 bus_state = &xhci->bus_state[hcd_index(hcd)];
980 spin_lock_irqsave(&xhci->lock, flags);
982 if (hcd->self.root_hub->do_remote_wakeup) {
983 port_index = max_ports;
984 while (port_index--) {
985 if (bus_state->resume_done[port_index] != 0) {
986 spin_unlock_irqrestore(&xhci->lock, flags);
987 xhci_dbg(xhci, "suspend failed because "
988 "port %d is resuming\n",
995 port_index = max_ports;
996 bus_state->bus_suspended = 0;
997 while (port_index--) {
998 /* suspend the port if the port is not suspended */
1002 t1 = xhci_readl(xhci, port_array[port_index]);
1003 t2 = xhci_port_state_to_neutral(t1);
1005 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1006 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1007 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1010 spin_unlock_irqrestore(&xhci->lock, flags);
1011 xhci_stop_device(xhci, slot_id, 1);
1012 spin_lock_irqsave(&xhci->lock, flags);
1014 t2 &= ~PORT_PLS_MASK;
1015 t2 |= PORT_LINK_STROBE | XDEV_U3;
1016 set_bit(port_index, &bus_state->bus_suspended);
1018 if (hcd->self.root_hub->do_remote_wakeup) {
1019 if (t1 & PORT_CONNECT) {
1020 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1021 t2 &= ~PORT_WKCONN_E;
1023 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1024 t2 &= ~PORT_WKDISC_E;
1027 t2 &= ~PORT_WAKE_BITS;
1029 t1 = xhci_port_state_to_neutral(t1);
1031 xhci_writel(xhci, t2, port_array[port_index]);
1033 hcd->state = HC_STATE_SUSPENDED;
1034 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1035 spin_unlock_irqrestore(&xhci->lock, flags);
1040 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1041 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1042 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1044 static bool xhci_port_missing_cas_quirk(int port_index,
1045 __le32 __iomem **port_array)
1049 portsc = readl(port_array[port_index]);
1051 /* if any of these are set we are not stuck */
1052 if (portsc & (PORT_CONNECT | PORT_CAS))
1055 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1056 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1059 /* clear wakeup/change bits, and do a warm port reset */
1060 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1062 writel(portsc, port_array[port_index]);
1064 readl(port_array[port_index]);
1068 int xhci_bus_resume(struct usb_hcd *hcd)
1070 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1071 int max_ports, port_index;
1072 __le32 __iomem **port_array;
1073 struct xhci_bus_state *bus_state;
1075 unsigned long flags;
1077 max_ports = xhci_get_ports(hcd, &port_array);
1078 bus_state = &xhci->bus_state[hcd_index(hcd)];
1080 if (time_before(jiffies, bus_state->next_statechange))
1083 spin_lock_irqsave(&xhci->lock, flags);
1084 if (!HCD_HW_ACCESSIBLE(hcd)) {
1085 spin_unlock_irqrestore(&xhci->lock, flags);
1089 /* delay the irqs */
1090 temp = xhci_readl(xhci, &xhci->op_regs->command);
1092 xhci_writel(xhci, temp, &xhci->op_regs->command);
1094 port_index = max_ports;
1095 while (port_index--) {
1096 /* Check whether need resume ports. If needed
1097 resume port and disable remote wakeup */
1101 temp = xhci_readl(xhci, port_array[port_index]);
1103 /* warm reset CAS limited ports stuck in polling/compliance */
1104 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1105 (hcd->speed >= HCD_USB3) &&
1106 xhci_port_missing_cas_quirk(port_index, port_array)) {
1107 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1110 if (DEV_SUPERSPEED(temp))
1111 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1113 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1114 if (test_bit(port_index, &bus_state->bus_suspended) &&
1115 (temp & PORT_PLS_MASK)) {
1116 if (DEV_SUPERSPEED(temp)) {
1117 xhci_set_link_state(xhci, port_array,
1118 port_index, XDEV_U0);
1120 xhci_set_link_state(xhci, port_array,
1121 port_index, XDEV_RESUME);
1123 spin_unlock_irqrestore(&xhci->lock, flags);
1125 spin_lock_irqsave(&xhci->lock, flags);
1127 xhci_set_link_state(xhci, port_array,
1128 port_index, XDEV_U0);
1130 /* wait for the port to enter U0 and report port link
1133 spin_unlock_irqrestore(&xhci->lock, flags);
1135 spin_lock_irqsave(&xhci->lock, flags);
1138 xhci_test_and_clear_bit(xhci, port_array, port_index,
1141 slot_id = xhci_find_slot_id_by_port(hcd,
1142 xhci, port_index + 1);
1144 xhci_ring_device(xhci, slot_id);
1146 xhci_writel(xhci, temp, port_array[port_index]);
1149 (void) xhci_readl(xhci, &xhci->op_regs->command);
1151 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1152 /* re-enable irqs */
1153 temp = xhci_readl(xhci, &xhci->op_regs->command);
1155 xhci_writel(xhci, temp, &xhci->op_regs->command);
1156 temp = xhci_readl(xhci, &xhci->op_regs->command);
1158 spin_unlock_irqrestore(&xhci->lock, flags);
1162 #endif /* CONFIG_PM */